1*4e411ee4SZhengjun Xing[ 2*4e411ee4SZhengjun Xing { 3*4e411ee4SZhengjun Xing "BriefDescription": "IMC Clockticks at DCLK frequency", 4*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 5*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 6*4e411ee4SZhengjun Xing "EventCode": "0x01", 7*4e411ee4SZhengjun Xing "EventName": "UNC_M_CLOCKTICKS", 8*4e411ee4SZhengjun Xing "PerPkg": "1", 9*4e411ee4SZhengjun Xing "UMask": "0x0000000001", 10*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 11*4e411ee4SZhengjun Xing "Unit": "iMC" 12*4e411ee4SZhengjun Xing }, 13*4e411ee4SZhengjun Xing { 14*4e411ee4SZhengjun Xing "BriefDescription": "IMC Clockticks at HCLK frequency", 15*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 16*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 17*4e411ee4SZhengjun Xing "EventCode": "0x01", 18*4e411ee4SZhengjun Xing "EventName": "UNC_M_HCLOCKTICKS", 19*4e411ee4SZhengjun Xing "PerPkg": "1", 20*4e411ee4SZhengjun Xing "Unit": "iMC" 21*4e411ee4SZhengjun Xing }, 22*4e411ee4SZhengjun Xing { 23*4e411ee4SZhengjun Xing "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)", 24*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 25*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 26*4e411ee4SZhengjun Xing "EventCode": "0x05", 27*4e411ee4SZhengjun Xing "EventName": "UNC_M_CAS_COUNT.RD_REG", 28*4e411ee4SZhengjun Xing "PerPkg": "1", 29*4e411ee4SZhengjun Xing "UMask": "0x00000000c1", 30*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 31*4e411ee4SZhengjun Xing "Unit": "iMC" 32*4e411ee4SZhengjun Xing }, 33*4e411ee4SZhengjun Xing { 34*4e411ee4SZhengjun Xing "BriefDescription": "DRAM underfill read CAS commands issued", 35*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 36*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 37*4e411ee4SZhengjun Xing "EventCode": "0x05", 38*4e411ee4SZhengjun Xing "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", 39*4e411ee4SZhengjun Xing "PerPkg": "1", 40*4e411ee4SZhengjun Xing "UMask": "0x00000000c4", 41*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 42*4e411ee4SZhengjun Xing "Unit": "iMC" 43*4e411ee4SZhengjun Xing }, 44*4e411ee4SZhengjun Xing { 45*4e411ee4SZhengjun Xing "BriefDescription": "All DRAM read CAS commands issued (including underfills)", 46*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 47*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 48*4e411ee4SZhengjun Xing "EventCode": "0x05", 49*4e411ee4SZhengjun Xing "EventName": "UNC_M_CAS_COUNT.RD", 50*4e411ee4SZhengjun Xing "PerPkg": "1", 51*4e411ee4SZhengjun Xing "UMask": "0x00000000cf", 52*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 53*4e411ee4SZhengjun Xing "Unit": "iMC" 54*4e411ee4SZhengjun Xing }, 55*4e411ee4SZhengjun Xing { 56*4e411ee4SZhengjun Xing "BriefDescription": "All DRAM write CAS commands issued", 57*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 58*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 59*4e411ee4SZhengjun Xing "EventCode": "0x05", 60*4e411ee4SZhengjun Xing "EventName": "UNC_M_CAS_COUNT.WR", 61*4e411ee4SZhengjun Xing "PerPkg": "1", 62*4e411ee4SZhengjun Xing "UMask": "0x00000000f0", 63*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 64*4e411ee4SZhengjun Xing "Unit": "iMC" 65*4e411ee4SZhengjun Xing }, 66*4e411ee4SZhengjun Xing { 67*4e411ee4SZhengjun Xing "BriefDescription": "Read Pending Queue Allocations", 68*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 69*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 70*4e411ee4SZhengjun Xing "EventCode": "0x10", 71*4e411ee4SZhengjun Xing "EventName": "UNC_M_RPQ_INSERTS.PCH0", 72*4e411ee4SZhengjun Xing "PerPkg": "1", 73*4e411ee4SZhengjun Xing "UMask": "0x0000000001", 74*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 75*4e411ee4SZhengjun Xing "Unit": "iMC" 76*4e411ee4SZhengjun Xing }, 77*4e411ee4SZhengjun Xing { 78*4e411ee4SZhengjun Xing "BriefDescription": "Read Pending Queue Allocations", 79*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 80*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 81*4e411ee4SZhengjun Xing "EventCode": "0x10", 82*4e411ee4SZhengjun Xing "EventName": "UNC_M_RPQ_INSERTS.PCH1", 83*4e411ee4SZhengjun Xing "PerPkg": "1", 84*4e411ee4SZhengjun Xing "UMask": "0x0000000002", 85*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 86*4e411ee4SZhengjun Xing "Unit": "iMC" 87*4e411ee4SZhengjun Xing }, 88*4e411ee4SZhengjun Xing { 89*4e411ee4SZhengjun Xing "BriefDescription": "Write Pending Queue Allocations", 90*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 91*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 92*4e411ee4SZhengjun Xing "EventCode": "0x20", 93*4e411ee4SZhengjun Xing "EventName": "UNC_M_WPQ_INSERTS.PCH0", 94*4e411ee4SZhengjun Xing "PerPkg": "1", 95*4e411ee4SZhengjun Xing "UMask": "0x0000000001", 96*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 97*4e411ee4SZhengjun Xing "Unit": "iMC" 98*4e411ee4SZhengjun Xing }, 99*4e411ee4SZhengjun Xing { 100*4e411ee4SZhengjun Xing "BriefDescription": "Write Pending Queue Allocations", 101*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 102*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 103*4e411ee4SZhengjun Xing "EventCode": "0x20", 104*4e411ee4SZhengjun Xing "EventName": "UNC_M_WPQ_INSERTS.PCH1", 105*4e411ee4SZhengjun Xing "PerPkg": "1", 106*4e411ee4SZhengjun Xing "UMask": "0x0000000002", 107*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 108*4e411ee4SZhengjun Xing "Unit": "iMC" 109*4e411ee4SZhengjun Xing }, 110*4e411ee4SZhengjun Xing { 111*4e411ee4SZhengjun Xing "BriefDescription": "Read Pending Queue Occupancy", 112*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 113*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 114*4e411ee4SZhengjun Xing "EventCode": "0x80", 115*4e411ee4SZhengjun Xing "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0", 116*4e411ee4SZhengjun Xing "PerPkg": "1", 117*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 118*4e411ee4SZhengjun Xing "Unit": "iMC" 119*4e411ee4SZhengjun Xing }, 120*4e411ee4SZhengjun Xing { 121*4e411ee4SZhengjun Xing "BriefDescription": "Read Pending Queue Occupancy", 122*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 123*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 124*4e411ee4SZhengjun Xing "EventCode": "0x81", 125*4e411ee4SZhengjun Xing "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1", 126*4e411ee4SZhengjun Xing "PerPkg": "1", 127*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 128*4e411ee4SZhengjun Xing "Unit": "iMC" 129*4e411ee4SZhengjun Xing }, 130*4e411ee4SZhengjun Xing { 131*4e411ee4SZhengjun Xing "BriefDescription": "Write Pending Queue Occupancy", 132*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 133*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 134*4e411ee4SZhengjun Xing "EventCode": "0x82", 135*4e411ee4SZhengjun Xing "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0", 136*4e411ee4SZhengjun Xing "PerPkg": "1", 137*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 138*4e411ee4SZhengjun Xing "Unit": "iMC" 139*4e411ee4SZhengjun Xing }, 140*4e411ee4SZhengjun Xing { 141*4e411ee4SZhengjun Xing "BriefDescription": "Write Pending Queue Occupancy", 142*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 143*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 144*4e411ee4SZhengjun Xing "EventCode": "0x83", 145*4e411ee4SZhengjun Xing "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1", 146*4e411ee4SZhengjun Xing "PerPkg": "1", 147*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 148*4e411ee4SZhengjun Xing "Unit": "iMC" 149*4e411ee4SZhengjun Xing }, 150*4e411ee4SZhengjun Xing { 151*4e411ee4SZhengjun Xing "BriefDescription": "PMM Read Pending Queue occupancy", 152*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 153*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 154*4e411ee4SZhengjun Xing "EventCode": "0xe0", 155*4e411ee4SZhengjun Xing "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH0", 156*4e411ee4SZhengjun Xing "PerPkg": "1", 157*4e411ee4SZhengjun Xing "UMask": "0x0000000001", 158*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 159*4e411ee4SZhengjun Xing "Unit": "iMC" 160*4e411ee4SZhengjun Xing }, 161*4e411ee4SZhengjun Xing { 162*4e411ee4SZhengjun Xing "BriefDescription": "PMM Read Pending Queue occupancy", 163*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 164*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 165*4e411ee4SZhengjun Xing "EventCode": "0xe0", 166*4e411ee4SZhengjun Xing "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH1", 167*4e411ee4SZhengjun Xing "PerPkg": "1", 168*4e411ee4SZhengjun Xing "UMask": "0x0000000002", 169*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 170*4e411ee4SZhengjun Xing "Unit": "iMC" 171*4e411ee4SZhengjun Xing }, 172*4e411ee4SZhengjun Xing { 173*4e411ee4SZhengjun Xing "BriefDescription": "PMM Read Pending Queue inserts", 174*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 175*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 176*4e411ee4SZhengjun Xing "EventCode": "0xe3", 177*4e411ee4SZhengjun Xing "EventName": "UNC_M_PMM_RPQ_INSERTS", 178*4e411ee4SZhengjun Xing "PerPkg": "1", 179*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 180*4e411ee4SZhengjun Xing "Unit": "iMC" 181*4e411ee4SZhengjun Xing }, 182*4e411ee4SZhengjun Xing { 183*4e411ee4SZhengjun Xing "BriefDescription": "PMM Write Pending Queue Occupancy", 184*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 185*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 186*4e411ee4SZhengjun Xing "EventCode": "0xe4", 187*4e411ee4SZhengjun Xing "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL", 188*4e411ee4SZhengjun Xing "PerPkg": "1", 189*4e411ee4SZhengjun Xing "UMask": "0x03", 190*4e411ee4SZhengjun Xing "Unit": "iMC" 191*4e411ee4SZhengjun Xing }, 192*4e411ee4SZhengjun Xing { 193*4e411ee4SZhengjun Xing "BriefDescription": "PMM Write Pending Queue inserts", 194*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 195*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 196*4e411ee4SZhengjun Xing "EventCode": "0xe7", 197*4e411ee4SZhengjun Xing "EventName": "UNC_M_PMM_WPQ_INSERTS", 198*4e411ee4SZhengjun Xing "PerPkg": "1", 199*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 200*4e411ee4SZhengjun Xing "Unit": "iMC" 201*4e411ee4SZhengjun Xing }, 202*4e411ee4SZhengjun Xing { 203*4e411ee4SZhengjun Xing "BriefDescription": "PMM Write Pending Queue Occupancy", 204*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 205*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 206*4e411ee4SZhengjun Xing "EventCode": "0xE4", 207*4e411ee4SZhengjun Xing "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH0", 208*4e411ee4SZhengjun Xing "PerPkg": "1", 209*4e411ee4SZhengjun Xing "UMask": "0x0000000001", 210*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 211*4e411ee4SZhengjun Xing "Unit": "iMC" 212*4e411ee4SZhengjun Xing }, 213*4e411ee4SZhengjun Xing { 214*4e411ee4SZhengjun Xing "BriefDescription": "PMM Write Pending Queue Occupancy", 215*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 216*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 217*4e411ee4SZhengjun Xing "EventCode": "0xE4", 218*4e411ee4SZhengjun Xing "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH1", 219*4e411ee4SZhengjun Xing "PerPkg": "1", 220*4e411ee4SZhengjun Xing "UMask": "0x0000000002", 221*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 222*4e411ee4SZhengjun Xing "Unit": "iMC" 223*4e411ee4SZhengjun Xing }, 224*4e411ee4SZhengjun Xing { 225*4e411ee4SZhengjun Xing "BriefDescription": "Activate due to read, write, underfill, or bypass", 226*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 227*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 228*4e411ee4SZhengjun Xing "EventCode": "0x02", 229*4e411ee4SZhengjun Xing "EventName": "UNC_M_ACT_COUNT.ALL", 230*4e411ee4SZhengjun Xing "PerPkg": "1", 231*4e411ee4SZhengjun Xing "UMask": "0x00000000ff", 232*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 233*4e411ee4SZhengjun Xing "Unit": "iMC" 234*4e411ee4SZhengjun Xing }, 235*4e411ee4SZhengjun Xing { 236*4e411ee4SZhengjun Xing "BriefDescription": "Precharge due to read on page miss", 237*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 238*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 239*4e411ee4SZhengjun Xing "EventCode": "0x03", 240*4e411ee4SZhengjun Xing "EventName": "UNC_M_PRE_COUNT.RD", 241*4e411ee4SZhengjun Xing "PerPkg": "1", 242*4e411ee4SZhengjun Xing "UMask": "0x0000000011", 243*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 244*4e411ee4SZhengjun Xing "Unit": "iMC" 245*4e411ee4SZhengjun Xing }, 246*4e411ee4SZhengjun Xing { 247*4e411ee4SZhengjun Xing "BriefDescription": "Precharge due to write on page miss", 248*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 249*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 250*4e411ee4SZhengjun Xing "EventCode": "0x03", 251*4e411ee4SZhengjun Xing "EventName": "UNC_M_PRE_COUNT.WR", 252*4e411ee4SZhengjun Xing "PerPkg": "1", 253*4e411ee4SZhengjun Xing "UMask": "0x0000000022", 254*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 255*4e411ee4SZhengjun Xing "Unit": "iMC" 256*4e411ee4SZhengjun Xing }, 257*4e411ee4SZhengjun Xing { 258*4e411ee4SZhengjun Xing "BriefDescription": "DRAM Precharge commands. : Precharge due to (?)", 259*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 260*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 261*4e411ee4SZhengjun Xing "EventCode": "0x03", 262*4e411ee4SZhengjun Xing "EventName": "UNC_M_PRE_COUNT.PGT", 263*4e411ee4SZhengjun Xing "PerPkg": "1", 264*4e411ee4SZhengjun Xing "UMask": "0x0000000088", 265*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 266*4e411ee4SZhengjun Xing "Unit": "iMC" 267*4e411ee4SZhengjun Xing }, 268*4e411ee4SZhengjun Xing { 269*4e411ee4SZhengjun Xing "BriefDescription": "Precharge due to read, write, underfill, or PGT", 270*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 271*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 272*4e411ee4SZhengjun Xing "EventCode": "0x03", 273*4e411ee4SZhengjun Xing "EventName": "UNC_M_PRE_COUNT.ALL", 274*4e411ee4SZhengjun Xing "PerPkg": "1", 275*4e411ee4SZhengjun Xing "UMask": "0x00000000ff", 276*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 277*4e411ee4SZhengjun Xing "Unit": "iMC" 278*4e411ee4SZhengjun Xing }, 279*4e411ee4SZhengjun Xing { 280*4e411ee4SZhengjun Xing "BriefDescription": "All DRAM CAS commands issued", 281*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 282*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 283*4e411ee4SZhengjun Xing "EventCode": "0x05", 284*4e411ee4SZhengjun Xing "EventName": "UNC_M_CAS_COUNT.ALL", 285*4e411ee4SZhengjun Xing "PerPkg": "1", 286*4e411ee4SZhengjun Xing "UMask": "0x00000000ff", 287*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 288*4e411ee4SZhengjun Xing "Unit": "iMC" 289*4e411ee4SZhengjun Xing }, 290*4e411ee4SZhengjun Xing { 291*4e411ee4SZhengjun Xing "BriefDescription": "DRAM RD_CAS and WR_CAS Commands", 292*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 293*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 294*4e411ee4SZhengjun Xing "EventCode": "0x05", 295*4e411ee4SZhengjun Xing "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG", 296*4e411ee4SZhengjun Xing "PerPkg": "1", 297*4e411ee4SZhengjun Xing "UMask": "0x00000000c2", 298*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 299*4e411ee4SZhengjun Xing "Unit": "iMC" 300*4e411ee4SZhengjun Xing }, 301*4e411ee4SZhengjun Xing { 302*4e411ee4SZhengjun Xing "BriefDescription": "DRAM RD_CAS and WR_CAS Commands", 303*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 304*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 305*4e411ee4SZhengjun Xing "EventCode": "0x05", 306*4e411ee4SZhengjun Xing "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL", 307*4e411ee4SZhengjun Xing "PerPkg": "1", 308*4e411ee4SZhengjun Xing "UMask": "0x00000000c8", 309*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 310*4e411ee4SZhengjun Xing "Unit": "iMC" 311*4e411ee4SZhengjun Xing }, 312*4e411ee4SZhengjun Xing { 313*4e411ee4SZhengjun Xing "BriefDescription": "DRAM RD_CAS and WR_CAS Commands", 314*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 315*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 316*4e411ee4SZhengjun Xing "EventCode": "0x05", 317*4e411ee4SZhengjun Xing "EventName": "UNC_M_CAS_COUNT.WR_PRE", 318*4e411ee4SZhengjun Xing "PerPkg": "1", 319*4e411ee4SZhengjun Xing "UMask": "0x00000000e0", 320*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 321*4e411ee4SZhengjun Xing "Unit": "iMC" 322*4e411ee4SZhengjun Xing }, 323*4e411ee4SZhengjun Xing { 324*4e411ee4SZhengjun Xing "BriefDescription": "PMM Read Pending Queue Occupancy", 325*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 326*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 327*4e411ee4SZhengjun Xing "EventCode": "0xe0", 328*4e411ee4SZhengjun Xing "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH0", 329*4e411ee4SZhengjun Xing "PerPkg": "1", 330*4e411ee4SZhengjun Xing "UMask": "0x0000000004", 331*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 332*4e411ee4SZhengjun Xing "Unit": "iMC" 333*4e411ee4SZhengjun Xing }, 334*4e411ee4SZhengjun Xing { 335*4e411ee4SZhengjun Xing "BriefDescription": "PMM Read Pending Queue Occupancy", 336*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 337*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 338*4e411ee4SZhengjun Xing "EventCode": "0xe0", 339*4e411ee4SZhengjun Xing "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH1", 340*4e411ee4SZhengjun Xing "PerPkg": "1", 341*4e411ee4SZhengjun Xing "UMask": "0x0000000008", 342*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 343*4e411ee4SZhengjun Xing "Unit": "iMC" 344*4e411ee4SZhengjun Xing }, 345*4e411ee4SZhengjun Xing { 346*4e411ee4SZhengjun Xing "BriefDescription": "DRAM Precharge commands. : Precharge due to read", 347*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 348*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 349*4e411ee4SZhengjun Xing "EventCode": "0x03", 350*4e411ee4SZhengjun Xing "EventName": "UNC_M_PRE_COUNT.RD_PCH0", 351*4e411ee4SZhengjun Xing "PerPkg": "1", 352*4e411ee4SZhengjun Xing "UMask": "0x0000000001", 353*4e411ee4SZhengjun Xing "UMaskExt": "0x00000000", 354*4e411ee4SZhengjun Xing "Unit": "iMC" 355*4e411ee4SZhengjun Xing }, 356*4e411ee4SZhengjun Xing { 357*4e411ee4SZhengjun Xing "BriefDescription": "DRAM Precharge commands. : Precharge due to write", 358*4e411ee4SZhengjun Xing "Counter": "0,1,2,3", 359*4e411ee4SZhengjun Xing "CounterType": "PGMABLE", 360*4e411ee4SZhengjun Xing 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500