1[
2    {
3        "BriefDescription": "ARITH.FPDIV_ACTIVE",
4        "CounterMask": "1",
5        "EventCode": "0xb0",
6        "EventName": "ARITH.FPDIV_ACTIVE",
7        "SampleAfterValue": "1000003",
8        "UMask": "0x1"
9    },
10    {
11        "BriefDescription": "Counts all microcode FP assists.",
12        "EventCode": "0xc1",
13        "EventName": "ASSISTS.FP",
14        "PublicDescription": "Counts all microcode Floating Point assists.",
15        "SampleAfterValue": "100003",
16        "UMask": "0x2"
17    },
18    {
19        "BriefDescription": "ASSISTS.SSE_AVX_MIX",
20        "EventCode": "0xc1",
21        "EventName": "ASSISTS.SSE_AVX_MIX",
22        "SampleAfterValue": "1000003",
23        "UMask": "0x10"
24    },
25    {
26        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0",
27        "EventCode": "0xb3",
28        "EventName": "FP_ARITH_DISPATCHED.PORT_0",
29        "SampleAfterValue": "2000003",
30        "UMask": "0x1"
31    },
32    {
33        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1",
34        "EventCode": "0xb3",
35        "EventName": "FP_ARITH_DISPATCHED.PORT_1",
36        "SampleAfterValue": "2000003",
37        "UMask": "0x2"
38    },
39    {
40        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5",
41        "EventCode": "0xb3",
42        "EventName": "FP_ARITH_DISPATCHED.PORT_5",
43        "SampleAfterValue": "2000003",
44        "UMask": "0x4"
45    },
46    {
47        "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
48        "EventCode": "0xc7",
49        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
50        "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
51        "SampleAfterValue": "100003",
52        "UMask": "0x4"
53    },
54    {
55        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
56        "EventCode": "0xc7",
57        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
58        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
59        "SampleAfterValue": "100003",
60        "UMask": "0x8"
61    },
62    {
63        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
64        "EventCode": "0xc7",
65        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
66        "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
67        "SampleAfterValue": "100003",
68        "UMask": "0x10"
69    },
70    {
71        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
72        "EventCode": "0xc7",
73        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
74        "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
75        "SampleAfterValue": "100003",
76        "UMask": "0x20"
77    },
78    {
79        "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
80        "EventCode": "0xc7",
81        "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
82        "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
83        "SampleAfterValue": "100003",
84        "UMask": "0x40"
85    },
86    {
87        "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
88        "EventCode": "0xc7",
89        "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
90        "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
91        "SampleAfterValue": "100003",
92        "UMask": "0x80"
93    },
94    {
95        "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
96        "EventCode": "0xc7",
97        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
98        "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
99        "SampleAfterValue": "100003",
100        "UMask": "0x1"
101    },
102    {
103        "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
104        "EventCode": "0xc7",
105        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
106        "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
107        "SampleAfterValue": "100003",
108        "UMask": "0x2"
109    },
110    {
111        "BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF",
112        "EventCode": "0xcf",
113        "EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF",
114        "SampleAfterValue": "100003",
115        "UMask": "0x4"
116    },
117    {
118        "BriefDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF",
119        "EventCode": "0xcf",
120        "EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF",
121        "SampleAfterValue": "100003",
122        "UMask": "0x8"
123    },
124    {
125        "BriefDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF",
126        "EventCode": "0xcf",
127        "EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF",
128        "SampleAfterValue": "100003",
129        "UMask": "0x10"
130    },
131    {
132        "BriefDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF",
133        "EventCode": "0xcf",
134        "EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF",
135        "SampleAfterValue": "100003",
136        "UMask": "0x2"
137    },
138    {
139        "BriefDescription": "Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex.",
140        "EventCode": "0xcf",
141        "EventName": "FP_ARITH_INST_RETIRED2.SCALAR",
142        "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR",
143        "SampleAfterValue": "100003",
144        "UMask": "0x3"
145    },
146    {
147        "BriefDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF",
148        "EventCode": "0xcf",
149        "EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF",
150        "SampleAfterValue": "100003",
151        "UMask": "0x1"
152    },
153    {
154        "BriefDescription": "Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired.",
155        "EventCode": "0xcf",
156        "EventName": "FP_ARITH_INST_RETIRED2.VECTOR",
157        "PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR",
158        "SampleAfterValue": "100003",
159        "UMask": "0x1c"
160    }
161]
162