112c6385eSIan Rogers[ 212c6385eSIan Rogers { 3*9061dffdSZhengjun Xing "BriefDescription": "ARITH.FPDIV_ACTIVE", 412c6385eSIan Rogers "CollectPEBSRecord": "2", 512c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 612c6385eSIan Rogers "CounterMask": "1", 712c6385eSIan Rogers "EventCode": "0xb0", 812c6385eSIan Rogers "EventName": "ARITH.FPDIV_ACTIVE", 912c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 1012c6385eSIan Rogers "SampleAfterValue": "1000003", 1112c6385eSIan Rogers "UMask": "0x1" 1212c6385eSIan Rogers }, 1312c6385eSIan Rogers { 1412c6385eSIan Rogers "BriefDescription": "Counts all microcode FP assists.", 1512c6385eSIan Rogers "CollectPEBSRecord": "2", 1612c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 1712c6385eSIan Rogers "EventCode": "0xc1", 1812c6385eSIan Rogers "EventName": "ASSISTS.FP", 1912c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 2012c6385eSIan Rogers "PublicDescription": "Counts all microcode Floating Point assists.", 2112c6385eSIan Rogers "SampleAfterValue": "100003", 2212c6385eSIan Rogers "UMask": "0x2" 2312c6385eSIan Rogers }, 2412c6385eSIan Rogers { 25*9061dffdSZhengjun Xing "BriefDescription": "ASSISTS.SSE_AVX_MIX", 2612c6385eSIan Rogers "CollectPEBSRecord": "2", 2712c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 2812c6385eSIan Rogers "EventCode": "0xc1", 2912c6385eSIan Rogers "EventName": "ASSISTS.SSE_AVX_MIX", 3012c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 3112c6385eSIan Rogers "SampleAfterValue": "1000003", 3212c6385eSIan Rogers "UMask": "0x10" 3312c6385eSIan Rogers }, 3412c6385eSIan Rogers { 35*9061dffdSZhengjun Xing "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0", 3612c6385eSIan Rogers "CollectPEBSRecord": "2", 3712c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 3812c6385eSIan Rogers "EventCode": "0xb3", 3912c6385eSIan Rogers "EventName": "FP_ARITH_DISPATCHED.PORT_0", 4012c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 4112c6385eSIan Rogers "SampleAfterValue": "2000003", 4212c6385eSIan Rogers "UMask": "0x1" 4312c6385eSIan Rogers }, 4412c6385eSIan Rogers { 45*9061dffdSZhengjun Xing "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1", 4612c6385eSIan Rogers "CollectPEBSRecord": "2", 4712c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 4812c6385eSIan Rogers "EventCode": "0xb3", 4912c6385eSIan Rogers "EventName": "FP_ARITH_DISPATCHED.PORT_1", 5012c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 5112c6385eSIan Rogers "SampleAfterValue": "2000003", 5212c6385eSIan Rogers "UMask": "0x2" 5312c6385eSIan Rogers }, 5412c6385eSIan Rogers { 55*9061dffdSZhengjun Xing "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5", 5612c6385eSIan Rogers "CollectPEBSRecord": "2", 5712c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 5812c6385eSIan Rogers "EventCode": "0xb3", 5912c6385eSIan Rogers "EventName": "FP_ARITH_DISPATCHED.PORT_5", 6012c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 6112c6385eSIan Rogers "SampleAfterValue": "2000003", 6212c6385eSIan Rogers "UMask": "0x4" 6312c6385eSIan Rogers }, 6412c6385eSIan Rogers { 6512c6385eSIan Rogers "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 6612c6385eSIan Rogers "CollectPEBSRecord": "2", 6712c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 6812c6385eSIan Rogers "EventCode": "0xc7", 6912c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 7012c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 7112c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 7212c6385eSIan Rogers "SampleAfterValue": "100003", 7312c6385eSIan Rogers "UMask": "0x4" 7412c6385eSIan Rogers }, 7512c6385eSIan Rogers { 7612c6385eSIan Rogers "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 7712c6385eSIan Rogers "CollectPEBSRecord": "2", 7812c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 7912c6385eSIan Rogers "EventCode": "0xc7", 8012c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 8112c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 8212c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 8312c6385eSIan Rogers "SampleAfterValue": "100003", 8412c6385eSIan Rogers "UMask": "0x8" 8512c6385eSIan Rogers }, 8612c6385eSIan Rogers { 8712c6385eSIan Rogers "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 8812c6385eSIan Rogers "CollectPEBSRecord": "2", 8912c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 9012c6385eSIan Rogers "EventCode": "0xc7", 9112c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 9212c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 9312c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 9412c6385eSIan Rogers "SampleAfterValue": "100003", 9512c6385eSIan Rogers "UMask": "0x10" 9612c6385eSIan Rogers }, 9712c6385eSIan Rogers { 9812c6385eSIan Rogers "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 9912c6385eSIan Rogers "CollectPEBSRecord": "2", 10012c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 10112c6385eSIan Rogers "EventCode": "0xc7", 10212c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 10312c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 10412c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 10512c6385eSIan Rogers "SampleAfterValue": "100003", 10612c6385eSIan Rogers "UMask": "0x20" 10712c6385eSIan Rogers }, 10812c6385eSIan Rogers { 10912c6385eSIan Rogers "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 11012c6385eSIan Rogers "CollectPEBSRecord": "2", 11112c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 11212c6385eSIan Rogers "EventCode": "0xc7", 11312c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", 11412c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 11512c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 11612c6385eSIan Rogers "SampleAfterValue": "100003", 11712c6385eSIan Rogers "UMask": "0x40" 11812c6385eSIan Rogers }, 11912c6385eSIan Rogers { 12012c6385eSIan Rogers "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 12112c6385eSIan Rogers "CollectPEBSRecord": "2", 12212c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 12312c6385eSIan Rogers "EventCode": "0xc7", 12412c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", 12512c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 12612c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 12712c6385eSIan Rogers "SampleAfterValue": "100003", 12812c6385eSIan Rogers "UMask": "0x80" 12912c6385eSIan Rogers }, 13012c6385eSIan Rogers { 13112c6385eSIan Rogers "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 13212c6385eSIan Rogers "CollectPEBSRecord": "2", 13312c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 13412c6385eSIan Rogers "EventCode": "0xc7", 13512c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 13612c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 13712c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 13812c6385eSIan Rogers "SampleAfterValue": "100003", 13912c6385eSIan Rogers "UMask": "0x1" 14012c6385eSIan Rogers }, 14112c6385eSIan Rogers { 14212c6385eSIan Rogers "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 14312c6385eSIan Rogers "CollectPEBSRecord": "2", 14412c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 14512c6385eSIan Rogers "EventCode": "0xc7", 14612c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 14712c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 14812c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 14912c6385eSIan Rogers "SampleAfterValue": "100003", 15012c6385eSIan Rogers "UMask": "0x2" 15112c6385eSIan Rogers }, 15212c6385eSIan Rogers { 153*9061dffdSZhengjun Xing "BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", 15412c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 15512c6385eSIan Rogers "EventCode": "0xcf", 15612c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", 15712c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 15812c6385eSIan Rogers "SampleAfterValue": "100003", 15912c6385eSIan Rogers "UMask": "0x4" 16012c6385eSIan Rogers }, 16112c6385eSIan Rogers { 162*9061dffdSZhengjun Xing "BriefDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", 16312c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 16412c6385eSIan Rogers "EventCode": "0xcf", 16512c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", 16612c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 16712c6385eSIan Rogers "SampleAfterValue": "100003", 16812c6385eSIan Rogers "UMask": "0x8" 16912c6385eSIan Rogers }, 17012c6385eSIan Rogers { 171*9061dffdSZhengjun Xing "BriefDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", 17212c6385eSIan Rogers "CollectPEBSRecord": "2", 17312c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 17412c6385eSIan Rogers "EventCode": "0xcf", 17512c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", 17612c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 17712c6385eSIan Rogers "SampleAfterValue": "100003", 17812c6385eSIan Rogers "UMask": "0x10" 17912c6385eSIan Rogers }, 18012c6385eSIan Rogers { 181*9061dffdSZhengjun Xing "BriefDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", 18212c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 18312c6385eSIan Rogers "EventCode": "0xcf", 18412c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", 18512c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 18612c6385eSIan Rogers "SampleAfterValue": "100003", 18712c6385eSIan Rogers "UMask": "0x2" 18812c6385eSIan Rogers }, 18912c6385eSIan Rogers { 19012c6385eSIan Rogers "BriefDescription": "Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex.", 19112c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 19212c6385eSIan Rogers "EventCode": "0xcf", 19312c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED2.SCALAR", 19412c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 195*9061dffdSZhengjun Xing "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR", 19612c6385eSIan Rogers "SampleAfterValue": "100003", 19712c6385eSIan Rogers "UMask": "0x3" 19812c6385eSIan Rogers }, 19912c6385eSIan Rogers { 200*9061dffdSZhengjun Xing "BriefDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", 20112c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 20212c6385eSIan Rogers "EventCode": "0xcf", 20312c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", 20412c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 20512c6385eSIan Rogers "SampleAfterValue": "100003", 20612c6385eSIan Rogers "UMask": "0x1" 20712c6385eSIan Rogers }, 20812c6385eSIan Rogers { 20912c6385eSIan Rogers "BriefDescription": "Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired.", 21012c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 21112c6385eSIan Rogers "EventCode": "0xcf", 21212c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED2.VECTOR", 21312c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 214*9061dffdSZhengjun Xing "PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR", 21512c6385eSIan Rogers "SampleAfterValue": "100003", 21612c6385eSIan Rogers "UMask": "0x1c" 21712c6385eSIan Rogers } 21812c6385eSIan Rogers] 219