1*12c6385eSIan Rogers[ 2*12c6385eSIan Rogers { 3*12c6385eSIan Rogers "BriefDescription": "TBD", 4*12c6385eSIan Rogers "CollectPEBSRecord": "2", 5*12c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 6*12c6385eSIan Rogers "CounterMask": "1", 7*12c6385eSIan Rogers "EventCode": "0xb0", 8*12c6385eSIan Rogers "EventName": "ARITH.FPDIV_ACTIVE", 9*12c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 10*12c6385eSIan Rogers "SampleAfterValue": "1000003", 11*12c6385eSIan Rogers "UMask": "0x1" 12*12c6385eSIan Rogers }, 13*12c6385eSIan Rogers { 14*12c6385eSIan Rogers "BriefDescription": "Counts all microcode FP assists.", 15*12c6385eSIan Rogers "CollectPEBSRecord": "2", 16*12c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 17*12c6385eSIan Rogers "EventCode": "0xc1", 18*12c6385eSIan Rogers "EventName": "ASSISTS.FP", 19*12c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 20*12c6385eSIan Rogers "PublicDescription": "Counts all microcode Floating Point assists.", 21*12c6385eSIan Rogers "SampleAfterValue": "100003", 22*12c6385eSIan Rogers "UMask": "0x2" 23*12c6385eSIan Rogers }, 24*12c6385eSIan Rogers { 25*12c6385eSIan Rogers "BriefDescription": "TBD", 26*12c6385eSIan Rogers "CollectPEBSRecord": "2", 27*12c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 28*12c6385eSIan Rogers "EventCode": "0xc1", 29*12c6385eSIan Rogers "EventName": "ASSISTS.SSE_AVX_MIX", 30*12c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 31*12c6385eSIan Rogers "SampleAfterValue": "1000003", 32*12c6385eSIan Rogers "UMask": "0x10" 33*12c6385eSIan Rogers }, 34*12c6385eSIan Rogers { 35*12c6385eSIan Rogers "BriefDescription": "TBD", 36*12c6385eSIan Rogers "CollectPEBSRecord": "2", 37*12c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 38*12c6385eSIan Rogers "EventCode": "0xb3", 39*12c6385eSIan Rogers "EventName": "FP_ARITH_DISPATCHED.PORT_0", 40*12c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 41*12c6385eSIan Rogers "SampleAfterValue": "2000003", 42*12c6385eSIan Rogers "UMask": "0x1" 43*12c6385eSIan Rogers }, 44*12c6385eSIan Rogers { 45*12c6385eSIan Rogers "BriefDescription": "TBD", 46*12c6385eSIan Rogers "CollectPEBSRecord": "2", 47*12c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 48*12c6385eSIan Rogers "EventCode": "0xb3", 49*12c6385eSIan Rogers "EventName": "FP_ARITH_DISPATCHED.PORT_1", 50*12c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 51*12c6385eSIan Rogers "SampleAfterValue": "2000003", 52*12c6385eSIan Rogers "UMask": "0x2" 53*12c6385eSIan Rogers }, 54*12c6385eSIan Rogers { 55*12c6385eSIan Rogers "BriefDescription": "TBD", 56*12c6385eSIan Rogers "CollectPEBSRecord": "2", 57*12c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 58*12c6385eSIan Rogers "EventCode": "0xb3", 59*12c6385eSIan Rogers "EventName": "FP_ARITH_DISPATCHED.PORT_5", 60*12c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 61*12c6385eSIan Rogers "SampleAfterValue": "2000003", 62*12c6385eSIan Rogers "UMask": "0x4" 63*12c6385eSIan Rogers }, 64*12c6385eSIan Rogers { 65*12c6385eSIan Rogers "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 66*12c6385eSIan Rogers "CollectPEBSRecord": "2", 67*12c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 68*12c6385eSIan Rogers "EventCode": "0xc7", 69*12c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 70*12c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 71*12c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 72*12c6385eSIan Rogers "SampleAfterValue": "100003", 73*12c6385eSIan Rogers "UMask": "0x4" 74*12c6385eSIan Rogers }, 75*12c6385eSIan Rogers { 76*12c6385eSIan Rogers "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 77*12c6385eSIan Rogers "CollectPEBSRecord": "2", 78*12c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 79*12c6385eSIan Rogers "EventCode": "0xc7", 80*12c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 81*12c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 82*12c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 83*12c6385eSIan Rogers "SampleAfterValue": "100003", 84*12c6385eSIan Rogers "UMask": "0x8" 85*12c6385eSIan Rogers }, 86*12c6385eSIan Rogers { 87*12c6385eSIan Rogers "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 88*12c6385eSIan Rogers "CollectPEBSRecord": "2", 89*12c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 90*12c6385eSIan Rogers "EventCode": "0xc7", 91*12c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 92*12c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 93*12c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 94*12c6385eSIan Rogers "SampleAfterValue": "100003", 95*12c6385eSIan Rogers "UMask": "0x10" 96*12c6385eSIan Rogers }, 97*12c6385eSIan Rogers { 98*12c6385eSIan Rogers "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 99*12c6385eSIan Rogers "CollectPEBSRecord": "2", 100*12c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 101*12c6385eSIan Rogers "EventCode": "0xc7", 102*12c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 103*12c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 104*12c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 105*12c6385eSIan Rogers "SampleAfterValue": "100003", 106*12c6385eSIan Rogers "UMask": "0x20" 107*12c6385eSIan Rogers }, 108*12c6385eSIan Rogers { 109*12c6385eSIan Rogers "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 110*12c6385eSIan Rogers "CollectPEBSRecord": "2", 111*12c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 112*12c6385eSIan Rogers "EventCode": "0xc7", 113*12c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", 114*12c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 115*12c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 116*12c6385eSIan Rogers "SampleAfterValue": "100003", 117*12c6385eSIan Rogers "UMask": "0x40" 118*12c6385eSIan Rogers }, 119*12c6385eSIan Rogers { 120*12c6385eSIan Rogers "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 121*12c6385eSIan Rogers "CollectPEBSRecord": "2", 122*12c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 123*12c6385eSIan Rogers "EventCode": "0xc7", 124*12c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", 125*12c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 126*12c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 127*12c6385eSIan Rogers "SampleAfterValue": "100003", 128*12c6385eSIan Rogers "UMask": "0x80" 129*12c6385eSIan Rogers }, 130*12c6385eSIan Rogers { 131*12c6385eSIan Rogers "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 132*12c6385eSIan Rogers "CollectPEBSRecord": "2", 133*12c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 134*12c6385eSIan Rogers "EventCode": "0xc7", 135*12c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 136*12c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 137*12c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 138*12c6385eSIan Rogers "SampleAfterValue": "100003", 139*12c6385eSIan Rogers "UMask": "0x1" 140*12c6385eSIan Rogers }, 141*12c6385eSIan Rogers { 142*12c6385eSIan Rogers "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 143*12c6385eSIan Rogers "CollectPEBSRecord": "2", 144*12c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 145*12c6385eSIan Rogers "EventCode": "0xc7", 146*12c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 147*12c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 148*12c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 149*12c6385eSIan Rogers "SampleAfterValue": "100003", 150*12c6385eSIan Rogers "UMask": "0x2" 151*12c6385eSIan Rogers }, 152*12c6385eSIan Rogers { 153*12c6385eSIan Rogers "BriefDescription": "TBD", 154*12c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 155*12c6385eSIan Rogers "EventCode": "0xcf", 156*12c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", 157*12c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 158*12c6385eSIan Rogers "SampleAfterValue": "100003", 159*12c6385eSIan Rogers "UMask": "0x4" 160*12c6385eSIan Rogers }, 161*12c6385eSIan Rogers { 162*12c6385eSIan Rogers "BriefDescription": "TBD", 163*12c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 164*12c6385eSIan Rogers "EventCode": "0xcf", 165*12c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", 166*12c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 167*12c6385eSIan Rogers "SampleAfterValue": "100003", 168*12c6385eSIan Rogers "UMask": "0x8" 169*12c6385eSIan Rogers }, 170*12c6385eSIan Rogers { 171*12c6385eSIan Rogers "BriefDescription": "TBD", 172*12c6385eSIan Rogers "CollectPEBSRecord": "2", 173*12c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 174*12c6385eSIan Rogers "EventCode": "0xcf", 175*12c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", 176*12c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 177*12c6385eSIan Rogers "SampleAfterValue": "100003", 178*12c6385eSIan Rogers "UMask": "0x10" 179*12c6385eSIan Rogers }, 180*12c6385eSIan Rogers { 181*12c6385eSIan Rogers "BriefDescription": "TBD", 182*12c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 183*12c6385eSIan Rogers "EventCode": "0xcf", 184*12c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", 185*12c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 186*12c6385eSIan Rogers "SampleAfterValue": "100003", 187*12c6385eSIan Rogers "UMask": "0x2" 188*12c6385eSIan Rogers }, 189*12c6385eSIan Rogers { 190*12c6385eSIan Rogers "BriefDescription": "Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex.", 191*12c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 192*12c6385eSIan Rogers "EventCode": "0xcf", 193*12c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED2.SCALAR", 194*12c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 195*12c6385eSIan Rogers "PublicDescription": "TBD", 196*12c6385eSIan Rogers "SampleAfterValue": "100003", 197*12c6385eSIan Rogers "UMask": "0x3" 198*12c6385eSIan Rogers }, 199*12c6385eSIan Rogers { 200*12c6385eSIan Rogers "BriefDescription": "TBD", 201*12c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 202*12c6385eSIan Rogers "EventCode": "0xcf", 203*12c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", 204*12c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 205*12c6385eSIan Rogers "SampleAfterValue": "100003", 206*12c6385eSIan Rogers "UMask": "0x1" 207*12c6385eSIan Rogers }, 208*12c6385eSIan Rogers { 209*12c6385eSIan Rogers "BriefDescription": "Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired.", 210*12c6385eSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 211*12c6385eSIan Rogers "EventCode": "0xcf", 212*12c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED2.VECTOR", 213*12c6385eSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 214*12c6385eSIan Rogers "PublicDescription": "TBD", 215*12c6385eSIan Rogers "SampleAfterValue": "100003", 216*12c6385eSIan Rogers "UMask": "0x1c" 217*12c6385eSIan Rogers } 218*12c6385eSIan Rogers] 219