112c6385eSIan Rogers[ 212c6385eSIan Rogers { 39061dffdSZhengjun Xing "BriefDescription": "ARITH.FPDIV_ACTIVE", 412c6385eSIan Rogers "CounterMask": "1", 512c6385eSIan Rogers "EventCode": "0xb0", 612c6385eSIan Rogers "EventName": "ARITH.FPDIV_ACTIVE", 712c6385eSIan Rogers "SampleAfterValue": "1000003", 812c6385eSIan Rogers "UMask": "0x1" 912c6385eSIan Rogers }, 1012c6385eSIan Rogers { 1112c6385eSIan Rogers "BriefDescription": "Counts all microcode FP assists.", 1212c6385eSIan Rogers "EventCode": "0xc1", 1312c6385eSIan Rogers "EventName": "ASSISTS.FP", 1412c6385eSIan Rogers "PublicDescription": "Counts all microcode Floating Point assists.", 1512c6385eSIan Rogers "SampleAfterValue": "100003", 1612c6385eSIan Rogers "UMask": "0x2" 1712c6385eSIan Rogers }, 1812c6385eSIan Rogers { 199061dffdSZhengjun Xing "BriefDescription": "ASSISTS.SSE_AVX_MIX", 2012c6385eSIan Rogers "EventCode": "0xc1", 2112c6385eSIan Rogers "EventName": "ASSISTS.SSE_AVX_MIX", 2212c6385eSIan Rogers "SampleAfterValue": "1000003", 2312c6385eSIan Rogers "UMask": "0x10" 2412c6385eSIan Rogers }, 2512c6385eSIan Rogers { 269061dffdSZhengjun Xing "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0", 2712c6385eSIan Rogers "EventCode": "0xb3", 2812c6385eSIan Rogers "EventName": "FP_ARITH_DISPATCHED.PORT_0", 2912c6385eSIan Rogers "SampleAfterValue": "2000003", 3012c6385eSIan Rogers "UMask": "0x1" 3112c6385eSIan Rogers }, 3212c6385eSIan Rogers { 339061dffdSZhengjun Xing "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1", 3412c6385eSIan Rogers "EventCode": "0xb3", 3512c6385eSIan Rogers "EventName": "FP_ARITH_DISPATCHED.PORT_1", 3612c6385eSIan Rogers "SampleAfterValue": "2000003", 3712c6385eSIan Rogers "UMask": "0x2" 3812c6385eSIan Rogers }, 3912c6385eSIan Rogers { 409061dffdSZhengjun Xing "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5", 4112c6385eSIan Rogers "EventCode": "0xb3", 4212c6385eSIan Rogers "EventName": "FP_ARITH_DISPATCHED.PORT_5", 4312c6385eSIan Rogers "SampleAfterValue": "2000003", 4412c6385eSIan Rogers "UMask": "0x4" 4512c6385eSIan Rogers }, 4612c6385eSIan Rogers { 4712c6385eSIan Rogers "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 4812c6385eSIan Rogers "EventCode": "0xc7", 4912c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 5012c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 5112c6385eSIan Rogers "SampleAfterValue": "100003", 5212c6385eSIan Rogers "UMask": "0x4" 5312c6385eSIan Rogers }, 5412c6385eSIan Rogers { 5512c6385eSIan Rogers "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 5612c6385eSIan Rogers "EventCode": "0xc7", 5712c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 5812c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 5912c6385eSIan Rogers "SampleAfterValue": "100003", 6012c6385eSIan Rogers "UMask": "0x8" 6112c6385eSIan Rogers }, 6212c6385eSIan Rogers { 6312c6385eSIan Rogers "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 6412c6385eSIan Rogers "EventCode": "0xc7", 6512c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 6612c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 6712c6385eSIan Rogers "SampleAfterValue": "100003", 6812c6385eSIan Rogers "UMask": "0x10" 6912c6385eSIan Rogers }, 7012c6385eSIan Rogers { 7112c6385eSIan Rogers "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 7212c6385eSIan Rogers "EventCode": "0xc7", 7312c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 7412c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 7512c6385eSIan Rogers "SampleAfterValue": "100003", 7612c6385eSIan Rogers "UMask": "0x20" 7712c6385eSIan Rogers }, 7812c6385eSIan Rogers { 79*aa205003SIan Rogers "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", 80*aa205003SIan Rogers "EventCode": "0xc7", 81*aa205003SIan Rogers "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", 82*aa205003SIan Rogers "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 83*aa205003SIan Rogers "SampleAfterValue": "100003", 84*aa205003SIan Rogers "UMask": "0x18" 85*aa205003SIan Rogers }, 86*aa205003SIan Rogers { 8712c6385eSIan Rogers "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 8812c6385eSIan Rogers "EventCode": "0xc7", 8912c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", 9012c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 9112c6385eSIan Rogers "SampleAfterValue": "100003", 9212c6385eSIan Rogers "UMask": "0x40" 9312c6385eSIan Rogers }, 9412c6385eSIan Rogers { 9512c6385eSIan Rogers "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 9612c6385eSIan Rogers "EventCode": "0xc7", 9712c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", 9812c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 9912c6385eSIan Rogers "SampleAfterValue": "100003", 10012c6385eSIan Rogers "UMask": "0x80" 10112c6385eSIan Rogers }, 10212c6385eSIan Rogers { 103*aa205003SIan Rogers "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", 104*aa205003SIan Rogers "EventCode": "0xc7", 105*aa205003SIan Rogers "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", 106*aa205003SIan Rogers "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 107*aa205003SIan Rogers "SampleAfterValue": "100003", 108*aa205003SIan Rogers "UMask": "0x60" 109*aa205003SIan Rogers }, 110*aa205003SIan Rogers { 111*aa205003SIan Rogers "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", 112*aa205003SIan Rogers "EventCode": "0xc7", 113*aa205003SIan Rogers "EventName": "FP_ARITH_INST_RETIRED.SCALAR", 114*aa205003SIan Rogers "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 115*aa205003SIan Rogers "SampleAfterValue": "1000003", 116*aa205003SIan Rogers "UMask": "0x3" 117*aa205003SIan Rogers }, 118*aa205003SIan Rogers { 11912c6385eSIan Rogers "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 12012c6385eSIan Rogers "EventCode": "0xc7", 12112c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 12212c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 12312c6385eSIan Rogers "SampleAfterValue": "100003", 12412c6385eSIan Rogers "UMask": "0x1" 12512c6385eSIan Rogers }, 12612c6385eSIan Rogers { 12712c6385eSIan Rogers "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 12812c6385eSIan Rogers "EventCode": "0xc7", 12912c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 13012c6385eSIan Rogers "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 13112c6385eSIan Rogers "SampleAfterValue": "100003", 13212c6385eSIan Rogers "UMask": "0x2" 13312c6385eSIan Rogers }, 13412c6385eSIan Rogers { 135*aa205003SIan Rogers "BriefDescription": "Number of any Vector retired FP arithmetic instructions", 136*aa205003SIan Rogers "EventCode": "0xc7", 137*aa205003SIan Rogers "EventName": "FP_ARITH_INST_RETIRED.VECTOR", 138*aa205003SIan Rogers "PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 139*aa205003SIan Rogers "SampleAfterValue": "1000003", 140*aa205003SIan Rogers "UMask": "0xfc" 141*aa205003SIan Rogers }, 142*aa205003SIan Rogers { 1439061dffdSZhengjun Xing "BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", 14412c6385eSIan Rogers "EventCode": "0xcf", 14512c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", 14612c6385eSIan Rogers "SampleAfterValue": "100003", 14712c6385eSIan Rogers "UMask": "0x4" 14812c6385eSIan Rogers }, 14912c6385eSIan Rogers { 1509061dffdSZhengjun Xing "BriefDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", 15112c6385eSIan Rogers "EventCode": "0xcf", 15212c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", 15312c6385eSIan Rogers "SampleAfterValue": "100003", 15412c6385eSIan Rogers "UMask": "0x8" 15512c6385eSIan Rogers }, 15612c6385eSIan Rogers { 1579061dffdSZhengjun Xing "BriefDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", 15812c6385eSIan Rogers "EventCode": "0xcf", 15912c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", 16012c6385eSIan Rogers "SampleAfterValue": "100003", 16112c6385eSIan Rogers "UMask": "0x10" 16212c6385eSIan Rogers }, 16312c6385eSIan Rogers { 1649061dffdSZhengjun Xing "BriefDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", 16512c6385eSIan Rogers "EventCode": "0xcf", 16612c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", 16712c6385eSIan Rogers "SampleAfterValue": "100003", 16812c6385eSIan Rogers "UMask": "0x2" 16912c6385eSIan Rogers }, 17012c6385eSIan Rogers { 17112c6385eSIan Rogers "BriefDescription": "Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex.", 17212c6385eSIan Rogers "EventCode": "0xcf", 17312c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED2.SCALAR", 1749061dffdSZhengjun Xing "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR", 17512c6385eSIan Rogers "SampleAfterValue": "100003", 17612c6385eSIan Rogers "UMask": "0x3" 17712c6385eSIan Rogers }, 17812c6385eSIan Rogers { 1799061dffdSZhengjun Xing "BriefDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", 18012c6385eSIan Rogers "EventCode": "0xcf", 18112c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", 18212c6385eSIan Rogers "SampleAfterValue": "100003", 18312c6385eSIan Rogers "UMask": "0x1" 18412c6385eSIan Rogers }, 18512c6385eSIan Rogers { 18612c6385eSIan Rogers "BriefDescription": "Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired.", 18712c6385eSIan Rogers "EventCode": "0xcf", 18812c6385eSIan Rogers "EventName": "FP_ARITH_INST_RETIRED2.VECTOR", 1899061dffdSZhengjun Xing "PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR", 19012c6385eSIan Rogers "SampleAfterValue": "100003", 19112c6385eSIan Rogers "UMask": "0x1c" 19212c6385eSIan Rogers } 19312c6385eSIan Rogers] 194