16e82bdaeSAndi Kleen[
26e82bdaeSAndi Kleen    {
3*b5948fc6SIan Rogers        "BriefDescription": "Unhalted core cycles when the thread is in ring 0.",
46e82bdaeSAndi Kleen        "Counter": "0,1,2,3",
5*b5948fc6SIan Rogers        "CounterHTOff": "0,1,2,3,4,5,6,7",
66e82bdaeSAndi Kleen        "EventCode": "0x5C",
76e82bdaeSAndi Kleen        "EventName": "CPL_CYCLES.RING0",
86e82bdaeSAndi Kleen        "SampleAfterValue": "2000003",
9*b5948fc6SIan Rogers        "UMask": "0x1"
106e82bdaeSAndi Kleen    },
116e82bdaeSAndi Kleen    {
12*b5948fc6SIan Rogers        "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
136e82bdaeSAndi Kleen        "Counter": "0,1,2,3",
14*b5948fc6SIan Rogers        "CounterHTOff": "0,1,2,3,4,5,6,7",
15*b5948fc6SIan Rogers        "CounterMask": "1",
166e82bdaeSAndi Kleen        "EdgeDetect": "1",
17*b5948fc6SIan Rogers        "EventCode": "0x5C",
186e82bdaeSAndi Kleen        "EventName": "CPL_CYCLES.RING0_TRANS",
196e82bdaeSAndi Kleen        "SampleAfterValue": "100007",
20*b5948fc6SIan Rogers        "UMask": "0x1"
216e82bdaeSAndi Kleen    },
226e82bdaeSAndi Kleen    {
23*b5948fc6SIan Rogers        "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
246e82bdaeSAndi Kleen        "Counter": "0,1,2,3",
25*b5948fc6SIan Rogers        "CounterHTOff": "0,1,2,3,4,5,6,7",
26*b5948fc6SIan Rogers        "EventCode": "0x5C",
276e82bdaeSAndi Kleen        "EventName": "CPL_CYCLES.RING123",
286e82bdaeSAndi Kleen        "SampleAfterValue": "2000003",
29*b5948fc6SIan Rogers        "UMask": "0x2"
306e82bdaeSAndi Kleen    },
316e82bdaeSAndi Kleen    {
32*b5948fc6SIan Rogers        "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
336e82bdaeSAndi Kleen        "Counter": "0,1,2,3",
34*b5948fc6SIan Rogers        "CounterHTOff": "0,1,2,3,4,5,6,7",
35*b5948fc6SIan Rogers        "EventCode": "0x4E",
36*b5948fc6SIan Rogers        "EventName": "HW_PRE_REQ.DL1_MISS",
37*b5948fc6SIan Rogers        "SampleAfterValue": "2000003",
38*b5948fc6SIan Rogers        "UMask": "0x2"
39*b5948fc6SIan Rogers    },
40*b5948fc6SIan Rogers    {
41*b5948fc6SIan Rogers        "BriefDescription": "Valid instructions written to IQ per cycle.",
42*b5948fc6SIan Rogers        "Counter": "0,1,2,3",
43*b5948fc6SIan Rogers        "CounterHTOff": "0,1,2,3,4,5,6,7",
44*b5948fc6SIan Rogers        "EventCode": "0x17",
45*b5948fc6SIan Rogers        "EventName": "INSTS_WRITTEN_TO_IQ.INSTS",
46*b5948fc6SIan Rogers        "SampleAfterValue": "2000003",
47*b5948fc6SIan Rogers        "UMask": "0x1"
48*b5948fc6SIan Rogers    },
49*b5948fc6SIan Rogers    {
50*b5948fc6SIan Rogers        "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",
51*b5948fc6SIan Rogers        "Counter": "0,1,2,3",
52*b5948fc6SIan Rogers        "CounterHTOff": "0,1,2,3,4,5,6,7",
53*b5948fc6SIan Rogers        "EventCode": "0x63",
546e82bdaeSAndi Kleen        "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
556e82bdaeSAndi Kleen        "SampleAfterValue": "2000003",
56*b5948fc6SIan Rogers        "UMask": "0x1"
576e82bdaeSAndi Kleen    }
586e82bdaeSAndi Kleen]