16e82bdaeSAndi Kleen[
26e82bdaeSAndi Kleen    {
36e82bdaeSAndi Kleen        "EventCode": "0x17",
46e82bdaeSAndi Kleen        "Counter": "0,1,2,3",
56e82bdaeSAndi Kleen        "UMask": "0x1",
66e82bdaeSAndi Kleen        "EventName": "INSTS_WRITTEN_TO_IQ.INSTS",
76e82bdaeSAndi Kleen        "SampleAfterValue": "2000003",
86e82bdaeSAndi Kleen        "BriefDescription": "Valid instructions written to IQ per cycle.",
96e82bdaeSAndi Kleen        "CounterHTOff": "0,1,2,3,4,5,6,7"
106e82bdaeSAndi Kleen    },
116e82bdaeSAndi Kleen    {
126e82bdaeSAndi Kleen        "EventCode": "0x5C",
136e82bdaeSAndi Kleen        "Counter": "0,1,2,3",
146e82bdaeSAndi Kleen        "UMask": "0x1",
156e82bdaeSAndi Kleen        "EventName": "CPL_CYCLES.RING0",
166e82bdaeSAndi Kleen        "SampleAfterValue": "2000003",
176e82bdaeSAndi Kleen        "BriefDescription": "Unhalted core cycles when the thread is in ring 0.",
186e82bdaeSAndi Kleen        "CounterHTOff": "0,1,2,3,4,5,6,7"
196e82bdaeSAndi Kleen    },
206e82bdaeSAndi Kleen    {
216e82bdaeSAndi Kleen        "EventCode": "0x5C",
226e82bdaeSAndi Kleen        "Counter": "0,1,2,3",
236e82bdaeSAndi Kleen        "UMask": "0x1",
246e82bdaeSAndi Kleen        "EdgeDetect": "1",
256e82bdaeSAndi Kleen        "EventName": "CPL_CYCLES.RING0_TRANS",
266e82bdaeSAndi Kleen        "SampleAfterValue": "100007",
276e82bdaeSAndi Kleen        "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
286e82bdaeSAndi Kleen        "CounterMask": "1",
296e82bdaeSAndi Kleen        "CounterHTOff": "0,1,2,3,4,5,6,7"
306e82bdaeSAndi Kleen    },
316e82bdaeSAndi Kleen    {
326e82bdaeSAndi Kleen        "EventCode": "0x5C",
336e82bdaeSAndi Kleen        "Counter": "0,1,2,3",
346e82bdaeSAndi Kleen        "UMask": "0x2",
356e82bdaeSAndi Kleen        "EventName": "CPL_CYCLES.RING123",
366e82bdaeSAndi Kleen        "SampleAfterValue": "2000003",
376e82bdaeSAndi Kleen        "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
386e82bdaeSAndi Kleen        "CounterHTOff": "0,1,2,3,4,5,6,7"
396e82bdaeSAndi Kleen    },
406e82bdaeSAndi Kleen    {
416e82bdaeSAndi Kleen        "EventCode": "0x4E",
426e82bdaeSAndi Kleen        "Counter": "0,1,2,3",
436e82bdaeSAndi Kleen        "UMask": "0x2",
446e82bdaeSAndi Kleen        "EventName": "HW_PRE_REQ.DL1_MISS",
456e82bdaeSAndi Kleen        "SampleAfterValue": "2000003",
466e82bdaeSAndi Kleen        "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
476e82bdaeSAndi Kleen        "CounterHTOff": "0,1,2,3,4,5,6,7"
486e82bdaeSAndi Kleen    },
496e82bdaeSAndi Kleen    {
506e82bdaeSAndi Kleen        "EventCode": "0x63",
516e82bdaeSAndi Kleen        "Counter": "0,1,2,3",
526e82bdaeSAndi Kleen        "UMask": "0x1",
536e82bdaeSAndi Kleen        "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
546e82bdaeSAndi Kleen        "SampleAfterValue": "2000003",
556e82bdaeSAndi Kleen        "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",
566e82bdaeSAndi Kleen        "CounterHTOff": "0,1,2,3,4,5,6,7"
576e82bdaeSAndi Kleen    }
586e82bdaeSAndi Kleen]