16e82bdaeSAndi Kleen[ 26e82bdaeSAndi Kleen { 3*b5948fc6SIan Rogers "BriefDescription": "Unhalted core cycles when the thread is in ring 0.", 46e82bdaeSAndi Kleen "EventCode": "0x5C", 56e82bdaeSAndi Kleen "EventName": "CPL_CYCLES.RING0", 66e82bdaeSAndi Kleen "SampleAfterValue": "2000003", 7*b5948fc6SIan Rogers "UMask": "0x1" 86e82bdaeSAndi Kleen }, 96e82bdaeSAndi Kleen { 10*b5948fc6SIan Rogers "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", 11*b5948fc6SIan Rogers "CounterMask": "1", 126e82bdaeSAndi Kleen "EdgeDetect": "1", 13*b5948fc6SIan Rogers "EventCode": "0x5C", 146e82bdaeSAndi Kleen "EventName": "CPL_CYCLES.RING0_TRANS", 156e82bdaeSAndi Kleen "SampleAfterValue": "100007", 16*b5948fc6SIan Rogers "UMask": "0x1" 176e82bdaeSAndi Kleen }, 186e82bdaeSAndi Kleen { 19*b5948fc6SIan Rogers "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.", 20*b5948fc6SIan Rogers "EventCode": "0x5C", 216e82bdaeSAndi Kleen "EventName": "CPL_CYCLES.RING123", 226e82bdaeSAndi Kleen "SampleAfterValue": "2000003", 23*b5948fc6SIan Rogers "UMask": "0x2" 246e82bdaeSAndi Kleen }, 256e82bdaeSAndi Kleen { 26*b5948fc6SIan Rogers "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .", 27*b5948fc6SIan Rogers "EventCode": "0x4E", 28*b5948fc6SIan Rogers "EventName": "HW_PRE_REQ.DL1_MISS", 29*b5948fc6SIan Rogers "SampleAfterValue": "2000003", 30*b5948fc6SIan Rogers "UMask": "0x2" 31*b5948fc6SIan Rogers }, 32*b5948fc6SIan Rogers { 33*b5948fc6SIan Rogers "BriefDescription": "Valid instructions written to IQ per cycle.", 34*b5948fc6SIan Rogers "EventCode": "0x17", 35*b5948fc6SIan Rogers "EventName": "INSTS_WRITTEN_TO_IQ.INSTS", 36*b5948fc6SIan Rogers "SampleAfterValue": "2000003", 37*b5948fc6SIan Rogers "UMask": "0x1" 38*b5948fc6SIan Rogers }, 39*b5948fc6SIan Rogers { 40*b5948fc6SIan Rogers "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.", 41*b5948fc6SIan Rogers "EventCode": "0x63", 426e82bdaeSAndi Kleen "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", 436e82bdaeSAndi Kleen "SampleAfterValue": "2000003", 44*b5948fc6SIan Rogers "UMask": "0x1" 456e82bdaeSAndi Kleen } 466e82bdaeSAndi Kleen] 47