1[ 2 { 3 "EventCode": "0x05", 4 "Counter": "0,1,2,3", 5 "UMask": "0x1", 6 "EventName": "MISALIGN_MEM_REF.LOADS", 7 "SampleAfterValue": "2000003", 8 "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.", 9 "CounterHTOff": "0,1,2,3,4,5,6,7" 10 }, 11 { 12 "EventCode": "0x05", 13 "Counter": "0,1,2,3", 14 "UMask": "0x2", 15 "EventName": "MISALIGN_MEM_REF.STORES", 16 "SampleAfterValue": "2000003", 17 "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.", 18 "CounterHTOff": "0,1,2,3,4,5,6,7" 19 }, 20 { 21 "EventCode": "0xBE", 22 "Counter": "0,1,2,3", 23 "UMask": "0x1", 24 "EventName": "PAGE_WALKS.LLC_MISS", 25 "SampleAfterValue": "100003", 26 "BriefDescription": "Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND.", 27 "CounterHTOff": "0,1,2,3,4,5,6,7" 28 }, 29 { 30 "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.", 31 "EventCode": "0xC3", 32 "Counter": "0,1,2,3", 33 "UMask": "0x2", 34 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 35 "SampleAfterValue": "100003", 36 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 37 "CounterHTOff": "0,1,2,3,4,5,6,7" 38 }, 39 { 40 "PEBS": "2", 41 "EventCode": "0xCD", 42 "MSRValue": "0x4", 43 "Counter": "3", 44 "UMask": "0x1", 45 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 46 "MSRIndex": "0x3F6", 47 "SampleAfterValue": "100003", 48 "BriefDescription": "Loads with latency value being above 4 .", 49 "TakenAlone": "1", 50 "CounterHTOff": "3" 51 }, 52 { 53 "PEBS": "2", 54 "EventCode": "0xCD", 55 "MSRValue": "0x8", 56 "Counter": "3", 57 "UMask": "0x1", 58 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 59 "MSRIndex": "0x3F6", 60 "SampleAfterValue": "50021", 61 "BriefDescription": "Loads with latency value being above 8.", 62 "TakenAlone": "1", 63 "CounterHTOff": "3" 64 }, 65 { 66 "PEBS": "2", 67 "EventCode": "0xCD", 68 "MSRValue": "0x10", 69 "Counter": "3", 70 "UMask": "0x1", 71 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 72 "MSRIndex": "0x3F6", 73 "SampleAfterValue": "20011", 74 "BriefDescription": "Loads with latency value being above 16.", 75 "TakenAlone": "1", 76 "CounterHTOff": "3" 77 }, 78 { 79 "PEBS": "2", 80 "EventCode": "0xCD", 81 "MSRValue": "0x20", 82 "Counter": "3", 83 "UMask": "0x1", 84 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 85 "MSRIndex": "0x3F6", 86 "SampleAfterValue": "100007", 87 "BriefDescription": "Loads with latency value being above 32.", 88 "TakenAlone": "1", 89 "CounterHTOff": "3" 90 }, 91 { 92 "PEBS": "2", 93 "EventCode": "0xCD", 94 "MSRValue": "0x40", 95 "Counter": "3", 96 "UMask": "0x1", 97 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 98 "MSRIndex": "0x3F6", 99 "SampleAfterValue": "2003", 100 "BriefDescription": "Loads with latency value being above 64.", 101 "TakenAlone": "1", 102 "CounterHTOff": "3" 103 }, 104 { 105 "PEBS": "2", 106 "EventCode": "0xCD", 107 "MSRValue": "0x80", 108 "Counter": "3", 109 "UMask": "0x1", 110 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 111 "MSRIndex": "0x3F6", 112 "SampleAfterValue": "1009", 113 "BriefDescription": "Loads with latency value being above 128.", 114 "TakenAlone": "1", 115 "CounterHTOff": "3" 116 }, 117 { 118 "PEBS": "2", 119 "EventCode": "0xCD", 120 "MSRValue": "0x100", 121 "Counter": "3", 122 "UMask": "0x1", 123 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 124 "MSRIndex": "0x3F6", 125 "SampleAfterValue": "503", 126 "BriefDescription": "Loads with latency value being above 256.", 127 "TakenAlone": "1", 128 "CounterHTOff": "3" 129 }, 130 { 131 "PEBS": "2", 132 "EventCode": "0xCD", 133 "MSRValue": "0x200", 134 "Counter": "3", 135 "UMask": "0x1", 136 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 137 "MSRIndex": "0x3F6", 138 "SampleAfterValue": "101", 139 "BriefDescription": "Loads with latency value being above 512.", 140 "TakenAlone": "1", 141 "CounterHTOff": "3" 142 }, 143 { 144 "PEBS": "2", 145 "EventCode": "0xCD", 146 "Counter": "3", 147 "UMask": "0x2", 148 "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", 149 "SampleAfterValue": "2000003", 150 "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).", 151 "PRECISE_STORE": "1", 152 "TakenAlone": "1", 153 "CounterHTOff": "3" 154 }, 155 { 156 "EventCode": "0xB7, 0xBB", 157 "MSRValue": "0x300400244", 158 "Counter": "0,1,2,3", 159 "UMask": "0x1", 160 "Offcore": "1", 161 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM", 162 "MSRIndex": "0x1a6,0x1a7", 163 "SampleAfterValue": "100003", 164 "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram.", 165 "CounterHTOff": "0,1,2,3" 166 }, 167 { 168 "EventCode": "0xB7, 0xBB", 169 "MSRValue": "0x300400091", 170 "Counter": "0,1,2,3", 171 "UMask": "0x1", 172 "Offcore": "1", 173 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM", 174 "MSRIndex": "0x1a6,0x1a7", 175 "SampleAfterValue": "100003", 176 "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram.", 177 "CounterHTOff": "0,1,2,3" 178 }, 179 { 180 "EventCode": "0xB7, 0xBB", 181 "MSRValue": "0x300400240", 182 "Counter": "0,1,2,3", 183 "UMask": "0x1", 184 "Offcore": "1", 185 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_MISS.DRAM", 186 "MSRIndex": "0x1a6,0x1a7", 187 "SampleAfterValue": "100003", 188 "BriefDescription": "Counts all prefetch code reads that miss the LLC and the data returned from dram.", 189 "CounterHTOff": "0,1,2,3" 190 }, 191 { 192 "EventCode": "0xB7, 0xBB", 193 "MSRValue": "0x300400090", 194 "Counter": "0,1,2,3", 195 "UMask": "0x1", 196 "Offcore": "1", 197 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_MISS.DRAM", 198 "MSRIndex": "0x1a6,0x1a7", 199 "SampleAfterValue": "100003", 200 "BriefDescription": "Counts all prefetch data reads that miss the LLC and the data returned from dram.", 201 "CounterHTOff": "0,1,2,3" 202 }, 203 { 204 "EventCode": "0xB7, 0xBB", 205 "MSRValue": "0x300400120", 206 "Counter": "0,1,2,3", 207 "UMask": "0x1", 208 "Offcore": "1", 209 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_MISS.DRAM", 210 "MSRIndex": "0x1a6,0x1a7", 211 "SampleAfterValue": "100003", 212 "BriefDescription": "Counts all prefetch RFOs that miss the LLC and the data returned from dram.", 213 "CounterHTOff": "0,1,2,3" 214 }, 215 { 216 "EventCode": "0xB7, 0xBB", 217 "MSRValue": "0x3004003f7", 218 "Counter": "0,1,2,3", 219 "UMask": "0x1", 220 "Offcore": "1", 221 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM", 222 "MSRIndex": "0x1a6,0x1a7", 223 "SampleAfterValue": "100003", 224 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram.", 225 "CounterHTOff": "0,1,2,3" 226 }, 227 { 228 "EventCode": "0xB7, 0xBB", 229 "MSRValue": "0x300400122", 230 "Counter": "0,1,2,3", 231 "UMask": "0x1", 232 "Offcore": "1", 233 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.DRAM", 234 "MSRIndex": "0x1a6,0x1a7", 235 "SampleAfterValue": "100003", 236 "BriefDescription": "Counts all demand & prefetch RFOs that miss the LLC and the data returned from dram.", 237 "CounterHTOff": "0,1,2,3" 238 }, 239 { 240 "EventCode": "0xB7, 0xBB", 241 "MSRValue": "0x300400004", 242 "Counter": "0,1,2,3", 243 "UMask": "0x1", 244 "Offcore": "1", 245 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM", 246 "MSRIndex": "0x1a6,0x1a7", 247 "SampleAfterValue": "100003", 248 "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram.", 249 "CounterHTOff": "0,1,2,3" 250 }, 251 { 252 "EventCode": "0xB7, 0xBB", 253 "MSRValue": "0x300400001", 254 "Counter": "0,1,2,3", 255 "UMask": "0x1", 256 "Offcore": "1", 257 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM", 258 "MSRIndex": "0x1a6,0x1a7", 259 "SampleAfterValue": "100003", 260 "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram.", 261 "CounterHTOff": "0,1,2,3" 262 }, 263 { 264 "EventCode": "0xB7, 0xBB", 265 "MSRValue": "0x300400002", 266 "Counter": "0,1,2,3", 267 "UMask": "0x1", 268 "Offcore": "1", 269 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.DRAM", 270 "MSRIndex": "0x1a6,0x1a7", 271 "SampleAfterValue": "100003", 272 "BriefDescription": "Counts demand data writes (RFOs) that miss the LLC and the data returned from dram.", 273 "CounterHTOff": "0,1,2,3" 274 }, 275 { 276 "EventCode": "0xB7, 0xBB", 277 "MSRValue": "0x300400040", 278 "Counter": "0,1,2,3", 279 "UMask": "0x1", 280 "Offcore": "1", 281 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.DRAM", 282 "MSRIndex": "0x1a6,0x1a7", 283 "SampleAfterValue": "100003", 284 "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from dram.", 285 "CounterHTOff": "0,1,2,3" 286 }, 287 { 288 "EventCode": "0xB7, 0xBB", 289 "MSRValue": "0x300400010", 290 "Counter": "0,1,2,3", 291 "UMask": "0x1", 292 "Offcore": "1", 293 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.DRAM", 294 "MSRIndex": "0x1a6,0x1a7", 295 "SampleAfterValue": "100003", 296 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram.", 297 "CounterHTOff": "0,1,2,3" 298 }, 299 { 300 "EventCode": "0xB7, 0xBB", 301 "MSRValue": "0x300400020", 302 "Counter": "0,1,2,3", 303 "UMask": "0x1", 304 "Offcore": "1", 305 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.DRAM", 306 "MSRIndex": "0x1a6,0x1a7", 307 "SampleAfterValue": "100003", 308 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the LLC and the data returned from dram.", 309 "CounterHTOff": "0,1,2,3" 310 }, 311 { 312 "EventCode": "0xB7, 0xBB", 313 "MSRValue": "0x300400200", 314 "Counter": "0,1,2,3", 315 "UMask": "0x1", 316 "Offcore": "1", 317 "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.DRAM", 318 "MSRIndex": "0x1a6,0x1a7", 319 "SampleAfterValue": "100003", 320 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the LLC and the data returned from dram.", 321 "CounterHTOff": "0,1,2,3" 322 }, 323 { 324 "EventCode": "0xB7, 0xBB", 325 "MSRValue": "0x300400080", 326 "Counter": "0,1,2,3", 327 "UMask": "0x1", 328 "Offcore": "1", 329 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.DRAM", 330 "MSRIndex": "0x1a6,0x1a7", 331 "SampleAfterValue": "100003", 332 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the LLC and the data returned from dram.", 333 "CounterHTOff": "0,1,2,3" 334 }, 335 { 336 "EventCode": "0xB7, 0xBB", 337 "MSRValue": "0x300400100", 338 "Counter": "0,1,2,3", 339 "UMask": "0x1", 340 "Offcore": "1", 341 "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.DRAM", 342 "MSRIndex": "0x1a6,0x1a7", 343 "SampleAfterValue": "100003", 344 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC and the data returned from dram.", 345 "CounterHTOff": "0,1,2,3" 346 }, 347 { 348 "PublicDescription": "This event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC where the data is returned from local DRAM", 349 "EventCode": "0xB7, 0xBB", 350 "MSRValue": "0x6004001b3", 351 "Counter": "0,1,2,3", 352 "UMask": "0x1", 353 "Offcore": "1", 354 "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM", 355 "MSRIndex": "0x1a6,0x1a7", 356 "SampleAfterValue": "100003", 357 "BriefDescription": "Counts LLC replacements.", 358 "CounterHTOff": "0,1,2,3" 359 }, 360 { 361 "PublicDescription": "This event counts any requests that miss the LLC where the data was returned from local DRAM", 362 "EventCode": "0xB7, 0xBB", 363 "MSRValue": "0x1f80408fff", 364 "Counter": "0,1,2,3", 365 "UMask": "0x1", 366 "Offcore": "1", 367 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_MISS_LOCAL.DRAM", 368 "MSRIndex": "0x1a6,0x1a7", 369 "SampleAfterValue": "100003", 370 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", 371 "CounterHTOff": "0,1,2,3" 372 }, 373 { 374 "EventCode": "0xB7, 0xBB", 375 "MSRValue": "0x17004001b3", 376 "Counter": "0,1,2,3", 377 "UMask": "0x1", 378 "Offcore": "1", 379 "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS_LOCAL.ANY_LLC_HIT", 380 "MSRIndex": "0x1a6,0x1a7", 381 "SampleAfterValue": "100003", 382 "BriefDescription": "REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT", 383 "CounterHTOff": "0,1,2,3" 384 }, 385 { 386 "EventCode": "0xB7, 0xBB", 387 "MSRValue": "0x1f80400004", 388 "Counter": "0,1,2,3", 389 "UMask": "0x1", 390 "Offcore": "1", 391 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_MISS_LOCAL.DRAM", 392 "MSRIndex": "0x1a6,0x1a7", 393 "SampleAfterValue": "100003", 394 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", 395 "CounterHTOff": "0,1,2,3" 396 }, 397 { 398 "EventCode": "0xB7, 0xBB", 399 "MSRValue": "0x1f80400010", 400 "Counter": "0,1,2,3", 401 "UMask": "0x1", 402 "Offcore": "1", 403 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_MISS_LOCAL.DRAM", 404 "MSRIndex": "0x1a6,0x1a7", 405 "SampleAfterValue": "100003", 406 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", 407 "CounterHTOff": "0,1,2,3" 408 }, 409 { 410 "EventCode": "0xB7, 0xBB", 411 "MSRValue": "0x1f80400040", 412 "Counter": "0,1,2,3", 413 "UMask": "0x1", 414 "Offcore": "1", 415 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_MISS_LOCAL.DRAM", 416 "MSRIndex": "0x1a6,0x1a7", 417 "SampleAfterValue": "100003", 418 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", 419 "CounterHTOff": "0,1,2,3" 420 }, 421 { 422 "EventCode": "0xB7, 0xBB", 423 "MSRValue": "0x1f80400080", 424 "Counter": "0,1,2,3", 425 "UMask": "0x1", 426 "Offcore": "1", 427 "EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.LLC_MISS_LOCAL.DRAM", 428 "MSRIndex": "0x1a6,0x1a7", 429 "SampleAfterValue": "100003", 430 "BriefDescription": "REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", 431 "CounterHTOff": "0,1,2,3" 432 }, 433 { 434 "EventCode": "0xB7, 0xBB", 435 "MSRValue": "0x1f80400200", 436 "Counter": "0,1,2,3", 437 "UMask": "0x1", 438 "Offcore": "1", 439 "EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.LLC_MISS_LOCAL.DRAM", 440 "MSRIndex": "0x1a6,0x1a7", 441 "SampleAfterValue": "100003", 442 "BriefDescription": "REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", 443 "CounterHTOff": "0,1,2,3" 444 } 445]