xref: /openbmc/linux/tools/perf/pmu-events/arch/x86/sandybridge/memory.json (revision b5948fc6)

[
    {
        "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xC3",
        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
        "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers.  Machine clears can have a significant performance impact if they are happening frequently.",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Loads with latency value being above 128.",
        "Counter": "3",
        "CounterHTOff": "3",
        "EventCode": "0xCD",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x80",
        "PEBS": "2",
        "SampleAfterValue": "1009",
        "TakenAlone": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Loads with latency value being above 16.",
        "Counter": "3",
        "CounterHTOff": "3",
        "EventCode": "0xCD",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x10",
        "PEBS": "2",
        "SampleAfterValue": "20011",
        "TakenAlone": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Loads with latency value being above 256.",
        "Counter": "3",
        "CounterHTOff": "3",
        "EventCode": "0xCD",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x100",
        "PEBS": "2",
        "SampleAfterValue": "503",
        "TakenAlone": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Loads with latency value being above 32.",
        "Counter": "3",
        "CounterHTOff": "3",
        "EventCode": "0xCD",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x20",
        "PEBS": "2",
        "SampleAfterValue": "100007",
        "TakenAlone": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Loads with latency value being above 4 .",
        "Counter": "3",
        "CounterHTOff": "3",
        "EventCode": "0xCD",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x4",
        "PEBS": "2",
        "SampleAfterValue": "100003",
        "TakenAlone": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Loads with latency value being above 512.",
        "Counter": "3",
        "CounterHTOff": "3",
        "EventCode": "0xCD",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x200",
        "PEBS": "2",
        "SampleAfterValue": "101",
        "TakenAlone": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Loads with latency value being above 64.",
        "Counter": "3",
        "CounterHTOff": "3",
        "EventCode": "0xCD",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x40",
        "PEBS": "2",
        "SampleAfterValue": "2003",
        "TakenAlone": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Loads with latency value being above 8.",
        "Counter": "3",
        "CounterHTOff": "3",
        "EventCode": "0xCD",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x8",
        "PEBS": "2",
        "SampleAfterValue": "50021",
        "TakenAlone": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).",
        "Counter": "3",
        "CounterHTOff": "3",
        "EventCode": "0xCD",
        "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
        "PEBS": "2",
        "PRECISE_STORE": "1",
        "SampleAfterValue": "2000003",
        "TakenAlone": "1",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x05",
        "EventName": "MISALIGN_MEM_REF.LOADS",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x05",
        "EventName": "MISALIGN_MEM_REF.STORES",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC  and the data returned from dram.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x300400244",
        "Offcore": "1",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC  and the data returned from dram.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x300400091",
        "Offcore": "1",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all prefetch code reads that miss the LLC  and the data returned from dram.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_MISS.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x300400240",
        "Offcore": "1",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all prefetch data reads that miss the LLC  and the data returned from dram.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_MISS.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x300400090",
        "Offcore": "1",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all prefetch RFOs that miss the LLC  and the data returned from dram.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_MISS.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x300400120",
        "Offcore": "1",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from dram.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3004003f7",
        "Offcore": "1",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all demand & prefetch RFOs that miss the LLC  and the data returned from dram.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x300400122",
        "Offcore": "1",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_MISS_LOCAL.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x1f80408fff",
        "Offcore": "1",
        "PublicDescription": "This event counts any requests that miss the LLC where the data was returned from local DRAM",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts LLC replacements.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x6004001b3",
        "Offcore": "1",
        "PublicDescription": "This event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC  where the data is returned from local DRAM",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS_LOCAL.ANY_LLC_HIT",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x17004001b3",
        "Offcore": "1",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x300400004",
        "Offcore": "1",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x300400001",
        "Offcore": "1",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_MISS_LOCAL.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x1f80400004",
        "Offcore": "1",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand data writes (RFOs) that miss the LLC and the data returned from dram.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x300400002",
        "Offcore": "1",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_MISS_LOCAL.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x1f80400010",
        "Offcore": "1",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_MISS_LOCAL.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x1f80400040",
        "Offcore": "1",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from dram.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x300400040",
        "Offcore": "1",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x300400010",
        "Offcore": "1",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the LLC  and the data returned from dram.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x300400020",
        "Offcore": "1",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the LLC  and the data returned from dram.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x300400200",
        "Offcore": "1",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the LLC  and the data returned from dram.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x300400080",
        "Offcore": "1",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC  and the data returned from dram.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x300400100",
        "Offcore": "1",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.LLC_MISS_LOCAL.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x1f80400080",
        "Offcore": "1",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.LLC_MISS_LOCAL.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x1f80400200",
        "Offcore": "1",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xBE",
        "EventName": "PAGE_WALKS.LLC_MISS",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    }
]