16e82bdaeSAndi Kleen[ 26e82bdaeSAndi Kleen { 3*b5948fc6SIan Rogers "BriefDescription": "Cycles with any input/output SSE or FP assist.", 4*b5948fc6SIan Rogers "CounterMask": "1", 559da390eSAndi Kleen "EventCode": "0xCA", 66e82bdaeSAndi Kleen "EventName": "FP_ASSIST.ANY", 76e82bdaeSAndi Kleen "SampleAfterValue": "100003", 8*b5948fc6SIan Rogers "UMask": "0x1e" 9*b5948fc6SIan Rogers }, 10*b5948fc6SIan Rogers { 11*b5948fc6SIan Rogers "BriefDescription": "Number of SIMD FP assists due to input values.", 12*b5948fc6SIan Rogers "EventCode": "0xCA", 13*b5948fc6SIan Rogers "EventName": "FP_ASSIST.SIMD_INPUT", 14*b5948fc6SIan Rogers "SampleAfterValue": "100003", 15*b5948fc6SIan Rogers "UMask": "0x10" 16*b5948fc6SIan Rogers }, 17*b5948fc6SIan Rogers { 18*b5948fc6SIan Rogers "BriefDescription": "Number of SIMD FP assists due to Output values.", 19*b5948fc6SIan Rogers "EventCode": "0xCA", 20*b5948fc6SIan Rogers "EventName": "FP_ASSIST.SIMD_OUTPUT", 21*b5948fc6SIan Rogers "SampleAfterValue": "100003", 22*b5948fc6SIan Rogers "UMask": "0x8" 23*b5948fc6SIan Rogers }, 24*b5948fc6SIan Rogers { 25*b5948fc6SIan Rogers "BriefDescription": "Number of X87 assists due to input value.", 26*b5948fc6SIan Rogers "EventCode": "0xCA", 27*b5948fc6SIan Rogers "EventName": "FP_ASSIST.X87_INPUT", 28*b5948fc6SIan Rogers "SampleAfterValue": "100003", 29*b5948fc6SIan Rogers "UMask": "0x4" 30*b5948fc6SIan Rogers }, 31*b5948fc6SIan Rogers { 32*b5948fc6SIan Rogers "BriefDescription": "Number of X87 assists due to output value.", 33*b5948fc6SIan Rogers "EventCode": "0xCA", 34*b5948fc6SIan Rogers "EventName": "FP_ASSIST.X87_OUTPUT", 35*b5948fc6SIan Rogers "SampleAfterValue": "100003", 36*b5948fc6SIan Rogers "UMask": "0x2" 37*b5948fc6SIan Rogers }, 38*b5948fc6SIan Rogers { 39*b5948fc6SIan Rogers "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.", 40*b5948fc6SIan Rogers "EventCode": "0x10", 41*b5948fc6SIan Rogers "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", 42*b5948fc6SIan Rogers "SampleAfterValue": "2000003", 43*b5948fc6SIan Rogers "UMask": "0x10" 44*b5948fc6SIan Rogers }, 45*b5948fc6SIan Rogers { 46*b5948fc6SIan Rogers "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.", 47*b5948fc6SIan Rogers "EventCode": "0x10", 48*b5948fc6SIan Rogers "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", 49*b5948fc6SIan Rogers "SampleAfterValue": "2000003", 50*b5948fc6SIan Rogers "UMask": "0x40" 51*b5948fc6SIan Rogers }, 52*b5948fc6SIan Rogers { 53*b5948fc6SIan Rogers "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.", 54*b5948fc6SIan Rogers "EventCode": "0x10", 55*b5948fc6SIan Rogers "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", 56*b5948fc6SIan Rogers "SampleAfterValue": "2000003", 57*b5948fc6SIan Rogers "UMask": "0x80" 58*b5948fc6SIan Rogers }, 59*b5948fc6SIan Rogers { 60*b5948fc6SIan Rogers "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.", 61*b5948fc6SIan Rogers "EventCode": "0x10", 62*b5948fc6SIan Rogers "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", 63*b5948fc6SIan Rogers "SampleAfterValue": "2000003", 64*b5948fc6SIan Rogers "UMask": "0x20" 65*b5948fc6SIan Rogers }, 66*b5948fc6SIan Rogers { 67*b5948fc6SIan Rogers "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.", 68*b5948fc6SIan Rogers "EventCode": "0x10", 69*b5948fc6SIan Rogers "EventName": "FP_COMP_OPS_EXE.X87", 70*b5948fc6SIan Rogers "SampleAfterValue": "2000003", 71*b5948fc6SIan Rogers "UMask": "0x1" 72*b5948fc6SIan Rogers }, 73*b5948fc6SIan Rogers { 74*b5948fc6SIan Rogers "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.", 75*b5948fc6SIan Rogers "EventCode": "0xC1", 76*b5948fc6SIan Rogers "EventName": "OTHER_ASSISTS.AVX_STORE", 77*b5948fc6SIan Rogers "SampleAfterValue": "100003", 78*b5948fc6SIan Rogers "UMask": "0x8" 79*b5948fc6SIan Rogers }, 80*b5948fc6SIan Rogers { 81*b5948fc6SIan Rogers "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", 82*b5948fc6SIan Rogers "EventCode": "0xC1", 83*b5948fc6SIan Rogers "EventName": "OTHER_ASSISTS.AVX_TO_SSE", 84*b5948fc6SIan Rogers "SampleAfterValue": "100003", 85*b5948fc6SIan Rogers "UMask": "0x10" 86*b5948fc6SIan Rogers }, 87*b5948fc6SIan Rogers { 88*b5948fc6SIan Rogers "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", 89*b5948fc6SIan Rogers "EventCode": "0xC1", 90*b5948fc6SIan Rogers "EventName": "OTHER_ASSISTS.SSE_TO_AVX", 91*b5948fc6SIan Rogers "SampleAfterValue": "100003", 92*b5948fc6SIan Rogers "UMask": "0x20" 93*b5948fc6SIan Rogers }, 94*b5948fc6SIan Rogers { 95*b5948fc6SIan Rogers "BriefDescription": "Number of AVX-256 Computational FP double precision uops issued this cycle.", 96*b5948fc6SIan Rogers "EventCode": "0x11", 97*b5948fc6SIan Rogers "EventName": "SIMD_FP_256.PACKED_DOUBLE", 98*b5948fc6SIan Rogers "SampleAfterValue": "2000003", 99*b5948fc6SIan Rogers "UMask": "0x2" 100*b5948fc6SIan Rogers }, 101*b5948fc6SIan Rogers { 102*b5948fc6SIan Rogers "BriefDescription": "Number of GSSE-256 Computational FP single precision uops issued this cycle.", 103*b5948fc6SIan Rogers "EventCode": "0x11", 104*b5948fc6SIan Rogers "EventName": "SIMD_FP_256.PACKED_SINGLE", 105*b5948fc6SIan Rogers "SampleAfterValue": "2000003", 106*b5948fc6SIan Rogers "UMask": "0x1" 1076e82bdaeSAndi Kleen } 1086e82bdaeSAndi Kleen] 109