1[ 2 { 3 "EventCode": "0x63", 4 "Counter": "0,1", 5 "UMask": "0x2", 6 "EventName": "CACHE_LOCK_CYCLES.L1D", 7 "SampleAfterValue": "2000000", 8 "BriefDescription": "Cycles L1D locked" 9 }, 10 { 11 "EventCode": "0x63", 12 "Counter": "0,1", 13 "UMask": "0x1", 14 "EventName": "CACHE_LOCK_CYCLES.L1D_L2", 15 "SampleAfterValue": "2000000", 16 "BriefDescription": "Cycles L1D and L2 locked" 17 }, 18 { 19 "EventCode": "0x51", 20 "Counter": "0,1", 21 "UMask": "0x4", 22 "EventName": "L1D.M_EVICT", 23 "SampleAfterValue": "2000000", 24 "BriefDescription": "L1D cache lines replaced in M state" 25 }, 26 { 27 "EventCode": "0x51", 28 "Counter": "0,1", 29 "UMask": "0x2", 30 "EventName": "L1D.M_REPL", 31 "SampleAfterValue": "2000000", 32 "BriefDescription": "L1D cache lines allocated in the M state" 33 }, 34 { 35 "EventCode": "0x51", 36 "Counter": "0,1", 37 "UMask": "0x8", 38 "EventName": "L1D.M_SNOOP_EVICT", 39 "SampleAfterValue": "2000000", 40 "BriefDescription": "L1D snoop eviction of cache lines in M state" 41 }, 42 { 43 "EventCode": "0x51", 44 "Counter": "0,1", 45 "UMask": "0x1", 46 "EventName": "L1D.REPL", 47 "SampleAfterValue": "2000000", 48 "BriefDescription": "L1 data cache lines allocated" 49 }, 50 { 51 "EventCode": "0x43", 52 "Counter": "0,1", 53 "UMask": "0x1", 54 "EventName": "L1D_ALL_REF.ANY", 55 "SampleAfterValue": "2000000", 56 "BriefDescription": "All references to the L1 data cache" 57 }, 58 { 59 "EventCode": "0x43", 60 "Counter": "0,1", 61 "UMask": "0x2", 62 "EventName": "L1D_ALL_REF.CACHEABLE", 63 "SampleAfterValue": "2000000", 64 "BriefDescription": "L1 data cacheable reads and writes" 65 }, 66 { 67 "EventCode": "0x40", 68 "Counter": "0,1", 69 "UMask": "0x4", 70 "EventName": "L1D_CACHE_LD.E_STATE", 71 "SampleAfterValue": "2000000", 72 "BriefDescription": "L1 data cache read in E state" 73 }, 74 { 75 "EventCode": "0x40", 76 "Counter": "0,1", 77 "UMask": "0x1", 78 "EventName": "L1D_CACHE_LD.I_STATE", 79 "SampleAfterValue": "2000000", 80 "BriefDescription": "L1 data cache read in I state (misses)" 81 }, 82 { 83 "EventCode": "0x40", 84 "Counter": "0,1", 85 "UMask": "0x8", 86 "EventName": "L1D_CACHE_LD.M_STATE", 87 "SampleAfterValue": "2000000", 88 "BriefDescription": "L1 data cache read in M state" 89 }, 90 { 91 "EventCode": "0x40", 92 "Counter": "0,1", 93 "UMask": "0xf", 94 "EventName": "L1D_CACHE_LD.MESI", 95 "SampleAfterValue": "2000000", 96 "BriefDescription": "L1 data cache reads" 97 }, 98 { 99 "EventCode": "0x40", 100 "Counter": "0,1", 101 "UMask": "0x2", 102 "EventName": "L1D_CACHE_LD.S_STATE", 103 "SampleAfterValue": "2000000", 104 "BriefDescription": "L1 data cache read in S state" 105 }, 106 { 107 "EventCode": "0x42", 108 "Counter": "0,1", 109 "UMask": "0x4", 110 "EventName": "L1D_CACHE_LOCK.E_STATE", 111 "SampleAfterValue": "2000000", 112 "BriefDescription": "L1 data cache load locks in E state" 113 }, 114 { 115 "EventCode": "0x42", 116 "Counter": "0,1", 117 "UMask": "0x1", 118 "EventName": "L1D_CACHE_LOCK.HIT", 119 "SampleAfterValue": "2000000", 120 "BriefDescription": "L1 data cache load lock hits" 121 }, 122 { 123 "EventCode": "0x42", 124 "Counter": "0,1", 125 "UMask": "0x8", 126 "EventName": "L1D_CACHE_LOCK.M_STATE", 127 "SampleAfterValue": "2000000", 128 "BriefDescription": "L1 data cache load locks in M state" 129 }, 130 { 131 "EventCode": "0x42", 132 "Counter": "0,1", 133 "UMask": "0x2", 134 "EventName": "L1D_CACHE_LOCK.S_STATE", 135 "SampleAfterValue": "2000000", 136 "BriefDescription": "L1 data cache load locks in S state" 137 }, 138 { 139 "EventCode": "0x53", 140 "Counter": "0,1", 141 "UMask": "0x1", 142 "EventName": "L1D_CACHE_LOCK_FB_HIT", 143 "SampleAfterValue": "2000000", 144 "BriefDescription": "L1D load lock accepted in fill buffer" 145 }, 146 { 147 "EventCode": "0x52", 148 "Counter": "0,1", 149 "UMask": "0x1", 150 "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", 151 "SampleAfterValue": "2000000", 152 "BriefDescription": "L1D prefetch load lock accepted in fill buffer" 153 }, 154 { 155 "EventCode": "0x41", 156 "Counter": "0,1", 157 "UMask": "0x4", 158 "EventName": "L1D_CACHE_ST.E_STATE", 159 "SampleAfterValue": "2000000", 160 "BriefDescription": "L1 data cache stores in E state" 161 }, 162 { 163 "EventCode": "0x41", 164 "Counter": "0,1", 165 "UMask": "0x8", 166 "EventName": "L1D_CACHE_ST.M_STATE", 167 "SampleAfterValue": "2000000", 168 "BriefDescription": "L1 data cache stores in M state" 169 }, 170 { 171 "EventCode": "0x41", 172 "Counter": "0,1", 173 "UMask": "0x2", 174 "EventName": "L1D_CACHE_ST.S_STATE", 175 "SampleAfterValue": "2000000", 176 "BriefDescription": "L1 data cache stores in S state" 177 }, 178 { 179 "EventCode": "0x4E", 180 "Counter": "0,1", 181 "UMask": "0x2", 182 "EventName": "L1D_PREFETCH.MISS", 183 "SampleAfterValue": "200000", 184 "BriefDescription": "L1D hardware prefetch misses" 185 }, 186 { 187 "EventCode": "0x4E", 188 "Counter": "0,1", 189 "UMask": "0x1", 190 "EventName": "L1D_PREFETCH.REQUESTS", 191 "SampleAfterValue": "200000", 192 "BriefDescription": "L1D hardware prefetch requests" 193 }, 194 { 195 "EventCode": "0x4E", 196 "Counter": "0,1", 197 "UMask": "0x4", 198 "EventName": "L1D_PREFETCH.TRIGGERS", 199 "SampleAfterValue": "200000", 200 "BriefDescription": "L1D hardware prefetch requests triggered" 201 }, 202 { 203 "EventCode": "0x28", 204 "Counter": "0,1,2,3", 205 "UMask": "0x4", 206 "EventName": "L1D_WB_L2.E_STATE", 207 "SampleAfterValue": "100000", 208 "BriefDescription": "L1 writebacks to L2 in E state" 209 }, 210 { 211 "EventCode": "0x28", 212 "Counter": "0,1,2,3", 213 "UMask": "0x1", 214 "EventName": "L1D_WB_L2.I_STATE", 215 "SampleAfterValue": "100000", 216 "BriefDescription": "L1 writebacks to L2 in I state (misses)" 217 }, 218 { 219 "EventCode": "0x28", 220 "Counter": "0,1,2,3", 221 "UMask": "0x8", 222 "EventName": "L1D_WB_L2.M_STATE", 223 "SampleAfterValue": "100000", 224 "BriefDescription": "L1 writebacks to L2 in M state" 225 }, 226 { 227 "EventCode": "0x28", 228 "Counter": "0,1,2,3", 229 "UMask": "0xf", 230 "EventName": "L1D_WB_L2.MESI", 231 "SampleAfterValue": "100000", 232 "BriefDescription": "All L1 writebacks to L2" 233 }, 234 { 235 "EventCode": "0x28", 236 "Counter": "0,1,2,3", 237 "UMask": "0x2", 238 "EventName": "L1D_WB_L2.S_STATE", 239 "SampleAfterValue": "100000", 240 "BriefDescription": "L1 writebacks to L2 in S state" 241 }, 242 { 243 "EventCode": "0x26", 244 "Counter": "0,1,2,3", 245 "UMask": "0xff", 246 "EventName": "L2_DATA_RQSTS.ANY", 247 "SampleAfterValue": "200000", 248 "BriefDescription": "All L2 data requests" 249 }, 250 { 251 "EventCode": "0x26", 252 "Counter": "0,1,2,3", 253 "UMask": "0x4", 254 "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", 255 "SampleAfterValue": "200000", 256 "BriefDescription": "L2 data demand loads in E state" 257 }, 258 { 259 "EventCode": "0x26", 260 "Counter": "0,1,2,3", 261 "UMask": "0x1", 262 "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", 263 "SampleAfterValue": "200000", 264 "BriefDescription": "L2 data demand loads in I state (misses)" 265 }, 266 { 267 "EventCode": "0x26", 268 "Counter": "0,1,2,3", 269 "UMask": "0x8", 270 "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", 271 "SampleAfterValue": "200000", 272 "BriefDescription": "L2 data demand loads in M state" 273 }, 274 { 275 "EventCode": "0x26", 276 "Counter": "0,1,2,3", 277 "UMask": "0xf", 278 "EventName": "L2_DATA_RQSTS.DEMAND.MESI", 279 "SampleAfterValue": "200000", 280 "BriefDescription": "L2 data demand requests" 281 }, 282 { 283 "EventCode": "0x26", 284 "Counter": "0,1,2,3", 285 "UMask": "0x2", 286 "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", 287 "SampleAfterValue": "200000", 288 "BriefDescription": "L2 data demand loads in S state" 289 }, 290 { 291 "EventCode": "0x26", 292 "Counter": "0,1,2,3", 293 "UMask": "0x40", 294 "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", 295 "SampleAfterValue": "200000", 296 "BriefDescription": "L2 data prefetches in E state" 297 }, 298 { 299 "EventCode": "0x26", 300 "Counter": "0,1,2,3", 301 "UMask": "0x10", 302 "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", 303 "SampleAfterValue": "200000", 304 "BriefDescription": "L2 data prefetches in the I state (misses)" 305 }, 306 { 307 "EventCode": "0x26", 308 "Counter": "0,1,2,3", 309 "UMask": "0x80", 310 "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", 311 "SampleAfterValue": "200000", 312 "BriefDescription": "L2 data prefetches in M state" 313 }, 314 { 315 "EventCode": "0x26", 316 "Counter": "0,1,2,3", 317 "UMask": "0xf0", 318 "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", 319 "SampleAfterValue": "200000", 320 "BriefDescription": "All L2 data prefetches" 321 }, 322 { 323 "EventCode": "0x26", 324 "Counter": "0,1,2,3", 325 "UMask": "0x20", 326 "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", 327 "SampleAfterValue": "200000", 328 "BriefDescription": "L2 data prefetches in the S state" 329 }, 330 { 331 "EventCode": "0xF1", 332 "Counter": "0,1,2,3", 333 "UMask": "0x7", 334 "EventName": "L2_LINES_IN.ANY", 335 "SampleAfterValue": "100000", 336 "BriefDescription": "L2 lines alloacated" 337 }, 338 { 339 "EventCode": "0xF1", 340 "Counter": "0,1,2,3", 341 "UMask": "0x4", 342 "EventName": "L2_LINES_IN.E_STATE", 343 "SampleAfterValue": "100000", 344 "BriefDescription": "L2 lines allocated in the E state" 345 }, 346 { 347 "EventCode": "0xF1", 348 "Counter": "0,1,2,3", 349 "UMask": "0x2", 350 "EventName": "L2_LINES_IN.S_STATE", 351 "SampleAfterValue": "100000", 352 "BriefDescription": "L2 lines allocated in the S state" 353 }, 354 { 355 "EventCode": "0xF2", 356 "Counter": "0,1,2,3", 357 "UMask": "0xf", 358 "EventName": "L2_LINES_OUT.ANY", 359 "SampleAfterValue": "100000", 360 "BriefDescription": "L2 lines evicted" 361 }, 362 { 363 "EventCode": "0xF2", 364 "Counter": "0,1,2,3", 365 "UMask": "0x1", 366 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 367 "SampleAfterValue": "100000", 368 "BriefDescription": "L2 lines evicted by a demand request" 369 }, 370 { 371 "EventCode": "0xF2", 372 "Counter": "0,1,2,3", 373 "UMask": "0x2", 374 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 375 "SampleAfterValue": "100000", 376 "BriefDescription": "L2 modified lines evicted by a demand request" 377 }, 378 { 379 "EventCode": "0xF2", 380 "Counter": "0,1,2,3", 381 "UMask": "0x4", 382 "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", 383 "SampleAfterValue": "100000", 384 "BriefDescription": "L2 lines evicted by a prefetch request" 385 }, 386 { 387 "EventCode": "0xF2", 388 "Counter": "0,1,2,3", 389 "UMask": "0x8", 390 "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", 391 "SampleAfterValue": "100000", 392 "BriefDescription": "L2 modified lines evicted by a prefetch request" 393 }, 394 { 395 "EventCode": "0x24", 396 "Counter": "0,1,2,3", 397 "UMask": "0x10", 398 "EventName": "L2_RQSTS.IFETCH_HIT", 399 "SampleAfterValue": "200000", 400 "BriefDescription": "L2 instruction fetch hits" 401 }, 402 { 403 "EventCode": "0x24", 404 "Counter": "0,1,2,3", 405 "UMask": "0x20", 406 "EventName": "L2_RQSTS.IFETCH_MISS", 407 "SampleAfterValue": "200000", 408 "BriefDescription": "L2 instruction fetch misses" 409 }, 410 { 411 "EventCode": "0x24", 412 "Counter": "0,1,2,3", 413 "UMask": "0x30", 414 "EventName": "L2_RQSTS.IFETCHES", 415 "SampleAfterValue": "200000", 416 "BriefDescription": "L2 instruction fetches" 417 }, 418 { 419 "EventCode": "0x24", 420 "Counter": "0,1,2,3", 421 "UMask": "0x1", 422 "EventName": "L2_RQSTS.LD_HIT", 423 "SampleAfterValue": "200000", 424 "BriefDescription": "L2 load hits" 425 }, 426 { 427 "EventCode": "0x24", 428 "Counter": "0,1,2,3", 429 "UMask": "0x2", 430 "EventName": "L2_RQSTS.LD_MISS", 431 "SampleAfterValue": "200000", 432 "BriefDescription": "L2 load misses" 433 }, 434 { 435 "EventCode": "0x24", 436 "Counter": "0,1,2,3", 437 "UMask": "0x3", 438 "EventName": "L2_RQSTS.LOADS", 439 "SampleAfterValue": "200000", 440 "BriefDescription": "L2 requests" 441 }, 442 { 443 "EventCode": "0x24", 444 "Counter": "0,1,2,3", 445 "UMask": "0xaa", 446 "EventName": "L2_RQSTS.MISS", 447 "SampleAfterValue": "200000", 448 "BriefDescription": "All L2 misses" 449 }, 450 { 451 "EventCode": "0x24", 452 "Counter": "0,1,2,3", 453 "UMask": "0x40", 454 "EventName": "L2_RQSTS.PREFETCH_HIT", 455 "SampleAfterValue": "200000", 456 "BriefDescription": "L2 prefetch hits" 457 }, 458 { 459 "EventCode": "0x24", 460 "Counter": "0,1,2,3", 461 "UMask": "0x80", 462 "EventName": "L2_RQSTS.PREFETCH_MISS", 463 "SampleAfterValue": "200000", 464 "BriefDescription": "L2 prefetch misses" 465 }, 466 { 467 "EventCode": "0x24", 468 "Counter": "0,1,2,3", 469 "UMask": "0xc0", 470 "EventName": "L2_RQSTS.PREFETCHES", 471 "SampleAfterValue": "200000", 472 "BriefDescription": "All L2 prefetches" 473 }, 474 { 475 "EventCode": "0x24", 476 "Counter": "0,1,2,3", 477 "UMask": "0xff", 478 "EventName": "L2_RQSTS.REFERENCES", 479 "SampleAfterValue": "200000", 480 "BriefDescription": "All L2 requests" 481 }, 482 { 483 "EventCode": "0x24", 484 "Counter": "0,1,2,3", 485 "UMask": "0x4", 486 "EventName": "L2_RQSTS.RFO_HIT", 487 "SampleAfterValue": "200000", 488 "BriefDescription": "L2 RFO hits" 489 }, 490 { 491 "EventCode": "0x24", 492 "Counter": "0,1,2,3", 493 "UMask": "0x8", 494 "EventName": "L2_RQSTS.RFO_MISS", 495 "SampleAfterValue": "200000", 496 "BriefDescription": "L2 RFO misses" 497 }, 498 { 499 "EventCode": "0x24", 500 "Counter": "0,1,2,3", 501 "UMask": "0xc", 502 "EventName": "L2_RQSTS.RFOS", 503 "SampleAfterValue": "200000", 504 "BriefDescription": "L2 RFO requests" 505 }, 506 { 507 "EventCode": "0xF0", 508 "Counter": "0,1,2,3", 509 "UMask": "0x80", 510 "EventName": "L2_TRANSACTIONS.ANY", 511 "SampleAfterValue": "200000", 512 "BriefDescription": "All L2 transactions" 513 }, 514 { 515 "EventCode": "0xF0", 516 "Counter": "0,1,2,3", 517 "UMask": "0x20", 518 "EventName": "L2_TRANSACTIONS.FILL", 519 "SampleAfterValue": "200000", 520 "BriefDescription": "L2 fill transactions" 521 }, 522 { 523 "EventCode": "0xF0", 524 "Counter": "0,1,2,3", 525 "UMask": "0x4", 526 "EventName": "L2_TRANSACTIONS.IFETCH", 527 "SampleAfterValue": "200000", 528 "BriefDescription": "L2 instruction fetch transactions" 529 }, 530 { 531 "EventCode": "0xF0", 532 "Counter": "0,1,2,3", 533 "UMask": "0x10", 534 "EventName": "L2_TRANSACTIONS.L1D_WB", 535 "SampleAfterValue": "200000", 536 "BriefDescription": "L1D writeback to L2 transactions" 537 }, 538 { 539 "EventCode": "0xF0", 540 "Counter": "0,1,2,3", 541 "UMask": "0x1", 542 "EventName": "L2_TRANSACTIONS.LOAD", 543 "SampleAfterValue": "200000", 544 "BriefDescription": "L2 Load transactions" 545 }, 546 { 547 "EventCode": "0xF0", 548 "Counter": "0,1,2,3", 549 "UMask": "0x8", 550 "EventName": "L2_TRANSACTIONS.PREFETCH", 551 "SampleAfterValue": "200000", 552 "BriefDescription": "L2 prefetch transactions" 553 }, 554 { 555 "EventCode": "0xF0", 556 "Counter": "0,1,2,3", 557 "UMask": "0x2", 558 "EventName": "L2_TRANSACTIONS.RFO", 559 "SampleAfterValue": "200000", 560 "BriefDescription": "L2 RFO transactions" 561 }, 562 { 563 "EventCode": "0xF0", 564 "Counter": "0,1,2,3", 565 "UMask": "0x40", 566 "EventName": "L2_TRANSACTIONS.WB", 567 "SampleAfterValue": "200000", 568 "BriefDescription": "L2 writeback to LLC transactions" 569 }, 570 { 571 "EventCode": "0x27", 572 "Counter": "0,1,2,3", 573 "UMask": "0x40", 574 "EventName": "L2_WRITE.LOCK.E_STATE", 575 "SampleAfterValue": "100000", 576 "BriefDescription": "L2 demand lock RFOs in E state" 577 }, 578 { 579 "EventCode": "0x27", 580 "Counter": "0,1,2,3", 581 "UMask": "0xe0", 582 "EventName": "L2_WRITE.LOCK.HIT", 583 "SampleAfterValue": "100000", 584 "BriefDescription": "All demand L2 lock RFOs that hit the cache" 585 }, 586 { 587 "EventCode": "0x27", 588 "Counter": "0,1,2,3", 589 "UMask": "0x10", 590 "EventName": "L2_WRITE.LOCK.I_STATE", 591 "SampleAfterValue": "100000", 592 "BriefDescription": "L2 demand lock RFOs in I state (misses)" 593 }, 594 { 595 "EventCode": "0x27", 596 "Counter": "0,1,2,3", 597 "UMask": "0x80", 598 "EventName": "L2_WRITE.LOCK.M_STATE", 599 "SampleAfterValue": "100000", 600 "BriefDescription": "L2 demand lock RFOs in M state" 601 }, 602 { 603 "EventCode": "0x27", 604 "Counter": "0,1,2,3", 605 "UMask": "0xf0", 606 "EventName": "L2_WRITE.LOCK.MESI", 607 "SampleAfterValue": "100000", 608 "BriefDescription": "All demand L2 lock RFOs" 609 }, 610 { 611 "EventCode": "0x27", 612 "Counter": "0,1,2,3", 613 "UMask": "0x20", 614 "EventName": "L2_WRITE.LOCK.S_STATE", 615 "SampleAfterValue": "100000", 616 "BriefDescription": "L2 demand lock RFOs in S state" 617 }, 618 { 619 "EventCode": "0x27", 620 "Counter": "0,1,2,3", 621 "UMask": "0xe", 622 "EventName": "L2_WRITE.RFO.HIT", 623 "SampleAfterValue": "100000", 624 "BriefDescription": "All L2 demand store RFOs that hit the cache" 625 }, 626 { 627 "EventCode": "0x27", 628 "Counter": "0,1,2,3", 629 "UMask": "0x1", 630 "EventName": "L2_WRITE.RFO.I_STATE", 631 "SampleAfterValue": "100000", 632 "BriefDescription": "L2 demand store RFOs in I state (misses)" 633 }, 634 { 635 "EventCode": "0x27", 636 "Counter": "0,1,2,3", 637 "UMask": "0x8", 638 "EventName": "L2_WRITE.RFO.M_STATE", 639 "SampleAfterValue": "100000", 640 "BriefDescription": "L2 demand store RFOs in M state" 641 }, 642 { 643 "EventCode": "0x27", 644 "Counter": "0,1,2,3", 645 "UMask": "0xf", 646 "EventName": "L2_WRITE.RFO.MESI", 647 "SampleAfterValue": "100000", 648 "BriefDescription": "All L2 demand store RFOs" 649 }, 650 { 651 "EventCode": "0x27", 652 "Counter": "0,1,2,3", 653 "UMask": "0x2", 654 "EventName": "L2_WRITE.RFO.S_STATE", 655 "SampleAfterValue": "100000", 656 "BriefDescription": "L2 demand store RFOs in S state" 657 }, 658 { 659 "EventCode": "0x2E", 660 "Counter": "0,1,2,3", 661 "UMask": "0x41", 662 "EventName": "LONGEST_LAT_CACHE.MISS", 663 "SampleAfterValue": "100000", 664 "BriefDescription": "Longest latency cache miss" 665 }, 666 { 667 "EventCode": "0x2E", 668 "Counter": "0,1,2,3", 669 "UMask": "0x4f", 670 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 671 "SampleAfterValue": "200000", 672 "BriefDescription": "Longest latency cache reference" 673 }, 674 { 675 "PEBS": "1", 676 "EventCode": "0xB", 677 "Counter": "0,1,2,3", 678 "UMask": "0x1", 679 "EventName": "MEM_INST_RETIRED.LOADS", 680 "SampleAfterValue": "2000000", 681 "BriefDescription": "Instructions retired which contains a load (Precise Event)" 682 }, 683 { 684 "PEBS": "1", 685 "EventCode": "0xB", 686 "Counter": "0,1,2,3", 687 "UMask": "0x2", 688 "EventName": "MEM_INST_RETIRED.STORES", 689 "SampleAfterValue": "2000000", 690 "BriefDescription": "Instructions retired which contains a store (Precise Event)" 691 }, 692 { 693 "PEBS": "1", 694 "EventCode": "0xCB", 695 "Counter": "0,1,2,3", 696 "UMask": "0x40", 697 "EventName": "MEM_LOAD_RETIRED.HIT_LFB", 698 "SampleAfterValue": "200000", 699 "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)" 700 }, 701 { 702 "PEBS": "1", 703 "EventCode": "0xCB", 704 "Counter": "0,1,2,3", 705 "UMask": "0x1", 706 "EventName": "MEM_LOAD_RETIRED.L1D_HIT", 707 "SampleAfterValue": "2000000", 708 "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)" 709 }, 710 { 711 "PEBS": "1", 712 "EventCode": "0xCB", 713 "Counter": "0,1,2,3", 714 "UMask": "0x2", 715 "EventName": "MEM_LOAD_RETIRED.L2_HIT", 716 "SampleAfterValue": "200000", 717 "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)" 718 }, 719 { 720 "PEBS": "1", 721 "EventCode": "0xCB", 722 "Counter": "0,1,2,3", 723 "UMask": "0x10", 724 "EventName": "MEM_LOAD_RETIRED.LLC_MISS", 725 "SampleAfterValue": "10000", 726 "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)" 727 }, 728 { 729 "PEBS": "1", 730 "EventCode": "0xCB", 731 "Counter": "0,1,2,3", 732 "UMask": "0x4", 733 "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", 734 "SampleAfterValue": "40000", 735 "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)" 736 }, 737 { 738 "PEBS": "1", 739 "EventCode": "0xCB", 740 "Counter": "0,1,2,3", 741 "UMask": "0x8", 742 "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", 743 "SampleAfterValue": "40000", 744 "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)" 745 }, 746 { 747 "EventCode": "0xB0", 748 "Counter": "0,1,2,3", 749 "UMask": "0x40", 750 "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", 751 "SampleAfterValue": "100000", 752 "BriefDescription": "Offcore L1 data cache writebacks" 753 }, 754 { 755 "EventCode": "0xB2", 756 "Counter": "0,1,2,3", 757 "UMask": "0x1", 758 "EventName": "OFFCORE_REQUESTS_SQ_FULL", 759 "SampleAfterValue": "100000", 760 "BriefDescription": "Offcore requests blocked due to Super Queue full" 761 }, 762 { 763 "EventCode": "0xF4", 764 "Counter": "0,1,2,3", 765 "UMask": "0x10", 766 "EventName": "SQ_MISC.SPLIT_LOCK", 767 "SampleAfterValue": "2000000", 768 "BriefDescription": "Super Queue lock splits across a cache line" 769 }, 770 { 771 "EventCode": "0x6", 772 "Counter": "0,1,2,3", 773 "UMask": "0x4", 774 "EventName": "STORE_BLOCKS.AT_RET", 775 "SampleAfterValue": "200000", 776 "BriefDescription": "Loads delayed with at-Retirement block code" 777 }, 778 { 779 "EventCode": "0x6", 780 "Counter": "0,1,2,3", 781 "UMask": "0x8", 782 "EventName": "STORE_BLOCKS.L1D_BLOCK", 783 "SampleAfterValue": "200000", 784 "BriefDescription": "Cacheable loads delayed with L1D block code" 785 }, 786 { 787 "PEBS": "2", 788 "EventCode": "0xB", 789 "MSRValue": "0x0", 790 "Counter": "3", 791 "UMask": "0x10", 792 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", 793 "MSRIndex": "0x3F6", 794 "SampleAfterValue": "2000000", 795 "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)" 796 }, 797 { 798 "PEBS": "2", 799 "EventCode": "0xB", 800 "MSRValue": "0x400", 801 "Counter": "3", 802 "UMask": "0x10", 803 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", 804 "MSRIndex": "0x3F6", 805 "SampleAfterValue": "100", 806 "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)" 807 }, 808 { 809 "PEBS": "2", 810 "EventCode": "0xB", 811 "MSRValue": "0x80", 812 "Counter": "3", 813 "UMask": "0x10", 814 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", 815 "MSRIndex": "0x3F6", 816 "SampleAfterValue": "1000", 817 "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)" 818 }, 819 { 820 "PEBS": "2", 821 "EventCode": "0xB", 822 "MSRValue": "0x10", 823 "Counter": "3", 824 "UMask": "0x10", 825 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", 826 "MSRIndex": "0x3F6", 827 "SampleAfterValue": "10000", 828 "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)" 829 }, 830 { 831 "PEBS": "2", 832 "EventCode": "0xB", 833 "MSRValue": "0x4000", 834 "Counter": "3", 835 "UMask": "0x10", 836 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", 837 "MSRIndex": "0x3F6", 838 "SampleAfterValue": "5", 839 "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)" 840 }, 841 { 842 "PEBS": "2", 843 "EventCode": "0xB", 844 "MSRValue": "0x800", 845 "Counter": "3", 846 "UMask": "0x10", 847 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", 848 "MSRIndex": "0x3F6", 849 "SampleAfterValue": "50", 850 "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)" 851 }, 852 { 853 "PEBS": "2", 854 "EventCode": "0xB", 855 "MSRValue": "0x100", 856 "Counter": "3", 857 "UMask": "0x10", 858 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", 859 "MSRIndex": "0x3F6", 860 "SampleAfterValue": "500", 861 "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)" 862 }, 863 { 864 "PEBS": "2", 865 "EventCode": "0xB", 866 "MSRValue": "0x20", 867 "Counter": "3", 868 "UMask": "0x10", 869 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", 870 "MSRIndex": "0x3F6", 871 "SampleAfterValue": "5000", 872 "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)" 873 }, 874 { 875 "PEBS": "2", 876 "EventCode": "0xB", 877 "MSRValue": "0x8000", 878 "Counter": "3", 879 "UMask": "0x10", 880 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", 881 "MSRIndex": "0x3F6", 882 "SampleAfterValue": "3", 883 "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)" 884 }, 885 { 886 "PEBS": "2", 887 "EventCode": "0xB", 888 "MSRValue": "0x4", 889 "Counter": "3", 890 "UMask": "0x10", 891 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", 892 "MSRIndex": "0x3F6", 893 "SampleAfterValue": "50000", 894 "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)" 895 }, 896 { 897 "PEBS": "2", 898 "EventCode": "0xB", 899 "MSRValue": "0x1000", 900 "Counter": "3", 901 "UMask": "0x10", 902 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", 903 "MSRIndex": "0x3F6", 904 "SampleAfterValue": "20", 905 "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)" 906 }, 907 { 908 "PEBS": "2", 909 "EventCode": "0xB", 910 "MSRValue": "0x200", 911 "Counter": "3", 912 "UMask": "0x10", 913 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", 914 "MSRIndex": "0x3F6", 915 "SampleAfterValue": "200", 916 "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)" 917 }, 918 { 919 "PEBS": "2", 920 "EventCode": "0xB", 921 "MSRValue": "0x40", 922 "Counter": "3", 923 "UMask": "0x10", 924 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", 925 "MSRIndex": "0x3F6", 926 "SampleAfterValue": "2000", 927 "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)" 928 }, 929 { 930 "PEBS": "2", 931 "EventCode": "0xB", 932 "MSRValue": "0x8", 933 "Counter": "3", 934 "UMask": "0x10", 935 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", 936 "MSRIndex": "0x3F6", 937 "SampleAfterValue": "20000", 938 "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)" 939 }, 940 { 941 "PEBS": "2", 942 "EventCode": "0xB", 943 "MSRValue": "0x2000", 944 "Counter": "3", 945 "UMask": "0x10", 946 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", 947 "MSRIndex": "0x3F6", 948 "SampleAfterValue": "10", 949 "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)" 950 }, 951 { 952 "EventCode": "0xB7", 953 "MSRValue": "0x7F11", 954 "Counter": "2", 955 "UMask": "0x1", 956 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", 957 "MSRIndex": "0x1A6", 958 "SampleAfterValue": "100000", 959 "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", 960 "Offcore": "1" 961 }, 962 { 963 "EventCode": "0xB7", 964 "MSRValue": "0xFF11", 965 "Counter": "2", 966 "UMask": "0x1", 967 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", 968 "MSRIndex": "0x1A6", 969 "SampleAfterValue": "100000", 970 "BriefDescription": "All offcore data reads", 971 "Offcore": "1" 972 }, 973 { 974 "EventCode": "0xB7", 975 "MSRValue": "0x8011", 976 "Counter": "2", 977 "UMask": "0x1", 978 "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", 979 "MSRIndex": "0x1A6", 980 "SampleAfterValue": "100000", 981 "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", 982 "Offcore": "1" 983 }, 984 { 985 "EventCode": "0xB7", 986 "MSRValue": "0x111", 987 "Counter": "2", 988 "UMask": "0x1", 989 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", 990 "MSRIndex": "0x1A6", 991 "SampleAfterValue": "100000", 992 "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", 993 "Offcore": "1" 994 }, 995 { 996 "EventCode": "0xB7", 997 "MSRValue": "0x211", 998 "Counter": "2", 999 "UMask": "0x1", 1000 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", 1001 "MSRIndex": "0x1A6", 1002 "SampleAfterValue": "100000", 1003 "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", 1004 "Offcore": "1" 1005 }, 1006 { 1007 "EventCode": "0xB7", 1008 "MSRValue": "0x411", 1009 "Counter": "2", 1010 "UMask": "0x1", 1011 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", 1012 "MSRIndex": "0x1A6", 1013 "SampleAfterValue": "100000", 1014 "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", 1015 "Offcore": "1" 1016 }, 1017 { 1018 "EventCode": "0xB7", 1019 "MSRValue": "0x711", 1020 "Counter": "2", 1021 "UMask": "0x1", 1022 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", 1023 "MSRIndex": "0x1A6", 1024 "SampleAfterValue": "100000", 1025 "BriefDescription": "Offcore data reads satisfied by the LLC", 1026 "Offcore": "1" 1027 }, 1028 { 1029 "EventCode": "0xB7", 1030 "MSRValue": "0x4711", 1031 "Counter": "2", 1032 "UMask": "0x1", 1033 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", 1034 "MSRIndex": "0x1A6", 1035 "SampleAfterValue": "100000", 1036 "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", 1037 "Offcore": "1" 1038 }, 1039 { 1040 "EventCode": "0xB7", 1041 "MSRValue": "0x1811", 1042 "Counter": "2", 1043 "UMask": "0x1", 1044 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", 1045 "MSRIndex": "0x1A6", 1046 "SampleAfterValue": "100000", 1047 "BriefDescription": "Offcore data reads satisfied by a remote cache", 1048 "Offcore": "1" 1049 }, 1050 { 1051 "EventCode": "0xB7", 1052 "MSRValue": "0x3811", 1053 "Counter": "2", 1054 "UMask": "0x1", 1055 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", 1056 "MSRIndex": "0x1A6", 1057 "SampleAfterValue": "100000", 1058 "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", 1059 "Offcore": "1" 1060 }, 1061 { 1062 "EventCode": "0xB7", 1063 "MSRValue": "0x1011", 1064 "Counter": "2", 1065 "UMask": "0x1", 1066 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", 1067 "MSRIndex": "0x1A6", 1068 "SampleAfterValue": "100000", 1069 "BriefDescription": "Offcore data reads that HIT in a remote cache", 1070 "Offcore": "1" 1071 }, 1072 { 1073 "EventCode": "0xB7", 1074 "MSRValue": "0x811", 1075 "Counter": "2", 1076 "UMask": "0x1", 1077 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", 1078 "MSRIndex": "0x1A6", 1079 "SampleAfterValue": "100000", 1080 "BriefDescription": "Offcore data reads that HITM in a remote cache", 1081 "Offcore": "1" 1082 }, 1083 { 1084 "EventCode": "0xB7", 1085 "MSRValue": "0x7F44", 1086 "Counter": "2", 1087 "UMask": "0x1", 1088 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", 1089 "MSRIndex": "0x1A6", 1090 "SampleAfterValue": "100000", 1091 "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", 1092 "Offcore": "1" 1093 }, 1094 { 1095 "EventCode": "0xB7", 1096 "MSRValue": "0xFF44", 1097 "Counter": "2", 1098 "UMask": "0x1", 1099 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", 1100 "MSRIndex": "0x1A6", 1101 "SampleAfterValue": "100000", 1102 "BriefDescription": "All offcore code reads", 1103 "Offcore": "1" 1104 }, 1105 { 1106 "EventCode": "0xB7", 1107 "MSRValue": "0x8044", 1108 "Counter": "2", 1109 "UMask": "0x1", 1110 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", 1111 "MSRIndex": "0x1A6", 1112 "SampleAfterValue": "100000", 1113 "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", 1114 "Offcore": "1" 1115 }, 1116 { 1117 "EventCode": "0xB7", 1118 "MSRValue": "0x144", 1119 "Counter": "2", 1120 "UMask": "0x1", 1121 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", 1122 "MSRIndex": "0x1A6", 1123 "SampleAfterValue": "100000", 1124 "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", 1125 "Offcore": "1" 1126 }, 1127 { 1128 "EventCode": "0xB7", 1129 "MSRValue": "0x244", 1130 "Counter": "2", 1131 "UMask": "0x1", 1132 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1133 "MSRIndex": "0x1A6", 1134 "SampleAfterValue": "100000", 1135 "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", 1136 "Offcore": "1" 1137 }, 1138 { 1139 "EventCode": "0xB7", 1140 "MSRValue": "0x444", 1141 "Counter": "2", 1142 "UMask": "0x1", 1143 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1144 "MSRIndex": "0x1A6", 1145 "SampleAfterValue": "100000", 1146 "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", 1147 "Offcore": "1" 1148 }, 1149 { 1150 "EventCode": "0xB7", 1151 "MSRValue": "0x744", 1152 "Counter": "2", 1153 "UMask": "0x1", 1154 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", 1155 "MSRIndex": "0x1A6", 1156 "SampleAfterValue": "100000", 1157 "BriefDescription": "Offcore code reads satisfied by the LLC", 1158 "Offcore": "1" 1159 }, 1160 { 1161 "EventCode": "0xB7", 1162 "MSRValue": "0x4744", 1163 "Counter": "2", 1164 "UMask": "0x1", 1165 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", 1166 "MSRIndex": "0x1A6", 1167 "SampleAfterValue": "100000", 1168 "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", 1169 "Offcore": "1" 1170 }, 1171 { 1172 "EventCode": "0xB7", 1173 "MSRValue": "0x1844", 1174 "Counter": "2", 1175 "UMask": "0x1", 1176 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", 1177 "MSRIndex": "0x1A6", 1178 "SampleAfterValue": "100000", 1179 "BriefDescription": "Offcore code reads satisfied by a remote cache", 1180 "Offcore": "1" 1181 }, 1182 { 1183 "EventCode": "0xB7", 1184 "MSRValue": "0x3844", 1185 "Counter": "2", 1186 "UMask": "0x1", 1187 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", 1188 "MSRIndex": "0x1A6", 1189 "SampleAfterValue": "100000", 1190 "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", 1191 "Offcore": "1" 1192 }, 1193 { 1194 "EventCode": "0xB7", 1195 "MSRValue": "0x1044", 1196 "Counter": "2", 1197 "UMask": "0x1", 1198 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", 1199 "MSRIndex": "0x1A6", 1200 "SampleAfterValue": "100000", 1201 "BriefDescription": "Offcore code reads that HIT in a remote cache", 1202 "Offcore": "1" 1203 }, 1204 { 1205 "EventCode": "0xB7", 1206 "MSRValue": "0x844", 1207 "Counter": "2", 1208 "UMask": "0x1", 1209 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", 1210 "MSRIndex": "0x1A6", 1211 "SampleAfterValue": "100000", 1212 "BriefDescription": "Offcore code reads that HITM in a remote cache", 1213 "Offcore": "1" 1214 }, 1215 { 1216 "EventCode": "0xB7", 1217 "MSRValue": "0x7FFF", 1218 "Counter": "2", 1219 "UMask": "0x1", 1220 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", 1221 "MSRIndex": "0x1A6", 1222 "SampleAfterValue": "100000", 1223 "BriefDescription": "Offcore requests satisfied by any cache or DRAM", 1224 "Offcore": "1" 1225 }, 1226 { 1227 "EventCode": "0xB7", 1228 "MSRValue": "0xFFFF", 1229 "Counter": "2", 1230 "UMask": "0x1", 1231 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", 1232 "MSRIndex": "0x1A6", 1233 "SampleAfterValue": "100000", 1234 "BriefDescription": "All offcore requests", 1235 "Offcore": "1" 1236 }, 1237 { 1238 "EventCode": "0xB7", 1239 "MSRValue": "0x80FF", 1240 "Counter": "2", 1241 "UMask": "0x1", 1242 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", 1243 "MSRIndex": "0x1A6", 1244 "SampleAfterValue": "100000", 1245 "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", 1246 "Offcore": "1" 1247 }, 1248 { 1249 "EventCode": "0xB7", 1250 "MSRValue": "0x1FF", 1251 "Counter": "2", 1252 "UMask": "0x1", 1253 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", 1254 "MSRIndex": "0x1A6", 1255 "SampleAfterValue": "100000", 1256 "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", 1257 "Offcore": "1" 1258 }, 1259 { 1260 "EventCode": "0xB7", 1261 "MSRValue": "0x2FF", 1262 "Counter": "2", 1263 "UMask": "0x1", 1264 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", 1265 "MSRIndex": "0x1A6", 1266 "SampleAfterValue": "100000", 1267 "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", 1268 "Offcore": "1" 1269 }, 1270 { 1271 "EventCode": "0xB7", 1272 "MSRValue": "0x4FF", 1273 "Counter": "2", 1274 "UMask": "0x1", 1275 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", 1276 "MSRIndex": "0x1A6", 1277 "SampleAfterValue": "100000", 1278 "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", 1279 "Offcore": "1" 1280 }, 1281 { 1282 "EventCode": "0xB7", 1283 "MSRValue": "0x7FF", 1284 "Counter": "2", 1285 "UMask": "0x1", 1286 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", 1287 "MSRIndex": "0x1A6", 1288 "SampleAfterValue": "100000", 1289 "BriefDescription": "Offcore requests satisfied by the LLC", 1290 "Offcore": "1" 1291 }, 1292 { 1293 "EventCode": "0xB7", 1294 "MSRValue": "0x47FF", 1295 "Counter": "2", 1296 "UMask": "0x1", 1297 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", 1298 "MSRIndex": "0x1A6", 1299 "SampleAfterValue": "100000", 1300 "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", 1301 "Offcore": "1" 1302 }, 1303 { 1304 "EventCode": "0xB7", 1305 "MSRValue": "0x18FF", 1306 "Counter": "2", 1307 "UMask": "0x1", 1308 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", 1309 "MSRIndex": "0x1A6", 1310 "SampleAfterValue": "100000", 1311 "BriefDescription": "Offcore requests satisfied by a remote cache", 1312 "Offcore": "1" 1313 }, 1314 { 1315 "EventCode": "0xB7", 1316 "MSRValue": "0x38FF", 1317 "Counter": "2", 1318 "UMask": "0x1", 1319 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", 1320 "MSRIndex": "0x1A6", 1321 "SampleAfterValue": "100000", 1322 "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", 1323 "Offcore": "1" 1324 }, 1325 { 1326 "EventCode": "0xB7", 1327 "MSRValue": "0x10FF", 1328 "Counter": "2", 1329 "UMask": "0x1", 1330 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", 1331 "MSRIndex": "0x1A6", 1332 "SampleAfterValue": "100000", 1333 "BriefDescription": "Offcore requests that HIT in a remote cache", 1334 "Offcore": "1" 1335 }, 1336 { 1337 "EventCode": "0xB7", 1338 "MSRValue": "0x8FF", 1339 "Counter": "2", 1340 "UMask": "0x1", 1341 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", 1342 "MSRIndex": "0x1A6", 1343 "SampleAfterValue": "100000", 1344 "BriefDescription": "Offcore requests that HITM in a remote cache", 1345 "Offcore": "1" 1346 }, 1347 { 1348 "EventCode": "0xB7", 1349 "MSRValue": "0x7F22", 1350 "Counter": "2", 1351 "UMask": "0x1", 1352 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", 1353 "MSRIndex": "0x1A6", 1354 "SampleAfterValue": "100000", 1355 "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", 1356 "Offcore": "1" 1357 }, 1358 { 1359 "EventCode": "0xB7", 1360 "MSRValue": "0xFF22", 1361 "Counter": "2", 1362 "UMask": "0x1", 1363 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", 1364 "MSRIndex": "0x1A6", 1365 "SampleAfterValue": "100000", 1366 "BriefDescription": "All offcore RFO requests", 1367 "Offcore": "1" 1368 }, 1369 { 1370 "EventCode": "0xB7", 1371 "MSRValue": "0x8022", 1372 "Counter": "2", 1373 "UMask": "0x1", 1374 "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", 1375 "MSRIndex": "0x1A6", 1376 "SampleAfterValue": "100000", 1377 "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", 1378 "Offcore": "1" 1379 }, 1380 { 1381 "EventCode": "0xB7", 1382 "MSRValue": "0x122", 1383 "Counter": "2", 1384 "UMask": "0x1", 1385 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", 1386 "MSRIndex": "0x1A6", 1387 "SampleAfterValue": "100000", 1388 "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", 1389 "Offcore": "1" 1390 }, 1391 { 1392 "EventCode": "0xB7", 1393 "MSRValue": "0x222", 1394 "Counter": "2", 1395 "UMask": "0x1", 1396 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", 1397 "MSRIndex": "0x1A6", 1398 "SampleAfterValue": "100000", 1399 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", 1400 "Offcore": "1" 1401 }, 1402 { 1403 "EventCode": "0xB7", 1404 "MSRValue": "0x422", 1405 "Counter": "2", 1406 "UMask": "0x1", 1407 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", 1408 "MSRIndex": "0x1A6", 1409 "SampleAfterValue": "100000", 1410 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", 1411 "Offcore": "1" 1412 }, 1413 { 1414 "EventCode": "0xB7", 1415 "MSRValue": "0x722", 1416 "Counter": "2", 1417 "UMask": "0x1", 1418 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", 1419 "MSRIndex": "0x1A6", 1420 "SampleAfterValue": "100000", 1421 "BriefDescription": "Offcore RFO requests satisfied by the LLC", 1422 "Offcore": "1" 1423 }, 1424 { 1425 "EventCode": "0xB7", 1426 "MSRValue": "0x4722", 1427 "Counter": "2", 1428 "UMask": "0x1", 1429 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", 1430 "MSRIndex": "0x1A6", 1431 "SampleAfterValue": "100000", 1432 "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", 1433 "Offcore": "1" 1434 }, 1435 { 1436 "EventCode": "0xB7", 1437 "MSRValue": "0x1822", 1438 "Counter": "2", 1439 "UMask": "0x1", 1440 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", 1441 "MSRIndex": "0x1A6", 1442 "SampleAfterValue": "100000", 1443 "BriefDescription": "Offcore RFO requests satisfied by a remote cache", 1444 "Offcore": "1" 1445 }, 1446 { 1447 "EventCode": "0xB7", 1448 "MSRValue": "0x3822", 1449 "Counter": "2", 1450 "UMask": "0x1", 1451 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", 1452 "MSRIndex": "0x1A6", 1453 "SampleAfterValue": "100000", 1454 "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", 1455 "Offcore": "1" 1456 }, 1457 { 1458 "EventCode": "0xB7", 1459 "MSRValue": "0x1022", 1460 "Counter": "2", 1461 "UMask": "0x1", 1462 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", 1463 "MSRIndex": "0x1A6", 1464 "SampleAfterValue": "100000", 1465 "BriefDescription": "Offcore RFO requests that HIT in a remote cache", 1466 "Offcore": "1" 1467 }, 1468 { 1469 "EventCode": "0xB7", 1470 "MSRValue": "0x822", 1471 "Counter": "2", 1472 "UMask": "0x1", 1473 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", 1474 "MSRIndex": "0x1A6", 1475 "SampleAfterValue": "100000", 1476 "BriefDescription": "Offcore RFO requests that HITM in a remote cache", 1477 "Offcore": "1" 1478 }, 1479 { 1480 "EventCode": "0xB7", 1481 "MSRValue": "0x7F08", 1482 "Counter": "2", 1483 "UMask": "0x1", 1484 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", 1485 "MSRIndex": "0x1A6", 1486 "SampleAfterValue": "100000", 1487 "BriefDescription": "Offcore writebacks to any cache or DRAM.", 1488 "Offcore": "1" 1489 }, 1490 { 1491 "EventCode": "0xB7", 1492 "MSRValue": "0xFF08", 1493 "Counter": "2", 1494 "UMask": "0x1", 1495 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", 1496 "MSRIndex": "0x1A6", 1497 "SampleAfterValue": "100000", 1498 "BriefDescription": "All offcore writebacks", 1499 "Offcore": "1" 1500 }, 1501 { 1502 "EventCode": "0xB7", 1503 "MSRValue": "0x8008", 1504 "Counter": "2", 1505 "UMask": "0x1", 1506 "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", 1507 "MSRIndex": "0x1A6", 1508 "SampleAfterValue": "100000", 1509 "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", 1510 "Offcore": "1" 1511 }, 1512 { 1513 "EventCode": "0xB7", 1514 "MSRValue": "0x108", 1515 "Counter": "2", 1516 "UMask": "0x1", 1517 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", 1518 "MSRIndex": "0x1A6", 1519 "SampleAfterValue": "100000", 1520 "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", 1521 "Offcore": "1" 1522 }, 1523 { 1524 "EventCode": "0xB7", 1525 "MSRValue": "0x408", 1526 "Counter": "2", 1527 "UMask": "0x1", 1528 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", 1529 "MSRIndex": "0x1A6", 1530 "SampleAfterValue": "100000", 1531 "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", 1532 "Offcore": "1" 1533 }, 1534 { 1535 "EventCode": "0xB7", 1536 "MSRValue": "0x708", 1537 "Counter": "2", 1538 "UMask": "0x1", 1539 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", 1540 "MSRIndex": "0x1A6", 1541 "SampleAfterValue": "100000", 1542 "BriefDescription": "Offcore writebacks to the LLC", 1543 "Offcore": "1" 1544 }, 1545 { 1546 "EventCode": "0xB7", 1547 "MSRValue": "0x4708", 1548 "Counter": "2", 1549 "UMask": "0x1", 1550 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", 1551 "MSRIndex": "0x1A6", 1552 "SampleAfterValue": "100000", 1553 "BriefDescription": "Offcore writebacks to the LLC or local DRAM", 1554 "Offcore": "1" 1555 }, 1556 { 1557 "EventCode": "0xB7", 1558 "MSRValue": "0x1808", 1559 "Counter": "2", 1560 "UMask": "0x1", 1561 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", 1562 "MSRIndex": "0x1A6", 1563 "SampleAfterValue": "100000", 1564 "BriefDescription": "Offcore writebacks to a remote cache", 1565 "Offcore": "1" 1566 }, 1567 { 1568 "EventCode": "0xB7", 1569 "MSRValue": "0x3808", 1570 "Counter": "2", 1571 "UMask": "0x1", 1572 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", 1573 "MSRIndex": "0x1A6", 1574 "SampleAfterValue": "100000", 1575 "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", 1576 "Offcore": "1" 1577 }, 1578 { 1579 "EventCode": "0xB7", 1580 "MSRValue": "0x1008", 1581 "Counter": "2", 1582 "UMask": "0x1", 1583 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", 1584 "MSRIndex": "0x1A6", 1585 "SampleAfterValue": "100000", 1586 "BriefDescription": "Offcore writebacks that HIT in a remote cache", 1587 "Offcore": "1" 1588 }, 1589 { 1590 "EventCode": "0xB7", 1591 "MSRValue": "0x808", 1592 "Counter": "2", 1593 "UMask": "0x1", 1594 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", 1595 "MSRIndex": "0x1A6", 1596 "SampleAfterValue": "100000", 1597 "BriefDescription": "Offcore writebacks that HITM in a remote cache", 1598 "Offcore": "1" 1599 }, 1600 { 1601 "EventCode": "0xB7", 1602 "MSRValue": "0x7F77", 1603 "Counter": "2", 1604 "UMask": "0x1", 1605 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", 1606 "MSRIndex": "0x1A6", 1607 "SampleAfterValue": "100000", 1608 "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", 1609 "Offcore": "1" 1610 }, 1611 { 1612 "EventCode": "0xB7", 1613 "MSRValue": "0xFF77", 1614 "Counter": "2", 1615 "UMask": "0x1", 1616 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", 1617 "MSRIndex": "0x1A6", 1618 "SampleAfterValue": "100000", 1619 "BriefDescription": "All offcore code or data read requests", 1620 "Offcore": "1" 1621 }, 1622 { 1623 "EventCode": "0xB7", 1624 "MSRValue": "0x8077", 1625 "Counter": "2", 1626 "UMask": "0x1", 1627 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", 1628 "MSRIndex": "0x1A6", 1629 "SampleAfterValue": "100000", 1630 "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", 1631 "Offcore": "1" 1632 }, 1633 { 1634 "EventCode": "0xB7", 1635 "MSRValue": "0x177", 1636 "Counter": "2", 1637 "UMask": "0x1", 1638 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", 1639 "MSRIndex": "0x1A6", 1640 "SampleAfterValue": "100000", 1641 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", 1642 "Offcore": "1" 1643 }, 1644 { 1645 "EventCode": "0xB7", 1646 "MSRValue": "0x277", 1647 "Counter": "2", 1648 "UMask": "0x1", 1649 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1650 "MSRIndex": "0x1A6", 1651 "SampleAfterValue": "100000", 1652 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", 1653 "Offcore": "1" 1654 }, 1655 { 1656 "EventCode": "0xB7", 1657 "MSRValue": "0x477", 1658 "Counter": "2", 1659 "UMask": "0x1", 1660 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1661 "MSRIndex": "0x1A6", 1662 "SampleAfterValue": "100000", 1663 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", 1664 "Offcore": "1" 1665 }, 1666 { 1667 "EventCode": "0xB7", 1668 "MSRValue": "0x777", 1669 "Counter": "2", 1670 "UMask": "0x1", 1671 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", 1672 "MSRIndex": "0x1A6", 1673 "SampleAfterValue": "100000", 1674 "BriefDescription": "Offcore code or data read requests satisfied by the LLC", 1675 "Offcore": "1" 1676 }, 1677 { 1678 "EventCode": "0xB7", 1679 "MSRValue": "0x4777", 1680 "Counter": "2", 1681 "UMask": "0x1", 1682 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", 1683 "MSRIndex": "0x1A6", 1684 "SampleAfterValue": "100000", 1685 "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", 1686 "Offcore": "1" 1687 }, 1688 { 1689 "EventCode": "0xB7", 1690 "MSRValue": "0x1877", 1691 "Counter": "2", 1692 "UMask": "0x1", 1693 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", 1694 "MSRIndex": "0x1A6", 1695 "SampleAfterValue": "100000", 1696 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", 1697 "Offcore": "1" 1698 }, 1699 { 1700 "EventCode": "0xB7", 1701 "MSRValue": "0x3877", 1702 "Counter": "2", 1703 "UMask": "0x1", 1704 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", 1705 "MSRIndex": "0x1A6", 1706 "SampleAfterValue": "100000", 1707 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", 1708 "Offcore": "1" 1709 }, 1710 { 1711 "EventCode": "0xB7", 1712 "MSRValue": "0x1077", 1713 "Counter": "2", 1714 "UMask": "0x1", 1715 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", 1716 "MSRIndex": "0x1A6", 1717 "SampleAfterValue": "100000", 1718 "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", 1719 "Offcore": "1" 1720 }, 1721 { 1722 "EventCode": "0xB7", 1723 "MSRValue": "0x877", 1724 "Counter": "2", 1725 "UMask": "0x1", 1726 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", 1727 "MSRIndex": "0x1A6", 1728 "SampleAfterValue": "100000", 1729 "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", 1730 "Offcore": "1" 1731 }, 1732 { 1733 "EventCode": "0xB7", 1734 "MSRValue": "0x7F33", 1735 "Counter": "2", 1736 "UMask": "0x1", 1737 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", 1738 "MSRIndex": "0x1A6", 1739 "SampleAfterValue": "100000", 1740 "BriefDescription": "Offcore request = all data, response = any cache_dram", 1741 "Offcore": "1" 1742 }, 1743 { 1744 "EventCode": "0xB7", 1745 "MSRValue": "0xFF33", 1746 "Counter": "2", 1747 "UMask": "0x1", 1748 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", 1749 "MSRIndex": "0x1A6", 1750 "SampleAfterValue": "100000", 1751 "BriefDescription": "Offcore request = all data, response = any location", 1752 "Offcore": "1" 1753 }, 1754 { 1755 "EventCode": "0xB7", 1756 "MSRValue": "0x8033", 1757 "Counter": "2", 1758 "UMask": "0x1", 1759 "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", 1760 "MSRIndex": "0x1A6", 1761 "SampleAfterValue": "100000", 1762 "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit", 1763 "Offcore": "1" 1764 }, 1765 { 1766 "EventCode": "0xB7", 1767 "MSRValue": "0x133", 1768 "Counter": "2", 1769 "UMask": "0x1", 1770 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", 1771 "MSRIndex": "0x1A6", 1772 "SampleAfterValue": "100000", 1773 "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core", 1774 "Offcore": "1" 1775 }, 1776 { 1777 "EventCode": "0xB7", 1778 "MSRValue": "0x233", 1779 "Counter": "2", 1780 "UMask": "0x1", 1781 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", 1782 "MSRIndex": "0x1A6", 1783 "SampleAfterValue": "100000", 1784 "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core", 1785 "Offcore": "1" 1786 }, 1787 { 1788 "EventCode": "0xB7", 1789 "MSRValue": "0x433", 1790 "Counter": "2", 1791 "UMask": "0x1", 1792 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", 1793 "MSRIndex": "0x1A6", 1794 "SampleAfterValue": "100000", 1795 "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HITM in a sibling core", 1796 "Offcore": "1" 1797 }, 1798 { 1799 "EventCode": "0xB7", 1800 "MSRValue": "0x733", 1801 "Counter": "2", 1802 "UMask": "0x1", 1803 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", 1804 "MSRIndex": "0x1A6", 1805 "SampleAfterValue": "100000", 1806 "BriefDescription": "Offcore request = all data, response = local cache", 1807 "Offcore": "1" 1808 }, 1809 { 1810 "EventCode": "0xB7", 1811 "MSRValue": "0x4733", 1812 "Counter": "2", 1813 "UMask": "0x1", 1814 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", 1815 "MSRIndex": "0x1A6", 1816 "SampleAfterValue": "100000", 1817 "BriefDescription": "Offcore request = all data, response = local cache or dram", 1818 "Offcore": "1" 1819 }, 1820 { 1821 "EventCode": "0xB7", 1822 "MSRValue": "0x1833", 1823 "Counter": "2", 1824 "UMask": "0x1", 1825 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", 1826 "MSRIndex": "0x1A6", 1827 "SampleAfterValue": "100000", 1828 "BriefDescription": "Offcore request = all data, response = remote cache", 1829 "Offcore": "1" 1830 }, 1831 { 1832 "EventCode": "0xB7", 1833 "MSRValue": "0x3833", 1834 "Counter": "2", 1835 "UMask": "0x1", 1836 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", 1837 "MSRIndex": "0x1A6", 1838 "SampleAfterValue": "100000", 1839 "BriefDescription": "Offcore request = all data, response = remote cache or dram", 1840 "Offcore": "1" 1841 }, 1842 { 1843 "EventCode": "0xB7", 1844 "MSRValue": "0x1033", 1845 "Counter": "2", 1846 "UMask": "0x1", 1847 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", 1848 "MSRIndex": "0x1A6", 1849 "SampleAfterValue": "100000", 1850 "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache ", 1851 "Offcore": "1" 1852 }, 1853 { 1854 "EventCode": "0xB7", 1855 "MSRValue": "0x833", 1856 "Counter": "2", 1857 "UMask": "0x1", 1858 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", 1859 "MSRIndex": "0x1A6", 1860 "SampleAfterValue": "100000", 1861 "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache", 1862 "Offcore": "1" 1863 }, 1864 { 1865 "EventCode": "0xB7", 1866 "MSRValue": "0x7F03", 1867 "Counter": "2", 1868 "UMask": "0x1", 1869 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", 1870 "MSRIndex": "0x1A6", 1871 "SampleAfterValue": "100000", 1872 "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", 1873 "Offcore": "1" 1874 }, 1875 { 1876 "EventCode": "0xB7", 1877 "MSRValue": "0xFF03", 1878 "Counter": "2", 1879 "UMask": "0x1", 1880 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", 1881 "MSRIndex": "0x1A6", 1882 "SampleAfterValue": "100000", 1883 "BriefDescription": "All offcore demand data requests", 1884 "Offcore": "1" 1885 }, 1886 { 1887 "EventCode": "0xB7", 1888 "MSRValue": "0x8003", 1889 "Counter": "2", 1890 "UMask": "0x1", 1891 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", 1892 "MSRIndex": "0x1A6", 1893 "SampleAfterValue": "100000", 1894 "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", 1895 "Offcore": "1" 1896 }, 1897 { 1898 "EventCode": "0xB7", 1899 "MSRValue": "0x103", 1900 "Counter": "2", 1901 "UMask": "0x1", 1902 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", 1903 "MSRIndex": "0x1A6", 1904 "SampleAfterValue": "100000", 1905 "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", 1906 "Offcore": "1" 1907 }, 1908 { 1909 "EventCode": "0xB7", 1910 "MSRValue": "0x203", 1911 "Counter": "2", 1912 "UMask": "0x1", 1913 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", 1914 "MSRIndex": "0x1A6", 1915 "SampleAfterValue": "100000", 1916 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", 1917 "Offcore": "1" 1918 }, 1919 { 1920 "EventCode": "0xB7", 1921 "MSRValue": "0x403", 1922 "Counter": "2", 1923 "UMask": "0x1", 1924 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", 1925 "MSRIndex": "0x1A6", 1926 "SampleAfterValue": "100000", 1927 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", 1928 "Offcore": "1" 1929 }, 1930 { 1931 "EventCode": "0xB7", 1932 "MSRValue": "0x703", 1933 "Counter": "2", 1934 "UMask": "0x1", 1935 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", 1936 "MSRIndex": "0x1A6", 1937 "SampleAfterValue": "100000", 1938 "BriefDescription": "Offcore demand data requests satisfied by the LLC", 1939 "Offcore": "1" 1940 }, 1941 { 1942 "EventCode": "0xB7", 1943 "MSRValue": "0x4703", 1944 "Counter": "2", 1945 "UMask": "0x1", 1946 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", 1947 "MSRIndex": "0x1A6", 1948 "SampleAfterValue": "100000", 1949 "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", 1950 "Offcore": "1" 1951 }, 1952 { 1953 "EventCode": "0xB7", 1954 "MSRValue": "0x1803", 1955 "Counter": "2", 1956 "UMask": "0x1", 1957 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", 1958 "MSRIndex": "0x1A6", 1959 "SampleAfterValue": "100000", 1960 "BriefDescription": "Offcore demand data requests satisfied by a remote cache", 1961 "Offcore": "1" 1962 }, 1963 { 1964 "EventCode": "0xB7", 1965 "MSRValue": "0x3803", 1966 "Counter": "2", 1967 "UMask": "0x1", 1968 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", 1969 "MSRIndex": "0x1A6", 1970 "SampleAfterValue": "100000", 1971 "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", 1972 "Offcore": "1" 1973 }, 1974 { 1975 "EventCode": "0xB7", 1976 "MSRValue": "0x1003", 1977 "Counter": "2", 1978 "UMask": "0x1", 1979 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", 1980 "MSRIndex": "0x1A6", 1981 "SampleAfterValue": "100000", 1982 "BriefDescription": "Offcore demand data requests that HIT in a remote cache", 1983 "Offcore": "1" 1984 }, 1985 { 1986 "EventCode": "0xB7", 1987 "MSRValue": "0x803", 1988 "Counter": "2", 1989 "UMask": "0x1", 1990 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", 1991 "MSRIndex": "0x1A6", 1992 "SampleAfterValue": "100000", 1993 "BriefDescription": "Offcore demand data requests that HITM in a remote cache", 1994 "Offcore": "1" 1995 }, 1996 { 1997 "EventCode": "0xB7", 1998 "MSRValue": "0x7F01", 1999 "Counter": "2", 2000 "UMask": "0x1", 2001 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", 2002 "MSRIndex": "0x1A6", 2003 "SampleAfterValue": "100000", 2004 "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", 2005 "Offcore": "1" 2006 }, 2007 { 2008 "EventCode": "0xB7", 2009 "MSRValue": "0xFF01", 2010 "Counter": "2", 2011 "UMask": "0x1", 2012 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", 2013 "MSRIndex": "0x1A6", 2014 "SampleAfterValue": "100000", 2015 "BriefDescription": "All offcore demand data reads", 2016 "Offcore": "1" 2017 }, 2018 { 2019 "EventCode": "0xB7", 2020 "MSRValue": "0x8001", 2021 "Counter": "2", 2022 "UMask": "0x1", 2023 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", 2024 "MSRIndex": "0x1A6", 2025 "SampleAfterValue": "100000", 2026 "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", 2027 "Offcore": "1" 2028 }, 2029 { 2030 "EventCode": "0xB7", 2031 "MSRValue": "0x101", 2032 "Counter": "2", 2033 "UMask": "0x1", 2034 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", 2035 "MSRIndex": "0x1A6", 2036 "SampleAfterValue": "100000", 2037 "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", 2038 "Offcore": "1" 2039 }, 2040 { 2041 "EventCode": "0xB7", 2042 "MSRValue": "0x201", 2043 "Counter": "2", 2044 "UMask": "0x1", 2045 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 2046 "MSRIndex": "0x1A6", 2047 "SampleAfterValue": "100000", 2048 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", 2049 "Offcore": "1" 2050 }, 2051 { 2052 "EventCode": "0xB7", 2053 "MSRValue": "0x401", 2054 "Counter": "2", 2055 "UMask": "0x1", 2056 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 2057 "MSRIndex": "0x1A6", 2058 "SampleAfterValue": "100000", 2059 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", 2060 "Offcore": "1" 2061 }, 2062 { 2063 "EventCode": "0xB7", 2064 "MSRValue": "0x701", 2065 "Counter": "2", 2066 "UMask": "0x1", 2067 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", 2068 "MSRIndex": "0x1A6", 2069 "SampleAfterValue": "100000", 2070 "BriefDescription": "Offcore demand data reads satisfied by the LLC", 2071 "Offcore": "1" 2072 }, 2073 { 2074 "EventCode": "0xB7", 2075 "MSRValue": "0x4701", 2076 "Counter": "2", 2077 "UMask": "0x1", 2078 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", 2079 "MSRIndex": "0x1A6", 2080 "SampleAfterValue": "100000", 2081 "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", 2082 "Offcore": "1" 2083 }, 2084 { 2085 "EventCode": "0xB7", 2086 "MSRValue": "0x1801", 2087 "Counter": "2", 2088 "UMask": "0x1", 2089 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", 2090 "MSRIndex": "0x1A6", 2091 "SampleAfterValue": "100000", 2092 "BriefDescription": "Offcore demand data reads satisfied by a remote cache", 2093 "Offcore": "1" 2094 }, 2095 { 2096 "EventCode": "0xB7", 2097 "MSRValue": "0x3801", 2098 "Counter": "2", 2099 "UMask": "0x1", 2100 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", 2101 "MSRIndex": "0x1A6", 2102 "SampleAfterValue": "100000", 2103 "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", 2104 "Offcore": "1" 2105 }, 2106 { 2107 "EventCode": "0xB7", 2108 "MSRValue": "0x1001", 2109 "Counter": "2", 2110 "UMask": "0x1", 2111 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", 2112 "MSRIndex": "0x1A6", 2113 "SampleAfterValue": "100000", 2114 "BriefDescription": "Offcore demand data reads that HIT in a remote cache", 2115 "Offcore": "1" 2116 }, 2117 { 2118 "EventCode": "0xB7", 2119 "MSRValue": "0x801", 2120 "Counter": "2", 2121 "UMask": "0x1", 2122 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", 2123 "MSRIndex": "0x1A6", 2124 "SampleAfterValue": "100000", 2125 "BriefDescription": "Offcore demand data reads that HITM in a remote cache", 2126 "Offcore": "1" 2127 }, 2128 { 2129 "EventCode": "0xB7", 2130 "MSRValue": "0x7F04", 2131 "Counter": "2", 2132 "UMask": "0x1", 2133 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", 2134 "MSRIndex": "0x1A6", 2135 "SampleAfterValue": "100000", 2136 "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", 2137 "Offcore": "1" 2138 }, 2139 { 2140 "EventCode": "0xB7", 2141 "MSRValue": "0xFF04", 2142 "Counter": "2", 2143 "UMask": "0x1", 2144 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", 2145 "MSRIndex": "0x1A6", 2146 "SampleAfterValue": "100000", 2147 "BriefDescription": "All offcore demand code reads", 2148 "Offcore": "1" 2149 }, 2150 { 2151 "EventCode": "0xB7", 2152 "MSRValue": "0x8004", 2153 "Counter": "2", 2154 "UMask": "0x1", 2155 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", 2156 "MSRIndex": "0x1A6", 2157 "SampleAfterValue": "100000", 2158 "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", 2159 "Offcore": "1" 2160 }, 2161 { 2162 "EventCode": "0xB7", 2163 "MSRValue": "0x104", 2164 "Counter": "2", 2165 "UMask": "0x1", 2166 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", 2167 "MSRIndex": "0x1A6", 2168 "SampleAfterValue": "100000", 2169 "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", 2170 "Offcore": "1" 2171 }, 2172 { 2173 "EventCode": "0xB7", 2174 "MSRValue": "0x204", 2175 "Counter": "2", 2176 "UMask": "0x1", 2177 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2178 "MSRIndex": "0x1A6", 2179 "SampleAfterValue": "100000", 2180 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", 2181 "Offcore": "1" 2182 }, 2183 { 2184 "EventCode": "0xB7", 2185 "MSRValue": "0x404", 2186 "Counter": "2", 2187 "UMask": "0x1", 2188 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2189 "MSRIndex": "0x1A6", 2190 "SampleAfterValue": "100000", 2191 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", 2192 "Offcore": "1" 2193 }, 2194 { 2195 "EventCode": "0xB7", 2196 "MSRValue": "0x704", 2197 "Counter": "2", 2198 "UMask": "0x1", 2199 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", 2200 "MSRIndex": "0x1A6", 2201 "SampleAfterValue": "100000", 2202 "BriefDescription": "Offcore demand code reads satisfied by the LLC", 2203 "Offcore": "1" 2204 }, 2205 { 2206 "EventCode": "0xB7", 2207 "MSRValue": "0x4704", 2208 "Counter": "2", 2209 "UMask": "0x1", 2210 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", 2211 "MSRIndex": "0x1A6", 2212 "SampleAfterValue": "100000", 2213 "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", 2214 "Offcore": "1" 2215 }, 2216 { 2217 "EventCode": "0xB7", 2218 "MSRValue": "0x1804", 2219 "Counter": "2", 2220 "UMask": "0x1", 2221 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", 2222 "MSRIndex": "0x1A6", 2223 "SampleAfterValue": "100000", 2224 "BriefDescription": "Offcore demand code reads satisfied by a remote cache", 2225 "Offcore": "1" 2226 }, 2227 { 2228 "EventCode": "0xB7", 2229 "MSRValue": "0x3804", 2230 "Counter": "2", 2231 "UMask": "0x1", 2232 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", 2233 "MSRIndex": "0x1A6", 2234 "SampleAfterValue": "100000", 2235 "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", 2236 "Offcore": "1" 2237 }, 2238 { 2239 "EventCode": "0xB7", 2240 "MSRValue": "0x1004", 2241 "Counter": "2", 2242 "UMask": "0x1", 2243 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", 2244 "MSRIndex": "0x1A6", 2245 "SampleAfterValue": "100000", 2246 "BriefDescription": "Offcore demand code reads that HIT in a remote cache", 2247 "Offcore": "1" 2248 }, 2249 { 2250 "EventCode": "0xB7", 2251 "MSRValue": "0x804", 2252 "Counter": "2", 2253 "UMask": "0x1", 2254 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", 2255 "MSRIndex": "0x1A6", 2256 "SampleAfterValue": "100000", 2257 "BriefDescription": "Offcore demand code reads that HITM in a remote cache", 2258 "Offcore": "1" 2259 }, 2260 { 2261 "EventCode": "0xB7", 2262 "MSRValue": "0x7F02", 2263 "Counter": "2", 2264 "UMask": "0x1", 2265 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", 2266 "MSRIndex": "0x1A6", 2267 "SampleAfterValue": "100000", 2268 "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", 2269 "Offcore": "1" 2270 }, 2271 { 2272 "EventCode": "0xB7", 2273 "MSRValue": "0xFF02", 2274 "Counter": "2", 2275 "UMask": "0x1", 2276 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", 2277 "MSRIndex": "0x1A6", 2278 "SampleAfterValue": "100000", 2279 "BriefDescription": "All offcore demand RFO requests", 2280 "Offcore": "1" 2281 }, 2282 { 2283 "EventCode": "0xB7", 2284 "MSRValue": "0x8002", 2285 "Counter": "2", 2286 "UMask": "0x1", 2287 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", 2288 "MSRIndex": "0x1A6", 2289 "SampleAfterValue": "100000", 2290 "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", 2291 "Offcore": "1" 2292 }, 2293 { 2294 "EventCode": "0xB7", 2295 "MSRValue": "0x102", 2296 "Counter": "2", 2297 "UMask": "0x1", 2298 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", 2299 "MSRIndex": "0x1A6", 2300 "SampleAfterValue": "100000", 2301 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", 2302 "Offcore": "1" 2303 }, 2304 { 2305 "EventCode": "0xB7", 2306 "MSRValue": "0x202", 2307 "Counter": "2", 2308 "UMask": "0x1", 2309 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", 2310 "MSRIndex": "0x1A6", 2311 "SampleAfterValue": "100000", 2312 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", 2313 "Offcore": "1" 2314 }, 2315 { 2316 "EventCode": "0xB7", 2317 "MSRValue": "0x402", 2318 "Counter": "2", 2319 "UMask": "0x1", 2320 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", 2321 "MSRIndex": "0x1A6", 2322 "SampleAfterValue": "100000", 2323 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", 2324 "Offcore": "1" 2325 }, 2326 { 2327 "EventCode": "0xB7", 2328 "MSRValue": "0x702", 2329 "Counter": "2", 2330 "UMask": "0x1", 2331 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", 2332 "MSRIndex": "0x1A6", 2333 "SampleAfterValue": "100000", 2334 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", 2335 "Offcore": "1" 2336 }, 2337 { 2338 "EventCode": "0xB7", 2339 "MSRValue": "0x4702", 2340 "Counter": "2", 2341 "UMask": "0x1", 2342 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", 2343 "MSRIndex": "0x1A6", 2344 "SampleAfterValue": "100000", 2345 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", 2346 "Offcore": "1" 2347 }, 2348 { 2349 "EventCode": "0xB7", 2350 "MSRValue": "0x1802", 2351 "Counter": "2", 2352 "UMask": "0x1", 2353 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", 2354 "MSRIndex": "0x1A6", 2355 "SampleAfterValue": "100000", 2356 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", 2357 "Offcore": "1" 2358 }, 2359 { 2360 "EventCode": "0xB7", 2361 "MSRValue": "0x3802", 2362 "Counter": "2", 2363 "UMask": "0x1", 2364 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", 2365 "MSRIndex": "0x1A6", 2366 "SampleAfterValue": "100000", 2367 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", 2368 "Offcore": "1" 2369 }, 2370 { 2371 "EventCode": "0xB7", 2372 "MSRValue": "0x1002", 2373 "Counter": "2", 2374 "UMask": "0x1", 2375 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", 2376 "MSRIndex": "0x1A6", 2377 "SampleAfterValue": "100000", 2378 "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", 2379 "Offcore": "1" 2380 }, 2381 { 2382 "EventCode": "0xB7", 2383 "MSRValue": "0x802", 2384 "Counter": "2", 2385 "UMask": "0x1", 2386 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", 2387 "MSRIndex": "0x1A6", 2388 "SampleAfterValue": "100000", 2389 "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", 2390 "Offcore": "1" 2391 }, 2392 { 2393 "EventCode": "0xB7", 2394 "MSRValue": "0x7F80", 2395 "Counter": "2", 2396 "UMask": "0x1", 2397 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", 2398 "MSRIndex": "0x1A6", 2399 "SampleAfterValue": "100000", 2400 "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", 2401 "Offcore": "1" 2402 }, 2403 { 2404 "EventCode": "0xB7", 2405 "MSRValue": "0xFF80", 2406 "Counter": "2", 2407 "UMask": "0x1", 2408 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", 2409 "MSRIndex": "0x1A6", 2410 "SampleAfterValue": "100000", 2411 "BriefDescription": "All offcore other requests", 2412 "Offcore": "1" 2413 }, 2414 { 2415 "EventCode": "0xB7", 2416 "MSRValue": "0x8080", 2417 "Counter": "2", 2418 "UMask": "0x1", 2419 "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", 2420 "MSRIndex": "0x1A6", 2421 "SampleAfterValue": "100000", 2422 "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", 2423 "Offcore": "1" 2424 }, 2425 { 2426 "EventCode": "0xB7", 2427 "MSRValue": "0x180", 2428 "Counter": "2", 2429 "UMask": "0x1", 2430 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", 2431 "MSRIndex": "0x1A6", 2432 "SampleAfterValue": "100000", 2433 "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", 2434 "Offcore": "1" 2435 }, 2436 { 2437 "EventCode": "0xB7", 2438 "MSRValue": "0x280", 2439 "Counter": "2", 2440 "UMask": "0x1", 2441 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", 2442 "MSRIndex": "0x1A6", 2443 "SampleAfterValue": "100000", 2444 "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", 2445 "Offcore": "1" 2446 }, 2447 { 2448 "EventCode": "0xB7", 2449 "MSRValue": "0x480", 2450 "Counter": "2", 2451 "UMask": "0x1", 2452 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", 2453 "MSRIndex": "0x1A6", 2454 "SampleAfterValue": "100000", 2455 "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", 2456 "Offcore": "1" 2457 }, 2458 { 2459 "EventCode": "0xB7", 2460 "MSRValue": "0x780", 2461 "Counter": "2", 2462 "UMask": "0x1", 2463 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", 2464 "MSRIndex": "0x1A6", 2465 "SampleAfterValue": "100000", 2466 "BriefDescription": "Offcore other requests satisfied by the LLC", 2467 "Offcore": "1" 2468 }, 2469 { 2470 "EventCode": "0xB7", 2471 "MSRValue": "0x4780", 2472 "Counter": "2", 2473 "UMask": "0x1", 2474 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", 2475 "MSRIndex": "0x1A6", 2476 "SampleAfterValue": "100000", 2477 "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", 2478 "Offcore": "1" 2479 }, 2480 { 2481 "EventCode": "0xB7", 2482 "MSRValue": "0x1880", 2483 "Counter": "2", 2484 "UMask": "0x1", 2485 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", 2486 "MSRIndex": "0x1A6", 2487 "SampleAfterValue": "100000", 2488 "BriefDescription": "Offcore other requests satisfied by a remote cache", 2489 "Offcore": "1" 2490 }, 2491 { 2492 "EventCode": "0xB7", 2493 "MSRValue": "0x3880", 2494 "Counter": "2", 2495 "UMask": "0x1", 2496 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", 2497 "MSRIndex": "0x1A6", 2498 "SampleAfterValue": "100000", 2499 "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", 2500 "Offcore": "1" 2501 }, 2502 { 2503 "EventCode": "0xB7", 2504 "MSRValue": "0x1080", 2505 "Counter": "2", 2506 "UMask": "0x1", 2507 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", 2508 "MSRIndex": "0x1A6", 2509 "SampleAfterValue": "100000", 2510 "BriefDescription": "Offcore other requests that HIT in a remote cache", 2511 "Offcore": "1" 2512 }, 2513 { 2514 "EventCode": "0xB7", 2515 "MSRValue": "0x880", 2516 "Counter": "2", 2517 "UMask": "0x1", 2518 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", 2519 "MSRIndex": "0x1A6", 2520 "SampleAfterValue": "100000", 2521 "BriefDescription": "Offcore other requests that HITM in a remote cache", 2522 "Offcore": "1" 2523 }, 2524 { 2525 "EventCode": "0xB7", 2526 "MSRValue": "0x7F30", 2527 "Counter": "2", 2528 "UMask": "0x1", 2529 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", 2530 "MSRIndex": "0x1A6", 2531 "SampleAfterValue": "100000", 2532 "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", 2533 "Offcore": "1" 2534 }, 2535 { 2536 "EventCode": "0xB7", 2537 "MSRValue": "0xFF30", 2538 "Counter": "2", 2539 "UMask": "0x1", 2540 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", 2541 "MSRIndex": "0x1A6", 2542 "SampleAfterValue": "100000", 2543 "BriefDescription": "All offcore prefetch data requests", 2544 "Offcore": "1" 2545 }, 2546 { 2547 "EventCode": "0xB7", 2548 "MSRValue": "0x8030", 2549 "Counter": "2", 2550 "UMask": "0x1", 2551 "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", 2552 "MSRIndex": "0x1A6", 2553 "SampleAfterValue": "100000", 2554 "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", 2555 "Offcore": "1" 2556 }, 2557 { 2558 "EventCode": "0xB7", 2559 "MSRValue": "0x130", 2560 "Counter": "2", 2561 "UMask": "0x1", 2562 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", 2563 "MSRIndex": "0x1A6", 2564 "SampleAfterValue": "100000", 2565 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", 2566 "Offcore": "1" 2567 }, 2568 { 2569 "EventCode": "0xB7", 2570 "MSRValue": "0x230", 2571 "Counter": "2", 2572 "UMask": "0x1", 2573 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", 2574 "MSRIndex": "0x1A6", 2575 "SampleAfterValue": "100000", 2576 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", 2577 "Offcore": "1" 2578 }, 2579 { 2580 "EventCode": "0xB7", 2581 "MSRValue": "0x430", 2582 "Counter": "2", 2583 "UMask": "0x1", 2584 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", 2585 "MSRIndex": "0x1A6", 2586 "SampleAfterValue": "100000", 2587 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", 2588 "Offcore": "1" 2589 }, 2590 { 2591 "EventCode": "0xB7", 2592 "MSRValue": "0x730", 2593 "Counter": "2", 2594 "UMask": "0x1", 2595 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", 2596 "MSRIndex": "0x1A6", 2597 "SampleAfterValue": "100000", 2598 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", 2599 "Offcore": "1" 2600 }, 2601 { 2602 "EventCode": "0xB7", 2603 "MSRValue": "0x4730", 2604 "Counter": "2", 2605 "UMask": "0x1", 2606 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", 2607 "MSRIndex": "0x1A6", 2608 "SampleAfterValue": "100000", 2609 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", 2610 "Offcore": "1" 2611 }, 2612 { 2613 "EventCode": "0xB7", 2614 "MSRValue": "0x1830", 2615 "Counter": "2", 2616 "UMask": "0x1", 2617 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", 2618 "MSRIndex": "0x1A6", 2619 "SampleAfterValue": "100000", 2620 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", 2621 "Offcore": "1" 2622 }, 2623 { 2624 "EventCode": "0xB7", 2625 "MSRValue": "0x3830", 2626 "Counter": "2", 2627 "UMask": "0x1", 2628 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", 2629 "MSRIndex": "0x1A6", 2630 "SampleAfterValue": "100000", 2631 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", 2632 "Offcore": "1" 2633 }, 2634 { 2635 "EventCode": "0xB7", 2636 "MSRValue": "0x1030", 2637 "Counter": "2", 2638 "UMask": "0x1", 2639 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", 2640 "MSRIndex": "0x1A6", 2641 "SampleAfterValue": "100000", 2642 "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", 2643 "Offcore": "1" 2644 }, 2645 { 2646 "EventCode": "0xB7", 2647 "MSRValue": "0x830", 2648 "Counter": "2", 2649 "UMask": "0x1", 2650 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", 2651 "MSRIndex": "0x1A6", 2652 "SampleAfterValue": "100000", 2653 "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", 2654 "Offcore": "1" 2655 }, 2656 { 2657 "EventCode": "0xB7", 2658 "MSRValue": "0x7F10", 2659 "Counter": "2", 2660 "UMask": "0x1", 2661 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", 2662 "MSRIndex": "0x1A6", 2663 "SampleAfterValue": "100000", 2664 "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", 2665 "Offcore": "1" 2666 }, 2667 { 2668 "EventCode": "0xB7", 2669 "MSRValue": "0xFF10", 2670 "Counter": "2", 2671 "UMask": "0x1", 2672 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", 2673 "MSRIndex": "0x1A6", 2674 "SampleAfterValue": "100000", 2675 "BriefDescription": "All offcore prefetch data reads", 2676 "Offcore": "1" 2677 }, 2678 { 2679 "EventCode": "0xB7", 2680 "MSRValue": "0x8010", 2681 "Counter": "2", 2682 "UMask": "0x1", 2683 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", 2684 "MSRIndex": "0x1A6", 2685 "SampleAfterValue": "100000", 2686 "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", 2687 "Offcore": "1" 2688 }, 2689 { 2690 "EventCode": "0xB7", 2691 "MSRValue": "0x110", 2692 "Counter": "2", 2693 "UMask": "0x1", 2694 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", 2695 "MSRIndex": "0x1A6", 2696 "SampleAfterValue": "100000", 2697 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", 2698 "Offcore": "1" 2699 }, 2700 { 2701 "EventCode": "0xB7", 2702 "MSRValue": "0x210", 2703 "Counter": "2", 2704 "UMask": "0x1", 2705 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 2706 "MSRIndex": "0x1A6", 2707 "SampleAfterValue": "100000", 2708 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", 2709 "Offcore": "1" 2710 }, 2711 { 2712 "EventCode": "0xB7", 2713 "MSRValue": "0x410", 2714 "Counter": "2", 2715 "UMask": "0x1", 2716 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 2717 "MSRIndex": "0x1A6", 2718 "SampleAfterValue": "100000", 2719 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", 2720 "Offcore": "1" 2721 }, 2722 { 2723 "EventCode": "0xB7", 2724 "MSRValue": "0x710", 2725 "Counter": "2", 2726 "UMask": "0x1", 2727 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", 2728 "MSRIndex": "0x1A6", 2729 "SampleAfterValue": "100000", 2730 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", 2731 "Offcore": "1" 2732 }, 2733 { 2734 "EventCode": "0xB7", 2735 "MSRValue": "0x4710", 2736 "Counter": "2", 2737 "UMask": "0x1", 2738 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", 2739 "MSRIndex": "0x1A6", 2740 "SampleAfterValue": "100000", 2741 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", 2742 "Offcore": "1" 2743 }, 2744 { 2745 "EventCode": "0xB7", 2746 "MSRValue": "0x1810", 2747 "Counter": "2", 2748 "UMask": "0x1", 2749 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", 2750 "MSRIndex": "0x1A6", 2751 "SampleAfterValue": "100000", 2752 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", 2753 "Offcore": "1" 2754 }, 2755 { 2756 "EventCode": "0xB7", 2757 "MSRValue": "0x3810", 2758 "Counter": "2", 2759 "UMask": "0x1", 2760 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", 2761 "MSRIndex": "0x1A6", 2762 "SampleAfterValue": "100000", 2763 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", 2764 "Offcore": "1" 2765 }, 2766 { 2767 "EventCode": "0xB7", 2768 "MSRValue": "0x1010", 2769 "Counter": "2", 2770 "UMask": "0x1", 2771 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", 2772 "MSRIndex": "0x1A6", 2773 "SampleAfterValue": "100000", 2774 "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", 2775 "Offcore": "1" 2776 }, 2777 { 2778 "EventCode": "0xB7", 2779 "MSRValue": "0x810", 2780 "Counter": "2", 2781 "UMask": "0x1", 2782 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", 2783 "MSRIndex": "0x1A6", 2784 "SampleAfterValue": "100000", 2785 "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", 2786 "Offcore": "1" 2787 }, 2788 { 2789 "EventCode": "0xB7", 2790 "MSRValue": "0x7F40", 2791 "Counter": "2", 2792 "UMask": "0x1", 2793 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", 2794 "MSRIndex": "0x1A6", 2795 "SampleAfterValue": "100000", 2796 "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", 2797 "Offcore": "1" 2798 }, 2799 { 2800 "EventCode": "0xB7", 2801 "MSRValue": "0xFF40", 2802 "Counter": "2", 2803 "UMask": "0x1", 2804 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", 2805 "MSRIndex": "0x1A6", 2806 "SampleAfterValue": "100000", 2807 "BriefDescription": "All offcore prefetch code reads", 2808 "Offcore": "1" 2809 }, 2810 { 2811 "EventCode": "0xB7", 2812 "MSRValue": "0x8040", 2813 "Counter": "2", 2814 "UMask": "0x1", 2815 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", 2816 "MSRIndex": "0x1A6", 2817 "SampleAfterValue": "100000", 2818 "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", 2819 "Offcore": "1" 2820 }, 2821 { 2822 "EventCode": "0xB7", 2823 "MSRValue": "0x140", 2824 "Counter": "2", 2825 "UMask": "0x1", 2826 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", 2827 "MSRIndex": "0x1A6", 2828 "SampleAfterValue": "100000", 2829 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", 2830 "Offcore": "1" 2831 }, 2832 { 2833 "EventCode": "0xB7", 2834 "MSRValue": "0x240", 2835 "Counter": "2", 2836 "UMask": "0x1", 2837 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2838 "MSRIndex": "0x1A6", 2839 "SampleAfterValue": "100000", 2840 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", 2841 "Offcore": "1" 2842 }, 2843 { 2844 "EventCode": "0xB7", 2845 "MSRValue": "0x440", 2846 "Counter": "2", 2847 "UMask": "0x1", 2848 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2849 "MSRIndex": "0x1A6", 2850 "SampleAfterValue": "100000", 2851 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", 2852 "Offcore": "1" 2853 }, 2854 { 2855 "EventCode": "0xB7", 2856 "MSRValue": "0x740", 2857 "Counter": "2", 2858 "UMask": "0x1", 2859 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", 2860 "MSRIndex": "0x1A6", 2861 "SampleAfterValue": "100000", 2862 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", 2863 "Offcore": "1" 2864 }, 2865 { 2866 "EventCode": "0xB7", 2867 "MSRValue": "0x4740", 2868 "Counter": "2", 2869 "UMask": "0x1", 2870 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", 2871 "MSRIndex": "0x1A6", 2872 "SampleAfterValue": "100000", 2873 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", 2874 "Offcore": "1" 2875 }, 2876 { 2877 "EventCode": "0xB7", 2878 "MSRValue": "0x1840", 2879 "Counter": "2", 2880 "UMask": "0x1", 2881 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", 2882 "MSRIndex": "0x1A6", 2883 "SampleAfterValue": "100000", 2884 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", 2885 "Offcore": "1" 2886 }, 2887 { 2888 "EventCode": "0xB7", 2889 "MSRValue": "0x3840", 2890 "Counter": "2", 2891 "UMask": "0x1", 2892 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", 2893 "MSRIndex": "0x1A6", 2894 "SampleAfterValue": "100000", 2895 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", 2896 "Offcore": "1" 2897 }, 2898 { 2899 "EventCode": "0xB7", 2900 "MSRValue": "0x1040", 2901 "Counter": "2", 2902 "UMask": "0x1", 2903 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", 2904 "MSRIndex": "0x1A6", 2905 "SampleAfterValue": "100000", 2906 "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", 2907 "Offcore": "1" 2908 }, 2909 { 2910 "EventCode": "0xB7", 2911 "MSRValue": "0x840", 2912 "Counter": "2", 2913 "UMask": "0x1", 2914 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", 2915 "MSRIndex": "0x1A6", 2916 "SampleAfterValue": "100000", 2917 "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", 2918 "Offcore": "1" 2919 }, 2920 { 2921 "EventCode": "0xB7", 2922 "MSRValue": "0x7F20", 2923 "Counter": "2", 2924 "UMask": "0x1", 2925 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", 2926 "MSRIndex": "0x1A6", 2927 "SampleAfterValue": "100000", 2928 "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", 2929 "Offcore": "1" 2930 }, 2931 { 2932 "EventCode": "0xB7", 2933 "MSRValue": "0xFF20", 2934 "Counter": "2", 2935 "UMask": "0x1", 2936 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", 2937 "MSRIndex": "0x1A6", 2938 "SampleAfterValue": "100000", 2939 "BriefDescription": "All offcore prefetch RFO requests", 2940 "Offcore": "1" 2941 }, 2942 { 2943 "EventCode": "0xB7", 2944 "MSRValue": "0x8020", 2945 "Counter": "2", 2946 "UMask": "0x1", 2947 "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", 2948 "MSRIndex": "0x1A6", 2949 "SampleAfterValue": "100000", 2950 "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", 2951 "Offcore": "1" 2952 }, 2953 { 2954 "EventCode": "0xB7", 2955 "MSRValue": "0x120", 2956 "Counter": "2", 2957 "UMask": "0x1", 2958 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", 2959 "MSRIndex": "0x1A6", 2960 "SampleAfterValue": "100000", 2961 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", 2962 "Offcore": "1" 2963 }, 2964 { 2965 "EventCode": "0xB7", 2966 "MSRValue": "0x220", 2967 "Counter": "2", 2968 "UMask": "0x1", 2969 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", 2970 "MSRIndex": "0x1A6", 2971 "SampleAfterValue": "100000", 2972 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", 2973 "Offcore": "1" 2974 }, 2975 { 2976 "EventCode": "0xB7", 2977 "MSRValue": "0x420", 2978 "Counter": "2", 2979 "UMask": "0x1", 2980 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", 2981 "MSRIndex": "0x1A6", 2982 "SampleAfterValue": "100000", 2983 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", 2984 "Offcore": "1" 2985 }, 2986 { 2987 "EventCode": "0xB7", 2988 "MSRValue": "0x720", 2989 "Counter": "2", 2990 "UMask": "0x1", 2991 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", 2992 "MSRIndex": "0x1A6", 2993 "SampleAfterValue": "100000", 2994 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", 2995 "Offcore": "1" 2996 }, 2997 { 2998 "EventCode": "0xB7", 2999 "MSRValue": "0x4720", 3000 "Counter": "2", 3001 "UMask": "0x1", 3002 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", 3003 "MSRIndex": "0x1A6", 3004 "SampleAfterValue": "100000", 3005 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", 3006 "Offcore": "1" 3007 }, 3008 { 3009 "EventCode": "0xB7", 3010 "MSRValue": "0x1820", 3011 "Counter": "2", 3012 "UMask": "0x1", 3013 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", 3014 "MSRIndex": "0x1A6", 3015 "SampleAfterValue": "100000", 3016 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", 3017 "Offcore": "1" 3018 }, 3019 { 3020 "EventCode": "0xB7", 3021 "MSRValue": "0x3820", 3022 "Counter": "2", 3023 "UMask": "0x1", 3024 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", 3025 "MSRIndex": "0x1A6", 3026 "SampleAfterValue": "100000", 3027 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", 3028 "Offcore": "1" 3029 }, 3030 { 3031 "EventCode": "0xB7", 3032 "MSRValue": "0x1020", 3033 "Counter": "2", 3034 "UMask": "0x1", 3035 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", 3036 "MSRIndex": "0x1A6", 3037 "SampleAfterValue": "100000", 3038 "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", 3039 "Offcore": "1" 3040 }, 3041 { 3042 "EventCode": "0xB7", 3043 "MSRValue": "0x820", 3044 "Counter": "2", 3045 "UMask": "0x1", 3046 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", 3047 "MSRIndex": "0x1A6", 3048 "SampleAfterValue": "100000", 3049 "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", 3050 "Offcore": "1" 3051 }, 3052 { 3053 "EventCode": "0xB7", 3054 "MSRValue": "0x7F70", 3055 "Counter": "2", 3056 "UMask": "0x1", 3057 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", 3058 "MSRIndex": "0x1A6", 3059 "SampleAfterValue": "100000", 3060 "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", 3061 "Offcore": "1" 3062 }, 3063 { 3064 "EventCode": "0xB7", 3065 "MSRValue": "0xFF70", 3066 "Counter": "2", 3067 "UMask": "0x1", 3068 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", 3069 "MSRIndex": "0x1A6", 3070 "SampleAfterValue": "100000", 3071 "BriefDescription": "All offcore prefetch requests", 3072 "Offcore": "1" 3073 }, 3074 { 3075 "EventCode": "0xB7", 3076 "MSRValue": "0x8070", 3077 "Counter": "2", 3078 "UMask": "0x1", 3079 "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", 3080 "MSRIndex": "0x1A6", 3081 "SampleAfterValue": "100000", 3082 "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", 3083 "Offcore": "1" 3084 }, 3085 { 3086 "EventCode": "0xB7", 3087 "MSRValue": "0x170", 3088 "Counter": "2", 3089 "UMask": "0x1", 3090 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", 3091 "MSRIndex": "0x1A6", 3092 "SampleAfterValue": "100000", 3093 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", 3094 "Offcore": "1" 3095 }, 3096 { 3097 "EventCode": "0xB7", 3098 "MSRValue": "0x270", 3099 "Counter": "2", 3100 "UMask": "0x1", 3101 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", 3102 "MSRIndex": "0x1A6", 3103 "SampleAfterValue": "100000", 3104 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", 3105 "Offcore": "1" 3106 }, 3107 { 3108 "EventCode": "0xB7", 3109 "MSRValue": "0x470", 3110 "Counter": "2", 3111 "UMask": "0x1", 3112 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", 3113 "MSRIndex": "0x1A6", 3114 "SampleAfterValue": "100000", 3115 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", 3116 "Offcore": "1" 3117 }, 3118 { 3119 "EventCode": "0xB7", 3120 "MSRValue": "0x770", 3121 "Counter": "2", 3122 "UMask": "0x1", 3123 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", 3124 "MSRIndex": "0x1A6", 3125 "SampleAfterValue": "100000", 3126 "BriefDescription": "Offcore prefetch requests satisfied by the LLC", 3127 "Offcore": "1" 3128 }, 3129 { 3130 "EventCode": "0xB7", 3131 "MSRValue": "0x4770", 3132 "Counter": "2", 3133 "UMask": "0x1", 3134 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", 3135 "MSRIndex": "0x1A6", 3136 "SampleAfterValue": "100000", 3137 "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", 3138 "Offcore": "1" 3139 }, 3140 { 3141 "EventCode": "0xB7", 3142 "MSRValue": "0x1870", 3143 "Counter": "2", 3144 "UMask": "0x1", 3145 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", 3146 "MSRIndex": "0x1A6", 3147 "SampleAfterValue": "100000", 3148 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", 3149 "Offcore": "1" 3150 }, 3151 { 3152 "EventCode": "0xB7", 3153 "MSRValue": "0x3870", 3154 "Counter": "2", 3155 "UMask": "0x1", 3156 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", 3157 "MSRIndex": "0x1A6", 3158 "SampleAfterValue": "100000", 3159 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", 3160 "Offcore": "1" 3161 }, 3162 { 3163 "EventCode": "0xB7", 3164 "MSRValue": "0x1070", 3165 "Counter": "2", 3166 "UMask": "0x1", 3167 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", 3168 "MSRIndex": "0x1A6", 3169 "SampleAfterValue": "100000", 3170 "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", 3171 "Offcore": "1" 3172 }, 3173 { 3174 "EventCode": "0xB7", 3175 "MSRValue": "0x870", 3176 "Counter": "2", 3177 "UMask": "0x1", 3178 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", 3179 "MSRIndex": "0x1A6", 3180 "SampleAfterValue": "100000", 3181 "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", 3182 "Offcore": "1" 3183 } 3184]