1[ 2 { 3 "BriefDescription": "Cycles L1D locked", 4 "EventCode": "0x63", 5 "EventName": "CACHE_LOCK_CYCLES.L1D", 6 "SampleAfterValue": "2000000", 7 "UMask": "0x2" 8 }, 9 { 10 "BriefDescription": "Cycles L1D and L2 locked", 11 "EventCode": "0x63", 12 "EventName": "CACHE_LOCK_CYCLES.L1D_L2", 13 "SampleAfterValue": "2000000", 14 "UMask": "0x1" 15 }, 16 { 17 "BriefDescription": "L1D cache lines replaced in M state", 18 "EventCode": "0x51", 19 "EventName": "L1D.M_EVICT", 20 "SampleAfterValue": "2000000", 21 "UMask": "0x4" 22 }, 23 { 24 "BriefDescription": "L1D cache lines allocated in the M state", 25 "EventCode": "0x51", 26 "EventName": "L1D.M_REPL", 27 "SampleAfterValue": "2000000", 28 "UMask": "0x2" 29 }, 30 { 31 "BriefDescription": "L1D snoop eviction of cache lines in M state", 32 "EventCode": "0x51", 33 "EventName": "L1D.M_SNOOP_EVICT", 34 "SampleAfterValue": "2000000", 35 "UMask": "0x8" 36 }, 37 { 38 "BriefDescription": "L1 data cache lines allocated", 39 "EventCode": "0x51", 40 "EventName": "L1D.REPL", 41 "SampleAfterValue": "2000000", 42 "UMask": "0x1" 43 }, 44 { 45 "BriefDescription": "All references to the L1 data cache", 46 "EventCode": "0x43", 47 "EventName": "L1D_ALL_REF.ANY", 48 "SampleAfterValue": "2000000", 49 "UMask": "0x1" 50 }, 51 { 52 "BriefDescription": "L1 data cacheable reads and writes", 53 "EventCode": "0x43", 54 "EventName": "L1D_ALL_REF.CACHEABLE", 55 "SampleAfterValue": "2000000", 56 "UMask": "0x2" 57 }, 58 { 59 "BriefDescription": "L1 data cache read in E state", 60 "EventCode": "0x40", 61 "EventName": "L1D_CACHE_LD.E_STATE", 62 "SampleAfterValue": "2000000", 63 "UMask": "0x4" 64 }, 65 { 66 "BriefDescription": "L1 data cache read in I state (misses)", 67 "EventCode": "0x40", 68 "EventName": "L1D_CACHE_LD.I_STATE", 69 "SampleAfterValue": "2000000", 70 "UMask": "0x1" 71 }, 72 { 73 "BriefDescription": "L1 data cache reads", 74 "EventCode": "0x40", 75 "EventName": "L1D_CACHE_LD.MESI", 76 "SampleAfterValue": "2000000", 77 "UMask": "0xf" 78 }, 79 { 80 "BriefDescription": "L1 data cache read in M state", 81 "EventCode": "0x40", 82 "EventName": "L1D_CACHE_LD.M_STATE", 83 "SampleAfterValue": "2000000", 84 "UMask": "0x8" 85 }, 86 { 87 "BriefDescription": "L1 data cache read in S state", 88 "EventCode": "0x40", 89 "EventName": "L1D_CACHE_LD.S_STATE", 90 "SampleAfterValue": "2000000", 91 "UMask": "0x2" 92 }, 93 { 94 "BriefDescription": "L1 data cache load locks in E state", 95 "EventCode": "0x42", 96 "EventName": "L1D_CACHE_LOCK.E_STATE", 97 "SampleAfterValue": "2000000", 98 "UMask": "0x4" 99 }, 100 { 101 "BriefDescription": "L1 data cache load lock hits", 102 "EventCode": "0x42", 103 "EventName": "L1D_CACHE_LOCK.HIT", 104 "SampleAfterValue": "2000000", 105 "UMask": "0x1" 106 }, 107 { 108 "BriefDescription": "L1 data cache load locks in M state", 109 "EventCode": "0x42", 110 "EventName": "L1D_CACHE_LOCK.M_STATE", 111 "SampleAfterValue": "2000000", 112 "UMask": "0x8" 113 }, 114 { 115 "BriefDescription": "L1 data cache load locks in S state", 116 "EventCode": "0x42", 117 "EventName": "L1D_CACHE_LOCK.S_STATE", 118 "SampleAfterValue": "2000000", 119 "UMask": "0x2" 120 }, 121 { 122 "BriefDescription": "L1D load lock accepted in fill buffer", 123 "EventCode": "0x53", 124 "EventName": "L1D_CACHE_LOCK_FB_HIT", 125 "SampleAfterValue": "2000000", 126 "UMask": "0x1" 127 }, 128 { 129 "BriefDescription": "L1D prefetch load lock accepted in fill buffer", 130 "EventCode": "0x52", 131 "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", 132 "SampleAfterValue": "2000000", 133 "UMask": "0x1" 134 }, 135 { 136 "BriefDescription": "L1 data cache stores in E state", 137 "EventCode": "0x41", 138 "EventName": "L1D_CACHE_ST.E_STATE", 139 "SampleAfterValue": "2000000", 140 "UMask": "0x4" 141 }, 142 { 143 "BriefDescription": "L1 data cache stores in M state", 144 "EventCode": "0x41", 145 "EventName": "L1D_CACHE_ST.M_STATE", 146 "SampleAfterValue": "2000000", 147 "UMask": "0x8" 148 }, 149 { 150 "BriefDescription": "L1 data cache stores in S state", 151 "EventCode": "0x41", 152 "EventName": "L1D_CACHE_ST.S_STATE", 153 "SampleAfterValue": "2000000", 154 "UMask": "0x2" 155 }, 156 { 157 "BriefDescription": "L1D hardware prefetch misses", 158 "EventCode": "0x4E", 159 "EventName": "L1D_PREFETCH.MISS", 160 "SampleAfterValue": "200000", 161 "UMask": "0x2" 162 }, 163 { 164 "BriefDescription": "L1D hardware prefetch requests", 165 "EventCode": "0x4E", 166 "EventName": "L1D_PREFETCH.REQUESTS", 167 "SampleAfterValue": "200000", 168 "UMask": "0x1" 169 }, 170 { 171 "BriefDescription": "L1D hardware prefetch requests triggered", 172 "EventCode": "0x4E", 173 "EventName": "L1D_PREFETCH.TRIGGERS", 174 "SampleAfterValue": "200000", 175 "UMask": "0x4" 176 }, 177 { 178 "BriefDescription": "L1 writebacks to L2 in E state", 179 "EventCode": "0x28", 180 "EventName": "L1D_WB_L2.E_STATE", 181 "SampleAfterValue": "100000", 182 "UMask": "0x4" 183 }, 184 { 185 "BriefDescription": "L1 writebacks to L2 in I state (misses)", 186 "EventCode": "0x28", 187 "EventName": "L1D_WB_L2.I_STATE", 188 "SampleAfterValue": "100000", 189 "UMask": "0x1" 190 }, 191 { 192 "BriefDescription": "All L1 writebacks to L2", 193 "EventCode": "0x28", 194 "EventName": "L1D_WB_L2.MESI", 195 "SampleAfterValue": "100000", 196 "UMask": "0xf" 197 }, 198 { 199 "BriefDescription": "L1 writebacks to L2 in M state", 200 "EventCode": "0x28", 201 "EventName": "L1D_WB_L2.M_STATE", 202 "SampleAfterValue": "100000", 203 "UMask": "0x8" 204 }, 205 { 206 "BriefDescription": "L1 writebacks to L2 in S state", 207 "EventCode": "0x28", 208 "EventName": "L1D_WB_L2.S_STATE", 209 "SampleAfterValue": "100000", 210 "UMask": "0x2" 211 }, 212 { 213 "BriefDescription": "All L2 data requests", 214 "EventCode": "0x26", 215 "EventName": "L2_DATA_RQSTS.ANY", 216 "SampleAfterValue": "200000", 217 "UMask": "0xff" 218 }, 219 { 220 "BriefDescription": "L2 data demand loads in E state", 221 "EventCode": "0x26", 222 "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", 223 "SampleAfterValue": "200000", 224 "UMask": "0x4" 225 }, 226 { 227 "BriefDescription": "L2 data demand loads in I state (misses)", 228 "EventCode": "0x26", 229 "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", 230 "SampleAfterValue": "200000", 231 "UMask": "0x1" 232 }, 233 { 234 "BriefDescription": "L2 data demand requests", 235 "EventCode": "0x26", 236 "EventName": "L2_DATA_RQSTS.DEMAND.MESI", 237 "SampleAfterValue": "200000", 238 "UMask": "0xf" 239 }, 240 { 241 "BriefDescription": "L2 data demand loads in M state", 242 "EventCode": "0x26", 243 "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", 244 "SampleAfterValue": "200000", 245 "UMask": "0x8" 246 }, 247 { 248 "BriefDescription": "L2 data demand loads in S state", 249 "EventCode": "0x26", 250 "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", 251 "SampleAfterValue": "200000", 252 "UMask": "0x2" 253 }, 254 { 255 "BriefDescription": "L2 data prefetches in E state", 256 "EventCode": "0x26", 257 "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", 258 "SampleAfterValue": "200000", 259 "UMask": "0x40" 260 }, 261 { 262 "BriefDescription": "L2 data prefetches in the I state (misses)", 263 "EventCode": "0x26", 264 "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", 265 "SampleAfterValue": "200000", 266 "UMask": "0x10" 267 }, 268 { 269 "BriefDescription": "All L2 data prefetches", 270 "EventCode": "0x26", 271 "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", 272 "SampleAfterValue": "200000", 273 "UMask": "0xf0" 274 }, 275 { 276 "BriefDescription": "L2 data prefetches in M state", 277 "EventCode": "0x26", 278 "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", 279 "SampleAfterValue": "200000", 280 "UMask": "0x80" 281 }, 282 { 283 "BriefDescription": "L2 data prefetches in the S state", 284 "EventCode": "0x26", 285 "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", 286 "SampleAfterValue": "200000", 287 "UMask": "0x20" 288 }, 289 { 290 "BriefDescription": "L2 lines alloacated", 291 "EventCode": "0xF1", 292 "EventName": "L2_LINES_IN.ANY", 293 "SampleAfterValue": "100000", 294 "UMask": "0x7" 295 }, 296 { 297 "BriefDescription": "L2 lines allocated in the E state", 298 "EventCode": "0xF1", 299 "EventName": "L2_LINES_IN.E_STATE", 300 "SampleAfterValue": "100000", 301 "UMask": "0x4" 302 }, 303 { 304 "BriefDescription": "L2 lines allocated in the S state", 305 "EventCode": "0xF1", 306 "EventName": "L2_LINES_IN.S_STATE", 307 "SampleAfterValue": "100000", 308 "UMask": "0x2" 309 }, 310 { 311 "BriefDescription": "L2 lines evicted", 312 "EventCode": "0xF2", 313 "EventName": "L2_LINES_OUT.ANY", 314 "SampleAfterValue": "100000", 315 "UMask": "0xf" 316 }, 317 { 318 "BriefDescription": "L2 lines evicted by a demand request", 319 "EventCode": "0xF2", 320 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 321 "SampleAfterValue": "100000", 322 "UMask": "0x1" 323 }, 324 { 325 "BriefDescription": "L2 modified lines evicted by a demand request", 326 "EventCode": "0xF2", 327 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 328 "SampleAfterValue": "100000", 329 "UMask": "0x2" 330 }, 331 { 332 "BriefDescription": "L2 lines evicted by a prefetch request", 333 "EventCode": "0xF2", 334 "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", 335 "SampleAfterValue": "100000", 336 "UMask": "0x4" 337 }, 338 { 339 "BriefDescription": "L2 modified lines evicted by a prefetch request", 340 "EventCode": "0xF2", 341 "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", 342 "SampleAfterValue": "100000", 343 "UMask": "0x8" 344 }, 345 { 346 "BriefDescription": "L2 instruction fetches", 347 "EventCode": "0x24", 348 "EventName": "L2_RQSTS.IFETCHES", 349 "SampleAfterValue": "200000", 350 "UMask": "0x30" 351 }, 352 { 353 "BriefDescription": "L2 instruction fetch hits", 354 "EventCode": "0x24", 355 "EventName": "L2_RQSTS.IFETCH_HIT", 356 "SampleAfterValue": "200000", 357 "UMask": "0x10" 358 }, 359 { 360 "BriefDescription": "L2 instruction fetch misses", 361 "EventCode": "0x24", 362 "EventName": "L2_RQSTS.IFETCH_MISS", 363 "SampleAfterValue": "200000", 364 "UMask": "0x20" 365 }, 366 { 367 "BriefDescription": "L2 load hits", 368 "EventCode": "0x24", 369 "EventName": "L2_RQSTS.LD_HIT", 370 "SampleAfterValue": "200000", 371 "UMask": "0x1" 372 }, 373 { 374 "BriefDescription": "L2 load misses", 375 "EventCode": "0x24", 376 "EventName": "L2_RQSTS.LD_MISS", 377 "SampleAfterValue": "200000", 378 "UMask": "0x2" 379 }, 380 { 381 "BriefDescription": "L2 requests", 382 "EventCode": "0x24", 383 "EventName": "L2_RQSTS.LOADS", 384 "SampleAfterValue": "200000", 385 "UMask": "0x3" 386 }, 387 { 388 "BriefDescription": "All L2 misses", 389 "EventCode": "0x24", 390 "EventName": "L2_RQSTS.MISS", 391 "SampleAfterValue": "200000", 392 "UMask": "0xaa" 393 }, 394 { 395 "BriefDescription": "All L2 prefetches", 396 "EventCode": "0x24", 397 "EventName": "L2_RQSTS.PREFETCHES", 398 "SampleAfterValue": "200000", 399 "UMask": "0xc0" 400 }, 401 { 402 "BriefDescription": "L2 prefetch hits", 403 "EventCode": "0x24", 404 "EventName": "L2_RQSTS.PREFETCH_HIT", 405 "SampleAfterValue": "200000", 406 "UMask": "0x40" 407 }, 408 { 409 "BriefDescription": "L2 prefetch misses", 410 "EventCode": "0x24", 411 "EventName": "L2_RQSTS.PREFETCH_MISS", 412 "SampleAfterValue": "200000", 413 "UMask": "0x80" 414 }, 415 { 416 "BriefDescription": "All L2 requests", 417 "EventCode": "0x24", 418 "EventName": "L2_RQSTS.REFERENCES", 419 "SampleAfterValue": "200000", 420 "UMask": "0xff" 421 }, 422 { 423 "BriefDescription": "L2 RFO requests", 424 "EventCode": "0x24", 425 "EventName": "L2_RQSTS.RFOS", 426 "SampleAfterValue": "200000", 427 "UMask": "0xc" 428 }, 429 { 430 "BriefDescription": "L2 RFO hits", 431 "EventCode": "0x24", 432 "EventName": "L2_RQSTS.RFO_HIT", 433 "SampleAfterValue": "200000", 434 "UMask": "0x4" 435 }, 436 { 437 "BriefDescription": "L2 RFO misses", 438 "EventCode": "0x24", 439 "EventName": "L2_RQSTS.RFO_MISS", 440 "SampleAfterValue": "200000", 441 "UMask": "0x8" 442 }, 443 { 444 "BriefDescription": "All L2 transactions", 445 "EventCode": "0xF0", 446 "EventName": "L2_TRANSACTIONS.ANY", 447 "SampleAfterValue": "200000", 448 "UMask": "0x80" 449 }, 450 { 451 "BriefDescription": "L2 fill transactions", 452 "EventCode": "0xF0", 453 "EventName": "L2_TRANSACTIONS.FILL", 454 "SampleAfterValue": "200000", 455 "UMask": "0x20" 456 }, 457 { 458 "BriefDescription": "L2 instruction fetch transactions", 459 "EventCode": "0xF0", 460 "EventName": "L2_TRANSACTIONS.IFETCH", 461 "SampleAfterValue": "200000", 462 "UMask": "0x4" 463 }, 464 { 465 "BriefDescription": "L1D writeback to L2 transactions", 466 "EventCode": "0xF0", 467 "EventName": "L2_TRANSACTIONS.L1D_WB", 468 "SampleAfterValue": "200000", 469 "UMask": "0x10" 470 }, 471 { 472 "BriefDescription": "L2 Load transactions", 473 "EventCode": "0xF0", 474 "EventName": "L2_TRANSACTIONS.LOAD", 475 "SampleAfterValue": "200000", 476 "UMask": "0x1" 477 }, 478 { 479 "BriefDescription": "L2 prefetch transactions", 480 "EventCode": "0xF0", 481 "EventName": "L2_TRANSACTIONS.PREFETCH", 482 "SampleAfterValue": "200000", 483 "UMask": "0x8" 484 }, 485 { 486 "BriefDescription": "L2 RFO transactions", 487 "EventCode": "0xF0", 488 "EventName": "L2_TRANSACTIONS.RFO", 489 "SampleAfterValue": "200000", 490 "UMask": "0x2" 491 }, 492 { 493 "BriefDescription": "L2 writeback to LLC transactions", 494 "EventCode": "0xF0", 495 "EventName": "L2_TRANSACTIONS.WB", 496 "SampleAfterValue": "200000", 497 "UMask": "0x40" 498 }, 499 { 500 "BriefDescription": "L2 demand lock RFOs in E state", 501 "EventCode": "0x27", 502 "EventName": "L2_WRITE.LOCK.E_STATE", 503 "SampleAfterValue": "100000", 504 "UMask": "0x40" 505 }, 506 { 507 "BriefDescription": "All demand L2 lock RFOs that hit the cache", 508 "EventCode": "0x27", 509 "EventName": "L2_WRITE.LOCK.HIT", 510 "SampleAfterValue": "100000", 511 "UMask": "0xe0" 512 }, 513 { 514 "BriefDescription": "L2 demand lock RFOs in I state (misses)", 515 "EventCode": "0x27", 516 "EventName": "L2_WRITE.LOCK.I_STATE", 517 "SampleAfterValue": "100000", 518 "UMask": "0x10" 519 }, 520 { 521 "BriefDescription": "All demand L2 lock RFOs", 522 "EventCode": "0x27", 523 "EventName": "L2_WRITE.LOCK.MESI", 524 "SampleAfterValue": "100000", 525 "UMask": "0xf0" 526 }, 527 { 528 "BriefDescription": "L2 demand lock RFOs in M state", 529 "EventCode": "0x27", 530 "EventName": "L2_WRITE.LOCK.M_STATE", 531 "SampleAfterValue": "100000", 532 "UMask": "0x80" 533 }, 534 { 535 "BriefDescription": "L2 demand lock RFOs in S state", 536 "EventCode": "0x27", 537 "EventName": "L2_WRITE.LOCK.S_STATE", 538 "SampleAfterValue": "100000", 539 "UMask": "0x20" 540 }, 541 { 542 "BriefDescription": "All L2 demand store RFOs that hit the cache", 543 "EventCode": "0x27", 544 "EventName": "L2_WRITE.RFO.HIT", 545 "SampleAfterValue": "100000", 546 "UMask": "0xe" 547 }, 548 { 549 "BriefDescription": "L2 demand store RFOs in I state (misses)", 550 "EventCode": "0x27", 551 "EventName": "L2_WRITE.RFO.I_STATE", 552 "SampleAfterValue": "100000", 553 "UMask": "0x1" 554 }, 555 { 556 "BriefDescription": "All L2 demand store RFOs", 557 "EventCode": "0x27", 558 "EventName": "L2_WRITE.RFO.MESI", 559 "SampleAfterValue": "100000", 560 "UMask": "0xf" 561 }, 562 { 563 "BriefDescription": "L2 demand store RFOs in M state", 564 "EventCode": "0x27", 565 "EventName": "L2_WRITE.RFO.M_STATE", 566 "SampleAfterValue": "100000", 567 "UMask": "0x8" 568 }, 569 { 570 "BriefDescription": "L2 demand store RFOs in S state", 571 "EventCode": "0x27", 572 "EventName": "L2_WRITE.RFO.S_STATE", 573 "SampleAfterValue": "100000", 574 "UMask": "0x2" 575 }, 576 { 577 "BriefDescription": "Longest latency cache miss", 578 "EventCode": "0x2E", 579 "EventName": "LONGEST_LAT_CACHE.MISS", 580 "SampleAfterValue": "100000", 581 "UMask": "0x41" 582 }, 583 { 584 "BriefDescription": "Longest latency cache reference", 585 "EventCode": "0x2E", 586 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 587 "SampleAfterValue": "200000", 588 "UMask": "0x4f" 589 }, 590 { 591 "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)", 592 "EventCode": "0xB", 593 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", 594 "MSRIndex": "0x3F6", 595 "PEBS": "2", 596 "SampleAfterValue": "2000000", 597 "UMask": "0x10" 598 }, 599 { 600 "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)", 601 "EventCode": "0xB", 602 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", 603 "MSRIndex": "0x3F6", 604 "MSRValue": "0x400", 605 "PEBS": "2", 606 "SampleAfterValue": "100", 607 "UMask": "0x10" 608 }, 609 { 610 "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)", 611 "EventCode": "0xB", 612 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", 613 "MSRIndex": "0x3F6", 614 "MSRValue": "0x80", 615 "PEBS": "2", 616 "SampleAfterValue": "1000", 617 "UMask": "0x10" 618 }, 619 { 620 "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)", 621 "EventCode": "0xB", 622 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", 623 "MSRIndex": "0x3F6", 624 "MSRValue": "0x10", 625 "PEBS": "2", 626 "SampleAfterValue": "10000", 627 "UMask": "0x10" 628 }, 629 { 630 "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)", 631 "EventCode": "0xB", 632 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", 633 "MSRIndex": "0x3F6", 634 "MSRValue": "0x4000", 635 "PEBS": "2", 636 "SampleAfterValue": "5", 637 "UMask": "0x10" 638 }, 639 { 640 "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)", 641 "EventCode": "0xB", 642 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", 643 "MSRIndex": "0x3F6", 644 "MSRValue": "0x800", 645 "PEBS": "2", 646 "SampleAfterValue": "50", 647 "UMask": "0x10" 648 }, 649 { 650 "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)", 651 "EventCode": "0xB", 652 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", 653 "MSRIndex": "0x3F6", 654 "MSRValue": "0x100", 655 "PEBS": "2", 656 "SampleAfterValue": "500", 657 "UMask": "0x10" 658 }, 659 { 660 "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)", 661 "EventCode": "0xB", 662 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", 663 "MSRIndex": "0x3F6", 664 "MSRValue": "0x20", 665 "PEBS": "2", 666 "SampleAfterValue": "5000", 667 "UMask": "0x10" 668 }, 669 { 670 "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)", 671 "EventCode": "0xB", 672 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", 673 "MSRIndex": "0x3F6", 674 "MSRValue": "0x8000", 675 "PEBS": "2", 676 "SampleAfterValue": "3", 677 "UMask": "0x10" 678 }, 679 { 680 "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)", 681 "EventCode": "0xB", 682 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", 683 "MSRIndex": "0x3F6", 684 "MSRValue": "0x4", 685 "PEBS": "2", 686 "SampleAfterValue": "50000", 687 "UMask": "0x10" 688 }, 689 { 690 "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)", 691 "EventCode": "0xB", 692 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", 693 "MSRIndex": "0x3F6", 694 "MSRValue": "0x1000", 695 "PEBS": "2", 696 "SampleAfterValue": "20", 697 "UMask": "0x10" 698 }, 699 { 700 "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)", 701 "EventCode": "0xB", 702 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", 703 "MSRIndex": "0x3F6", 704 "MSRValue": "0x200", 705 "PEBS": "2", 706 "SampleAfterValue": "200", 707 "UMask": "0x10" 708 }, 709 { 710 "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)", 711 "EventCode": "0xB", 712 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", 713 "MSRIndex": "0x3F6", 714 "MSRValue": "0x40", 715 "PEBS": "2", 716 "SampleAfterValue": "2000", 717 "UMask": "0x10" 718 }, 719 { 720 "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)", 721 "EventCode": "0xB", 722 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", 723 "MSRIndex": "0x3F6", 724 "MSRValue": "0x8", 725 "PEBS": "2", 726 "SampleAfterValue": "20000", 727 "UMask": "0x10" 728 }, 729 { 730 "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)", 731 "EventCode": "0xB", 732 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", 733 "MSRIndex": "0x3F6", 734 "MSRValue": "0x2000", 735 "PEBS": "2", 736 "SampleAfterValue": "10", 737 "UMask": "0x10" 738 }, 739 { 740 "BriefDescription": "Instructions retired which contains a load (Precise Event)", 741 "EventCode": "0xB", 742 "EventName": "MEM_INST_RETIRED.LOADS", 743 "PEBS": "1", 744 "SampleAfterValue": "2000000", 745 "UMask": "0x1" 746 }, 747 { 748 "BriefDescription": "Instructions retired which contains a store (Precise Event)", 749 "EventCode": "0xB", 750 "EventName": "MEM_INST_RETIRED.STORES", 751 "PEBS": "1", 752 "SampleAfterValue": "2000000", 753 "UMask": "0x2" 754 }, 755 { 756 "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", 757 "EventCode": "0xCB", 758 "EventName": "MEM_LOAD_RETIRED.HIT_LFB", 759 "PEBS": "1", 760 "SampleAfterValue": "200000", 761 "UMask": "0x40" 762 }, 763 { 764 "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)", 765 "EventCode": "0xCB", 766 "EventName": "MEM_LOAD_RETIRED.L1D_HIT", 767 "PEBS": "1", 768 "SampleAfterValue": "2000000", 769 "UMask": "0x1" 770 }, 771 { 772 "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)", 773 "EventCode": "0xCB", 774 "EventName": "MEM_LOAD_RETIRED.L2_HIT", 775 "PEBS": "1", 776 "SampleAfterValue": "200000", 777 "UMask": "0x2" 778 }, 779 { 780 "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)", 781 "EventCode": "0xCB", 782 "EventName": "MEM_LOAD_RETIRED.LLC_MISS", 783 "PEBS": "1", 784 "SampleAfterValue": "10000", 785 "UMask": "0x10" 786 }, 787 { 788 "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", 789 "EventCode": "0xCB", 790 "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", 791 "PEBS": "1", 792 "SampleAfterValue": "40000", 793 "UMask": "0x4" 794 }, 795 { 796 "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", 797 "EventCode": "0xCB", 798 "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", 799 "PEBS": "1", 800 "SampleAfterValue": "40000", 801 "UMask": "0x8" 802 }, 803 { 804 "BriefDescription": "Offcore L1 data cache writebacks", 805 "EventCode": "0xB0", 806 "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", 807 "SampleAfterValue": "100000", 808 "UMask": "0x40" 809 }, 810 { 811 "BriefDescription": "Offcore requests blocked due to Super Queue full", 812 "EventCode": "0xB2", 813 "EventName": "OFFCORE_REQUESTS_SQ_FULL", 814 "SampleAfterValue": "100000", 815 "UMask": "0x1" 816 }, 817 { 818 "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", 819 "EventCode": "0xB7", 820 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", 821 "MSRIndex": "0x1A6", 822 "MSRValue": "0x7F11", 823 "SampleAfterValue": "100000", 824 "UMask": "0x1" 825 }, 826 { 827 "BriefDescription": "All offcore data reads", 828 "EventCode": "0xB7", 829 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", 830 "MSRIndex": "0x1A6", 831 "MSRValue": "0xFF11", 832 "SampleAfterValue": "100000", 833 "UMask": "0x1" 834 }, 835 { 836 "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", 837 "EventCode": "0xB7", 838 "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", 839 "MSRIndex": "0x1A6", 840 "MSRValue": "0x8011", 841 "SampleAfterValue": "100000", 842 "UMask": "0x1" 843 }, 844 { 845 "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", 846 "EventCode": "0xB7", 847 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", 848 "MSRIndex": "0x1A6", 849 "MSRValue": "0x111", 850 "SampleAfterValue": "100000", 851 "UMask": "0x1" 852 }, 853 { 854 "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", 855 "EventCode": "0xB7", 856 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", 857 "MSRIndex": "0x1A6", 858 "MSRValue": "0x211", 859 "SampleAfterValue": "100000", 860 "UMask": "0x1" 861 }, 862 { 863 "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", 864 "EventCode": "0xB7", 865 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", 866 "MSRIndex": "0x1A6", 867 "MSRValue": "0x411", 868 "SampleAfterValue": "100000", 869 "UMask": "0x1" 870 }, 871 { 872 "BriefDescription": "Offcore data reads satisfied by the LLC", 873 "EventCode": "0xB7", 874 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", 875 "MSRIndex": "0x1A6", 876 "MSRValue": "0x711", 877 "SampleAfterValue": "100000", 878 "UMask": "0x1" 879 }, 880 { 881 "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", 882 "EventCode": "0xB7", 883 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", 884 "MSRIndex": "0x1A6", 885 "MSRValue": "0x4711", 886 "SampleAfterValue": "100000", 887 "UMask": "0x1" 888 }, 889 { 890 "BriefDescription": "Offcore data reads satisfied by a remote cache", 891 "EventCode": "0xB7", 892 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", 893 "MSRIndex": "0x1A6", 894 "MSRValue": "0x1811", 895 "SampleAfterValue": "100000", 896 "UMask": "0x1" 897 }, 898 { 899 "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", 900 "EventCode": "0xB7", 901 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", 902 "MSRIndex": "0x1A6", 903 "MSRValue": "0x3811", 904 "SampleAfterValue": "100000", 905 "UMask": "0x1" 906 }, 907 { 908 "BriefDescription": "Offcore data reads that HIT in a remote cache", 909 "EventCode": "0xB7", 910 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", 911 "MSRIndex": "0x1A6", 912 "MSRValue": "0x1011", 913 "SampleAfterValue": "100000", 914 "UMask": "0x1" 915 }, 916 { 917 "BriefDescription": "Offcore data reads that HITM in a remote cache", 918 "EventCode": "0xB7", 919 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", 920 "MSRIndex": "0x1A6", 921 "MSRValue": "0x811", 922 "SampleAfterValue": "100000", 923 "UMask": "0x1" 924 }, 925 { 926 "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", 927 "EventCode": "0xB7", 928 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", 929 "MSRIndex": "0x1A6", 930 "MSRValue": "0x7F44", 931 "SampleAfterValue": "100000", 932 "UMask": "0x1" 933 }, 934 { 935 "BriefDescription": "All offcore code reads", 936 "EventCode": "0xB7", 937 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", 938 "MSRIndex": "0x1A6", 939 "MSRValue": "0xFF44", 940 "SampleAfterValue": "100000", 941 "UMask": "0x1" 942 }, 943 { 944 "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", 945 "EventCode": "0xB7", 946 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", 947 "MSRIndex": "0x1A6", 948 "MSRValue": "0x8044", 949 "SampleAfterValue": "100000", 950 "UMask": "0x1" 951 }, 952 { 953 "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", 954 "EventCode": "0xB7", 955 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", 956 "MSRIndex": "0x1A6", 957 "MSRValue": "0x144", 958 "SampleAfterValue": "100000", 959 "UMask": "0x1" 960 }, 961 { 962 "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", 963 "EventCode": "0xB7", 964 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", 965 "MSRIndex": "0x1A6", 966 "MSRValue": "0x244", 967 "SampleAfterValue": "100000", 968 "UMask": "0x1" 969 }, 970 { 971 "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", 972 "EventCode": "0xB7", 973 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", 974 "MSRIndex": "0x1A6", 975 "MSRValue": "0x444", 976 "SampleAfterValue": "100000", 977 "UMask": "0x1" 978 }, 979 { 980 "BriefDescription": "Offcore code reads satisfied by the LLC", 981 "EventCode": "0xB7", 982 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", 983 "MSRIndex": "0x1A6", 984 "MSRValue": "0x744", 985 "SampleAfterValue": "100000", 986 "UMask": "0x1" 987 }, 988 { 989 "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", 990 "EventCode": "0xB7", 991 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", 992 "MSRIndex": "0x1A6", 993 "MSRValue": "0x4744", 994 "SampleAfterValue": "100000", 995 "UMask": "0x1" 996 }, 997 { 998 "BriefDescription": "Offcore code reads satisfied by a remote cache", 999 "EventCode": "0xB7", 1000 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", 1001 "MSRIndex": "0x1A6", 1002 "MSRValue": "0x1844", 1003 "SampleAfterValue": "100000", 1004 "UMask": "0x1" 1005 }, 1006 { 1007 "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", 1008 "EventCode": "0xB7", 1009 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", 1010 "MSRIndex": "0x1A6", 1011 "MSRValue": "0x3844", 1012 "SampleAfterValue": "100000", 1013 "UMask": "0x1" 1014 }, 1015 { 1016 "BriefDescription": "Offcore code reads that HIT in a remote cache", 1017 "EventCode": "0xB7", 1018 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", 1019 "MSRIndex": "0x1A6", 1020 "MSRValue": "0x1044", 1021 "SampleAfterValue": "100000", 1022 "UMask": "0x1" 1023 }, 1024 { 1025 "BriefDescription": "Offcore code reads that HITM in a remote cache", 1026 "EventCode": "0xB7", 1027 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", 1028 "MSRIndex": "0x1A6", 1029 "MSRValue": "0x844", 1030 "SampleAfterValue": "100000", 1031 "UMask": "0x1" 1032 }, 1033 { 1034 "BriefDescription": "Offcore requests satisfied by any cache or DRAM", 1035 "EventCode": "0xB7", 1036 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", 1037 "MSRIndex": "0x1A6", 1038 "MSRValue": "0x7FFF", 1039 "SampleAfterValue": "100000", 1040 "UMask": "0x1" 1041 }, 1042 { 1043 "BriefDescription": "All offcore requests", 1044 "EventCode": "0xB7", 1045 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", 1046 "MSRIndex": "0x1A6", 1047 "MSRValue": "0xFFFF", 1048 "SampleAfterValue": "100000", 1049 "UMask": "0x1" 1050 }, 1051 { 1052 "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", 1053 "EventCode": "0xB7", 1054 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", 1055 "MSRIndex": "0x1A6", 1056 "MSRValue": "0x80FF", 1057 "SampleAfterValue": "100000", 1058 "UMask": "0x1" 1059 }, 1060 { 1061 "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", 1062 "EventCode": "0xB7", 1063 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", 1064 "MSRIndex": "0x1A6", 1065 "MSRValue": "0x1FF", 1066 "SampleAfterValue": "100000", 1067 "UMask": "0x1" 1068 }, 1069 { 1070 "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", 1071 "EventCode": "0xB7", 1072 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", 1073 "MSRIndex": "0x1A6", 1074 "MSRValue": "0x2FF", 1075 "SampleAfterValue": "100000", 1076 "UMask": "0x1" 1077 }, 1078 { 1079 "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", 1080 "EventCode": "0xB7", 1081 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", 1082 "MSRIndex": "0x1A6", 1083 "MSRValue": "0x4FF", 1084 "SampleAfterValue": "100000", 1085 "UMask": "0x1" 1086 }, 1087 { 1088 "BriefDescription": "Offcore requests satisfied by the LLC", 1089 "EventCode": "0xB7", 1090 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", 1091 "MSRIndex": "0x1A6", 1092 "MSRValue": "0x7FF", 1093 "SampleAfterValue": "100000", 1094 "UMask": "0x1" 1095 }, 1096 { 1097 "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", 1098 "EventCode": "0xB7", 1099 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", 1100 "MSRIndex": "0x1A6", 1101 "MSRValue": "0x47FF", 1102 "SampleAfterValue": "100000", 1103 "UMask": "0x1" 1104 }, 1105 { 1106 "BriefDescription": "Offcore requests satisfied by a remote cache", 1107 "EventCode": "0xB7", 1108 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", 1109 "MSRIndex": "0x1A6", 1110 "MSRValue": "0x18FF", 1111 "SampleAfterValue": "100000", 1112 "UMask": "0x1" 1113 }, 1114 { 1115 "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", 1116 "EventCode": "0xB7", 1117 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", 1118 "MSRIndex": "0x1A6", 1119 "MSRValue": "0x38FF", 1120 "SampleAfterValue": "100000", 1121 "UMask": "0x1" 1122 }, 1123 { 1124 "BriefDescription": "Offcore requests that HIT in a remote cache", 1125 "EventCode": "0xB7", 1126 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", 1127 "MSRIndex": "0x1A6", 1128 "MSRValue": "0x10FF", 1129 "SampleAfterValue": "100000", 1130 "UMask": "0x1" 1131 }, 1132 { 1133 "BriefDescription": "Offcore requests that HITM in a remote cache", 1134 "EventCode": "0xB7", 1135 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", 1136 "MSRIndex": "0x1A6", 1137 "MSRValue": "0x8FF", 1138 "SampleAfterValue": "100000", 1139 "UMask": "0x1" 1140 }, 1141 { 1142 "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", 1143 "EventCode": "0xB7", 1144 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", 1145 "MSRIndex": "0x1A6", 1146 "MSRValue": "0x7F22", 1147 "SampleAfterValue": "100000", 1148 "UMask": "0x1" 1149 }, 1150 { 1151 "BriefDescription": "All offcore RFO requests", 1152 "EventCode": "0xB7", 1153 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", 1154 "MSRIndex": "0x1A6", 1155 "MSRValue": "0xFF22", 1156 "SampleAfterValue": "100000", 1157 "UMask": "0x1" 1158 }, 1159 { 1160 "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", 1161 "EventCode": "0xB7", 1162 "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", 1163 "MSRIndex": "0x1A6", 1164 "MSRValue": "0x8022", 1165 "SampleAfterValue": "100000", 1166 "UMask": "0x1" 1167 }, 1168 { 1169 "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", 1170 "EventCode": "0xB7", 1171 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", 1172 "MSRIndex": "0x1A6", 1173 "MSRValue": "0x122", 1174 "SampleAfterValue": "100000", 1175 "UMask": "0x1" 1176 }, 1177 { 1178 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", 1179 "EventCode": "0xB7", 1180 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", 1181 "MSRIndex": "0x1A6", 1182 "MSRValue": "0x222", 1183 "SampleAfterValue": "100000", 1184 "UMask": "0x1" 1185 }, 1186 { 1187 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", 1188 "EventCode": "0xB7", 1189 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", 1190 "MSRIndex": "0x1A6", 1191 "MSRValue": "0x422", 1192 "SampleAfterValue": "100000", 1193 "UMask": "0x1" 1194 }, 1195 { 1196 "BriefDescription": "Offcore RFO requests satisfied by the LLC", 1197 "EventCode": "0xB7", 1198 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", 1199 "MSRIndex": "0x1A6", 1200 "MSRValue": "0x722", 1201 "SampleAfterValue": "100000", 1202 "UMask": "0x1" 1203 }, 1204 { 1205 "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", 1206 "EventCode": "0xB7", 1207 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", 1208 "MSRIndex": "0x1A6", 1209 "MSRValue": "0x4722", 1210 "SampleAfterValue": "100000", 1211 "UMask": "0x1" 1212 }, 1213 { 1214 "BriefDescription": "Offcore RFO requests satisfied by a remote cache", 1215 "EventCode": "0xB7", 1216 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", 1217 "MSRIndex": "0x1A6", 1218 "MSRValue": "0x1822", 1219 "SampleAfterValue": "100000", 1220 "UMask": "0x1" 1221 }, 1222 { 1223 "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", 1224 "EventCode": "0xB7", 1225 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", 1226 "MSRIndex": "0x1A6", 1227 "MSRValue": "0x3822", 1228 "SampleAfterValue": "100000", 1229 "UMask": "0x1" 1230 }, 1231 { 1232 "BriefDescription": "Offcore RFO requests that HIT in a remote cache", 1233 "EventCode": "0xB7", 1234 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", 1235 "MSRIndex": "0x1A6", 1236 "MSRValue": "0x1022", 1237 "SampleAfterValue": "100000", 1238 "UMask": "0x1" 1239 }, 1240 { 1241 "BriefDescription": "Offcore RFO requests that HITM in a remote cache", 1242 "EventCode": "0xB7", 1243 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", 1244 "MSRIndex": "0x1A6", 1245 "MSRValue": "0x822", 1246 "SampleAfterValue": "100000", 1247 "UMask": "0x1" 1248 }, 1249 { 1250 "BriefDescription": "Offcore writebacks to any cache or DRAM.", 1251 "EventCode": "0xB7", 1252 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", 1253 "MSRIndex": "0x1A6", 1254 "MSRValue": "0x7F08", 1255 "SampleAfterValue": "100000", 1256 "UMask": "0x1" 1257 }, 1258 { 1259 "BriefDescription": "All offcore writebacks", 1260 "EventCode": "0xB7", 1261 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", 1262 "MSRIndex": "0x1A6", 1263 "MSRValue": "0xFF08", 1264 "SampleAfterValue": "100000", 1265 "UMask": "0x1" 1266 }, 1267 { 1268 "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", 1269 "EventCode": "0xB7", 1270 "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", 1271 "MSRIndex": "0x1A6", 1272 "MSRValue": "0x8008", 1273 "SampleAfterValue": "100000", 1274 "UMask": "0x1" 1275 }, 1276 { 1277 "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", 1278 "EventCode": "0xB7", 1279 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", 1280 "MSRIndex": "0x1A6", 1281 "MSRValue": "0x108", 1282 "SampleAfterValue": "100000", 1283 "UMask": "0x1" 1284 }, 1285 { 1286 "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", 1287 "EventCode": "0xB7", 1288 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", 1289 "MSRIndex": "0x1A6", 1290 "MSRValue": "0x408", 1291 "SampleAfterValue": "100000", 1292 "UMask": "0x1" 1293 }, 1294 { 1295 "BriefDescription": "Offcore writebacks to the LLC", 1296 "EventCode": "0xB7", 1297 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", 1298 "MSRIndex": "0x1A6", 1299 "MSRValue": "0x708", 1300 "SampleAfterValue": "100000", 1301 "UMask": "0x1" 1302 }, 1303 { 1304 "BriefDescription": "Offcore writebacks to the LLC or local DRAM", 1305 "EventCode": "0xB7", 1306 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", 1307 "MSRIndex": "0x1A6", 1308 "MSRValue": "0x4708", 1309 "SampleAfterValue": "100000", 1310 "UMask": "0x1" 1311 }, 1312 { 1313 "BriefDescription": "Offcore writebacks to a remote cache", 1314 "EventCode": "0xB7", 1315 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", 1316 "MSRIndex": "0x1A6", 1317 "MSRValue": "0x1808", 1318 "SampleAfterValue": "100000", 1319 "UMask": "0x1" 1320 }, 1321 { 1322 "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", 1323 "EventCode": "0xB7", 1324 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", 1325 "MSRIndex": "0x1A6", 1326 "MSRValue": "0x3808", 1327 "SampleAfterValue": "100000", 1328 "UMask": "0x1" 1329 }, 1330 { 1331 "BriefDescription": "Offcore writebacks that HIT in a remote cache", 1332 "EventCode": "0xB7", 1333 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", 1334 "MSRIndex": "0x1A6", 1335 "MSRValue": "0x1008", 1336 "SampleAfterValue": "100000", 1337 "UMask": "0x1" 1338 }, 1339 { 1340 "BriefDescription": "Offcore writebacks that HITM in a remote cache", 1341 "EventCode": "0xB7", 1342 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", 1343 "MSRIndex": "0x1A6", 1344 "MSRValue": "0x808", 1345 "SampleAfterValue": "100000", 1346 "UMask": "0x1" 1347 }, 1348 { 1349 "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", 1350 "EventCode": "0xB7", 1351 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", 1352 "MSRIndex": "0x1A6", 1353 "MSRValue": "0x7F77", 1354 "SampleAfterValue": "100000", 1355 "UMask": "0x1" 1356 }, 1357 { 1358 "BriefDescription": "All offcore code or data read requests", 1359 "EventCode": "0xB7", 1360 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", 1361 "MSRIndex": "0x1A6", 1362 "MSRValue": "0xFF77", 1363 "SampleAfterValue": "100000", 1364 "UMask": "0x1" 1365 }, 1366 { 1367 "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", 1368 "EventCode": "0xB7", 1369 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", 1370 "MSRIndex": "0x1A6", 1371 "MSRValue": "0x8077", 1372 "SampleAfterValue": "100000", 1373 "UMask": "0x1" 1374 }, 1375 { 1376 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", 1377 "EventCode": "0xB7", 1378 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", 1379 "MSRIndex": "0x1A6", 1380 "MSRValue": "0x177", 1381 "SampleAfterValue": "100000", 1382 "UMask": "0x1" 1383 }, 1384 { 1385 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", 1386 "EventCode": "0xB7", 1387 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1388 "MSRIndex": "0x1A6", 1389 "MSRValue": "0x277", 1390 "SampleAfterValue": "100000", 1391 "UMask": "0x1" 1392 }, 1393 { 1394 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", 1395 "EventCode": "0xB7", 1396 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1397 "MSRIndex": "0x1A6", 1398 "MSRValue": "0x477", 1399 "SampleAfterValue": "100000", 1400 "UMask": "0x1" 1401 }, 1402 { 1403 "BriefDescription": "Offcore code or data read requests satisfied by the LLC", 1404 "EventCode": "0xB7", 1405 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", 1406 "MSRIndex": "0x1A6", 1407 "MSRValue": "0x777", 1408 "SampleAfterValue": "100000", 1409 "UMask": "0x1" 1410 }, 1411 { 1412 "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", 1413 "EventCode": "0xB7", 1414 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", 1415 "MSRIndex": "0x1A6", 1416 "MSRValue": "0x4777", 1417 "SampleAfterValue": "100000", 1418 "UMask": "0x1" 1419 }, 1420 { 1421 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", 1422 "EventCode": "0xB7", 1423 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", 1424 "MSRIndex": "0x1A6", 1425 "MSRValue": "0x1877", 1426 "SampleAfterValue": "100000", 1427 "UMask": "0x1" 1428 }, 1429 { 1430 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", 1431 "EventCode": "0xB7", 1432 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", 1433 "MSRIndex": "0x1A6", 1434 "MSRValue": "0x3877", 1435 "SampleAfterValue": "100000", 1436 "UMask": "0x1" 1437 }, 1438 { 1439 "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", 1440 "EventCode": "0xB7", 1441 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", 1442 "MSRIndex": "0x1A6", 1443 "MSRValue": "0x1077", 1444 "SampleAfterValue": "100000", 1445 "UMask": "0x1" 1446 }, 1447 { 1448 "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", 1449 "EventCode": "0xB7", 1450 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", 1451 "MSRIndex": "0x1A6", 1452 "MSRValue": "0x877", 1453 "SampleAfterValue": "100000", 1454 "UMask": "0x1" 1455 }, 1456 { 1457 "BriefDescription": "Offcore request = all data, response = any cache_dram", 1458 "EventCode": "0xB7", 1459 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", 1460 "MSRIndex": "0x1A6", 1461 "MSRValue": "0x7F33", 1462 "SampleAfterValue": "100000", 1463 "UMask": "0x1" 1464 }, 1465 { 1466 "BriefDescription": "Offcore request = all data, response = any location", 1467 "EventCode": "0xB7", 1468 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", 1469 "MSRIndex": "0x1A6", 1470 "MSRValue": "0xFF33", 1471 "SampleAfterValue": "100000", 1472 "UMask": "0x1" 1473 }, 1474 { 1475 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit", 1476 "EventCode": "0xB7", 1477 "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", 1478 "MSRIndex": "0x1A6", 1479 "MSRValue": "0x8033", 1480 "SampleAfterValue": "100000", 1481 "UMask": "0x1" 1482 }, 1483 { 1484 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core", 1485 "EventCode": "0xB7", 1486 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", 1487 "MSRIndex": "0x1A6", 1488 "MSRValue": "0x133", 1489 "SampleAfterValue": "100000", 1490 "UMask": "0x1" 1491 }, 1492 { 1493 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core", 1494 "EventCode": "0xB7", 1495 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", 1496 "MSRIndex": "0x1A6", 1497 "MSRValue": "0x233", 1498 "SampleAfterValue": "100000", 1499 "UMask": "0x1" 1500 }, 1501 { 1502 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core", 1503 "EventCode": "0xB7", 1504 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", 1505 "MSRIndex": "0x1A6", 1506 "MSRValue": "0x433", 1507 "SampleAfterValue": "100000", 1508 "UMask": "0x1" 1509 }, 1510 { 1511 "BriefDescription": "Offcore request = all data, response = local cache", 1512 "EventCode": "0xB7", 1513 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", 1514 "MSRIndex": "0x1A6", 1515 "MSRValue": "0x733", 1516 "SampleAfterValue": "100000", 1517 "UMask": "0x1" 1518 }, 1519 { 1520 "BriefDescription": "Offcore request = all data, response = local cache or dram", 1521 "EventCode": "0xB7", 1522 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", 1523 "MSRIndex": "0x1A6", 1524 "MSRValue": "0x4733", 1525 "SampleAfterValue": "100000", 1526 "UMask": "0x1" 1527 }, 1528 { 1529 "BriefDescription": "Offcore request = all data, response = remote cache", 1530 "EventCode": "0xB7", 1531 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", 1532 "MSRIndex": "0x1A6", 1533 "MSRValue": "0x1833", 1534 "SampleAfterValue": "100000", 1535 "UMask": "0x1" 1536 }, 1537 { 1538 "BriefDescription": "Offcore request = all data, response = remote cache or dram", 1539 "EventCode": "0xB7", 1540 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", 1541 "MSRIndex": "0x1A6", 1542 "MSRValue": "0x3833", 1543 "SampleAfterValue": "100000", 1544 "UMask": "0x1" 1545 }, 1546 { 1547 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache", 1548 "EventCode": "0xB7", 1549 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", 1550 "MSRIndex": "0x1A6", 1551 "MSRValue": "0x1033", 1552 "SampleAfterValue": "100000", 1553 "UMask": "0x1" 1554 }, 1555 { 1556 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache", 1557 "EventCode": "0xB7", 1558 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", 1559 "MSRIndex": "0x1A6", 1560 "MSRValue": "0x833", 1561 "SampleAfterValue": "100000", 1562 "UMask": "0x1" 1563 }, 1564 { 1565 "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", 1566 "EventCode": "0xB7", 1567 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", 1568 "MSRIndex": "0x1A6", 1569 "MSRValue": "0x7F03", 1570 "SampleAfterValue": "100000", 1571 "UMask": "0x1" 1572 }, 1573 { 1574 "BriefDescription": "All offcore demand data requests", 1575 "EventCode": "0xB7", 1576 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", 1577 "MSRIndex": "0x1A6", 1578 "MSRValue": "0xFF03", 1579 "SampleAfterValue": "100000", 1580 "UMask": "0x1" 1581 }, 1582 { 1583 "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", 1584 "EventCode": "0xB7", 1585 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", 1586 "MSRIndex": "0x1A6", 1587 "MSRValue": "0x8003", 1588 "SampleAfterValue": "100000", 1589 "UMask": "0x1" 1590 }, 1591 { 1592 "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", 1593 "EventCode": "0xB7", 1594 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", 1595 "MSRIndex": "0x1A6", 1596 "MSRValue": "0x103", 1597 "SampleAfterValue": "100000", 1598 "UMask": "0x1" 1599 }, 1600 { 1601 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", 1602 "EventCode": "0xB7", 1603 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", 1604 "MSRIndex": "0x1A6", 1605 "MSRValue": "0x203", 1606 "SampleAfterValue": "100000", 1607 "UMask": "0x1" 1608 }, 1609 { 1610 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", 1611 "EventCode": "0xB7", 1612 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", 1613 "MSRIndex": "0x1A6", 1614 "MSRValue": "0x403", 1615 "SampleAfterValue": "100000", 1616 "UMask": "0x1" 1617 }, 1618 { 1619 "BriefDescription": "Offcore demand data requests satisfied by the LLC", 1620 "EventCode": "0xB7", 1621 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", 1622 "MSRIndex": "0x1A6", 1623 "MSRValue": "0x703", 1624 "SampleAfterValue": "100000", 1625 "UMask": "0x1" 1626 }, 1627 { 1628 "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", 1629 "EventCode": "0xB7", 1630 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", 1631 "MSRIndex": "0x1A6", 1632 "MSRValue": "0x4703", 1633 "SampleAfterValue": "100000", 1634 "UMask": "0x1" 1635 }, 1636 { 1637 "BriefDescription": "Offcore demand data requests satisfied by a remote cache", 1638 "EventCode": "0xB7", 1639 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", 1640 "MSRIndex": "0x1A6", 1641 "MSRValue": "0x1803", 1642 "SampleAfterValue": "100000", 1643 "UMask": "0x1" 1644 }, 1645 { 1646 "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", 1647 "EventCode": "0xB7", 1648 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", 1649 "MSRIndex": "0x1A6", 1650 "MSRValue": "0x3803", 1651 "SampleAfterValue": "100000", 1652 "UMask": "0x1" 1653 }, 1654 { 1655 "BriefDescription": "Offcore demand data requests that HIT in a remote cache", 1656 "EventCode": "0xB7", 1657 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", 1658 "MSRIndex": "0x1A6", 1659 "MSRValue": "0x1003", 1660 "SampleAfterValue": "100000", 1661 "UMask": "0x1" 1662 }, 1663 { 1664 "BriefDescription": "Offcore demand data requests that HITM in a remote cache", 1665 "EventCode": "0xB7", 1666 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", 1667 "MSRIndex": "0x1A6", 1668 "MSRValue": "0x803", 1669 "SampleAfterValue": "100000", 1670 "UMask": "0x1" 1671 }, 1672 { 1673 "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", 1674 "EventCode": "0xB7", 1675 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", 1676 "MSRIndex": "0x1A6", 1677 "MSRValue": "0x7F01", 1678 "SampleAfterValue": "100000", 1679 "UMask": "0x1" 1680 }, 1681 { 1682 "BriefDescription": "All offcore demand data reads", 1683 "EventCode": "0xB7", 1684 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", 1685 "MSRIndex": "0x1A6", 1686 "MSRValue": "0xFF01", 1687 "SampleAfterValue": "100000", 1688 "UMask": "0x1" 1689 }, 1690 { 1691 "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", 1692 "EventCode": "0xB7", 1693 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", 1694 "MSRIndex": "0x1A6", 1695 "MSRValue": "0x8001", 1696 "SampleAfterValue": "100000", 1697 "UMask": "0x1" 1698 }, 1699 { 1700 "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", 1701 "EventCode": "0xB7", 1702 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", 1703 "MSRIndex": "0x1A6", 1704 "MSRValue": "0x101", 1705 "SampleAfterValue": "100000", 1706 "UMask": "0x1" 1707 }, 1708 { 1709 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", 1710 "EventCode": "0xB7", 1711 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 1712 "MSRIndex": "0x1A6", 1713 "MSRValue": "0x201", 1714 "SampleAfterValue": "100000", 1715 "UMask": "0x1" 1716 }, 1717 { 1718 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", 1719 "EventCode": "0xB7", 1720 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 1721 "MSRIndex": "0x1A6", 1722 "MSRValue": "0x401", 1723 "SampleAfterValue": "100000", 1724 "UMask": "0x1" 1725 }, 1726 { 1727 "BriefDescription": "Offcore demand data reads satisfied by the LLC", 1728 "EventCode": "0xB7", 1729 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", 1730 "MSRIndex": "0x1A6", 1731 "MSRValue": "0x701", 1732 "SampleAfterValue": "100000", 1733 "UMask": "0x1" 1734 }, 1735 { 1736 "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", 1737 "EventCode": "0xB7", 1738 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", 1739 "MSRIndex": "0x1A6", 1740 "MSRValue": "0x4701", 1741 "SampleAfterValue": "100000", 1742 "UMask": "0x1" 1743 }, 1744 { 1745 "BriefDescription": "Offcore demand data reads satisfied by a remote cache", 1746 "EventCode": "0xB7", 1747 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", 1748 "MSRIndex": "0x1A6", 1749 "MSRValue": "0x1801", 1750 "SampleAfterValue": "100000", 1751 "UMask": "0x1" 1752 }, 1753 { 1754 "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", 1755 "EventCode": "0xB7", 1756 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", 1757 "MSRIndex": "0x1A6", 1758 "MSRValue": "0x3801", 1759 "SampleAfterValue": "100000", 1760 "UMask": "0x1" 1761 }, 1762 { 1763 "BriefDescription": "Offcore demand data reads that HIT in a remote cache", 1764 "EventCode": "0xB7", 1765 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", 1766 "MSRIndex": "0x1A6", 1767 "MSRValue": "0x1001", 1768 "SampleAfterValue": "100000", 1769 "UMask": "0x1" 1770 }, 1771 { 1772 "BriefDescription": "Offcore demand data reads that HITM in a remote cache", 1773 "EventCode": "0xB7", 1774 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", 1775 "MSRIndex": "0x1A6", 1776 "MSRValue": "0x801", 1777 "SampleAfterValue": "100000", 1778 "UMask": "0x1" 1779 }, 1780 { 1781 "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", 1782 "EventCode": "0xB7", 1783 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", 1784 "MSRIndex": "0x1A6", 1785 "MSRValue": "0x7F04", 1786 "SampleAfterValue": "100000", 1787 "UMask": "0x1" 1788 }, 1789 { 1790 "BriefDescription": "All offcore demand code reads", 1791 "EventCode": "0xB7", 1792 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", 1793 "MSRIndex": "0x1A6", 1794 "MSRValue": "0xFF04", 1795 "SampleAfterValue": "100000", 1796 "UMask": "0x1" 1797 }, 1798 { 1799 "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", 1800 "EventCode": "0xB7", 1801 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", 1802 "MSRIndex": "0x1A6", 1803 "MSRValue": "0x8004", 1804 "SampleAfterValue": "100000", 1805 "UMask": "0x1" 1806 }, 1807 { 1808 "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", 1809 "EventCode": "0xB7", 1810 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", 1811 "MSRIndex": "0x1A6", 1812 "MSRValue": "0x104", 1813 "SampleAfterValue": "100000", 1814 "UMask": "0x1" 1815 }, 1816 { 1817 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", 1818 "EventCode": "0xB7", 1819 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1820 "MSRIndex": "0x1A6", 1821 "MSRValue": "0x204", 1822 "SampleAfterValue": "100000", 1823 "UMask": "0x1" 1824 }, 1825 { 1826 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", 1827 "EventCode": "0xB7", 1828 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1829 "MSRIndex": "0x1A6", 1830 "MSRValue": "0x404", 1831 "SampleAfterValue": "100000", 1832 "UMask": "0x1" 1833 }, 1834 { 1835 "BriefDescription": "Offcore demand code reads satisfied by the LLC", 1836 "EventCode": "0xB7", 1837 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", 1838 "MSRIndex": "0x1A6", 1839 "MSRValue": "0x704", 1840 "SampleAfterValue": "100000", 1841 "UMask": "0x1" 1842 }, 1843 { 1844 "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", 1845 "EventCode": "0xB7", 1846 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", 1847 "MSRIndex": "0x1A6", 1848 "MSRValue": "0x4704", 1849 "SampleAfterValue": "100000", 1850 "UMask": "0x1" 1851 }, 1852 { 1853 "BriefDescription": "Offcore demand code reads satisfied by a remote cache", 1854 "EventCode": "0xB7", 1855 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", 1856 "MSRIndex": "0x1A6", 1857 "MSRValue": "0x1804", 1858 "SampleAfterValue": "100000", 1859 "UMask": "0x1" 1860 }, 1861 { 1862 "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", 1863 "EventCode": "0xB7", 1864 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", 1865 "MSRIndex": "0x1A6", 1866 "MSRValue": "0x3804", 1867 "SampleAfterValue": "100000", 1868 "UMask": "0x1" 1869 }, 1870 { 1871 "BriefDescription": "Offcore demand code reads that HIT in a remote cache", 1872 "EventCode": "0xB7", 1873 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", 1874 "MSRIndex": "0x1A6", 1875 "MSRValue": "0x1004", 1876 "SampleAfterValue": "100000", 1877 "UMask": "0x1" 1878 }, 1879 { 1880 "BriefDescription": "Offcore demand code reads that HITM in a remote cache", 1881 "EventCode": "0xB7", 1882 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", 1883 "MSRIndex": "0x1A6", 1884 "MSRValue": "0x804", 1885 "SampleAfterValue": "100000", 1886 "UMask": "0x1" 1887 }, 1888 { 1889 "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", 1890 "EventCode": "0xB7", 1891 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", 1892 "MSRIndex": "0x1A6", 1893 "MSRValue": "0x7F02", 1894 "SampleAfterValue": "100000", 1895 "UMask": "0x1" 1896 }, 1897 { 1898 "BriefDescription": "All offcore demand RFO requests", 1899 "EventCode": "0xB7", 1900 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", 1901 "MSRIndex": "0x1A6", 1902 "MSRValue": "0xFF02", 1903 "SampleAfterValue": "100000", 1904 "UMask": "0x1" 1905 }, 1906 { 1907 "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", 1908 "EventCode": "0xB7", 1909 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", 1910 "MSRIndex": "0x1A6", 1911 "MSRValue": "0x8002", 1912 "SampleAfterValue": "100000", 1913 "UMask": "0x1" 1914 }, 1915 { 1916 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", 1917 "EventCode": "0xB7", 1918 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", 1919 "MSRIndex": "0x1A6", 1920 "MSRValue": "0x102", 1921 "SampleAfterValue": "100000", 1922 "UMask": "0x1" 1923 }, 1924 { 1925 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", 1926 "EventCode": "0xB7", 1927 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", 1928 "MSRIndex": "0x1A6", 1929 "MSRValue": "0x202", 1930 "SampleAfterValue": "100000", 1931 "UMask": "0x1" 1932 }, 1933 { 1934 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", 1935 "EventCode": "0xB7", 1936 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", 1937 "MSRIndex": "0x1A6", 1938 "MSRValue": "0x402", 1939 "SampleAfterValue": "100000", 1940 "UMask": "0x1" 1941 }, 1942 { 1943 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", 1944 "EventCode": "0xB7", 1945 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", 1946 "MSRIndex": "0x1A6", 1947 "MSRValue": "0x702", 1948 "SampleAfterValue": "100000", 1949 "UMask": "0x1" 1950 }, 1951 { 1952 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", 1953 "EventCode": "0xB7", 1954 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", 1955 "MSRIndex": "0x1A6", 1956 "MSRValue": "0x4702", 1957 "SampleAfterValue": "100000", 1958 "UMask": "0x1" 1959 }, 1960 { 1961 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", 1962 "EventCode": "0xB7", 1963 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", 1964 "MSRIndex": "0x1A6", 1965 "MSRValue": "0x1802", 1966 "SampleAfterValue": "100000", 1967 "UMask": "0x1" 1968 }, 1969 { 1970 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", 1971 "EventCode": "0xB7", 1972 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", 1973 "MSRIndex": "0x1A6", 1974 "MSRValue": "0x3802", 1975 "SampleAfterValue": "100000", 1976 "UMask": "0x1" 1977 }, 1978 { 1979 "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", 1980 "EventCode": "0xB7", 1981 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", 1982 "MSRIndex": "0x1A6", 1983 "MSRValue": "0x1002", 1984 "SampleAfterValue": "100000", 1985 "UMask": "0x1" 1986 }, 1987 { 1988 "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", 1989 "EventCode": "0xB7", 1990 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", 1991 "MSRIndex": "0x1A6", 1992 "MSRValue": "0x802", 1993 "SampleAfterValue": "100000", 1994 "UMask": "0x1" 1995 }, 1996 { 1997 "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", 1998 "EventCode": "0xB7", 1999 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", 2000 "MSRIndex": "0x1A6", 2001 "MSRValue": "0x7F80", 2002 "SampleAfterValue": "100000", 2003 "UMask": "0x1" 2004 }, 2005 { 2006 "BriefDescription": "All offcore other requests", 2007 "EventCode": "0xB7", 2008 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", 2009 "MSRIndex": "0x1A6", 2010 "MSRValue": "0xFF80", 2011 "SampleAfterValue": "100000", 2012 "UMask": "0x1" 2013 }, 2014 { 2015 "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", 2016 "EventCode": "0xB7", 2017 "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", 2018 "MSRIndex": "0x1A6", 2019 "MSRValue": "0x8080", 2020 "SampleAfterValue": "100000", 2021 "UMask": "0x1" 2022 }, 2023 { 2024 "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", 2025 "EventCode": "0xB7", 2026 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", 2027 "MSRIndex": "0x1A6", 2028 "MSRValue": "0x180", 2029 "SampleAfterValue": "100000", 2030 "UMask": "0x1" 2031 }, 2032 { 2033 "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", 2034 "EventCode": "0xB7", 2035 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", 2036 "MSRIndex": "0x1A6", 2037 "MSRValue": "0x280", 2038 "SampleAfterValue": "100000", 2039 "UMask": "0x1" 2040 }, 2041 { 2042 "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", 2043 "EventCode": "0xB7", 2044 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", 2045 "MSRIndex": "0x1A6", 2046 "MSRValue": "0x480", 2047 "SampleAfterValue": "100000", 2048 "UMask": "0x1" 2049 }, 2050 { 2051 "BriefDescription": "Offcore other requests satisfied by the LLC", 2052 "EventCode": "0xB7", 2053 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", 2054 "MSRIndex": "0x1A6", 2055 "MSRValue": "0x780", 2056 "SampleAfterValue": "100000", 2057 "UMask": "0x1" 2058 }, 2059 { 2060 "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", 2061 "EventCode": "0xB7", 2062 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", 2063 "MSRIndex": "0x1A6", 2064 "MSRValue": "0x4780", 2065 "SampleAfterValue": "100000", 2066 "UMask": "0x1" 2067 }, 2068 { 2069 "BriefDescription": "Offcore other requests satisfied by a remote cache", 2070 "EventCode": "0xB7", 2071 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", 2072 "MSRIndex": "0x1A6", 2073 "MSRValue": "0x1880", 2074 "SampleAfterValue": "100000", 2075 "UMask": "0x1" 2076 }, 2077 { 2078 "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", 2079 "EventCode": "0xB7", 2080 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", 2081 "MSRIndex": "0x1A6", 2082 "MSRValue": "0x3880", 2083 "SampleAfterValue": "100000", 2084 "UMask": "0x1" 2085 }, 2086 { 2087 "BriefDescription": "Offcore other requests that HIT in a remote cache", 2088 "EventCode": "0xB7", 2089 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", 2090 "MSRIndex": "0x1A6", 2091 "MSRValue": "0x1080", 2092 "SampleAfterValue": "100000", 2093 "UMask": "0x1" 2094 }, 2095 { 2096 "BriefDescription": "Offcore other requests that HITM in a remote cache", 2097 "EventCode": "0xB7", 2098 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", 2099 "MSRIndex": "0x1A6", 2100 "MSRValue": "0x880", 2101 "SampleAfterValue": "100000", 2102 "UMask": "0x1" 2103 }, 2104 { 2105 "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", 2106 "EventCode": "0xB7", 2107 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", 2108 "MSRIndex": "0x1A6", 2109 "MSRValue": "0x7F30", 2110 "SampleAfterValue": "100000", 2111 "UMask": "0x1" 2112 }, 2113 { 2114 "BriefDescription": "All offcore prefetch data requests", 2115 "EventCode": "0xB7", 2116 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", 2117 "MSRIndex": "0x1A6", 2118 "MSRValue": "0xFF30", 2119 "SampleAfterValue": "100000", 2120 "UMask": "0x1" 2121 }, 2122 { 2123 "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", 2124 "EventCode": "0xB7", 2125 "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", 2126 "MSRIndex": "0x1A6", 2127 "MSRValue": "0x8030", 2128 "SampleAfterValue": "100000", 2129 "UMask": "0x1" 2130 }, 2131 { 2132 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", 2133 "EventCode": "0xB7", 2134 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", 2135 "MSRIndex": "0x1A6", 2136 "MSRValue": "0x130", 2137 "SampleAfterValue": "100000", 2138 "UMask": "0x1" 2139 }, 2140 { 2141 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", 2142 "EventCode": "0xB7", 2143 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", 2144 "MSRIndex": "0x1A6", 2145 "MSRValue": "0x230", 2146 "SampleAfterValue": "100000", 2147 "UMask": "0x1" 2148 }, 2149 { 2150 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", 2151 "EventCode": "0xB7", 2152 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", 2153 "MSRIndex": "0x1A6", 2154 "MSRValue": "0x430", 2155 "SampleAfterValue": "100000", 2156 "UMask": "0x1" 2157 }, 2158 { 2159 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", 2160 "EventCode": "0xB7", 2161 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", 2162 "MSRIndex": "0x1A6", 2163 "MSRValue": "0x730", 2164 "SampleAfterValue": "100000", 2165 "UMask": "0x1" 2166 }, 2167 { 2168 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", 2169 "EventCode": "0xB7", 2170 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", 2171 "MSRIndex": "0x1A6", 2172 "MSRValue": "0x4730", 2173 "SampleAfterValue": "100000", 2174 "UMask": "0x1" 2175 }, 2176 { 2177 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", 2178 "EventCode": "0xB7", 2179 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", 2180 "MSRIndex": "0x1A6", 2181 "MSRValue": "0x1830", 2182 "SampleAfterValue": "100000", 2183 "UMask": "0x1" 2184 }, 2185 { 2186 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", 2187 "EventCode": "0xB7", 2188 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", 2189 "MSRIndex": "0x1A6", 2190 "MSRValue": "0x3830", 2191 "SampleAfterValue": "100000", 2192 "UMask": "0x1" 2193 }, 2194 { 2195 "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", 2196 "EventCode": "0xB7", 2197 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", 2198 "MSRIndex": "0x1A6", 2199 "MSRValue": "0x1030", 2200 "SampleAfterValue": "100000", 2201 "UMask": "0x1" 2202 }, 2203 { 2204 "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", 2205 "EventCode": "0xB7", 2206 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", 2207 "MSRIndex": "0x1A6", 2208 "MSRValue": "0x830", 2209 "SampleAfterValue": "100000", 2210 "UMask": "0x1" 2211 }, 2212 { 2213 "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", 2214 "EventCode": "0xB7", 2215 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", 2216 "MSRIndex": "0x1A6", 2217 "MSRValue": "0x7F10", 2218 "SampleAfterValue": "100000", 2219 "UMask": "0x1" 2220 }, 2221 { 2222 "BriefDescription": "All offcore prefetch data reads", 2223 "EventCode": "0xB7", 2224 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", 2225 "MSRIndex": "0x1A6", 2226 "MSRValue": "0xFF10", 2227 "SampleAfterValue": "100000", 2228 "UMask": "0x1" 2229 }, 2230 { 2231 "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", 2232 "EventCode": "0xB7", 2233 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", 2234 "MSRIndex": "0x1A6", 2235 "MSRValue": "0x8010", 2236 "SampleAfterValue": "100000", 2237 "UMask": "0x1" 2238 }, 2239 { 2240 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", 2241 "EventCode": "0xB7", 2242 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", 2243 "MSRIndex": "0x1A6", 2244 "MSRValue": "0x110", 2245 "SampleAfterValue": "100000", 2246 "UMask": "0x1" 2247 }, 2248 { 2249 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", 2250 "EventCode": "0xB7", 2251 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 2252 "MSRIndex": "0x1A6", 2253 "MSRValue": "0x210", 2254 "SampleAfterValue": "100000", 2255 "UMask": "0x1" 2256 }, 2257 { 2258 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", 2259 "EventCode": "0xB7", 2260 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 2261 "MSRIndex": "0x1A6", 2262 "MSRValue": "0x410", 2263 "SampleAfterValue": "100000", 2264 "UMask": "0x1" 2265 }, 2266 { 2267 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", 2268 "EventCode": "0xB7", 2269 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", 2270 "MSRIndex": "0x1A6", 2271 "MSRValue": "0x710", 2272 "SampleAfterValue": "100000", 2273 "UMask": "0x1" 2274 }, 2275 { 2276 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", 2277 "EventCode": "0xB7", 2278 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", 2279 "MSRIndex": "0x1A6", 2280 "MSRValue": "0x4710", 2281 "SampleAfterValue": "100000", 2282 "UMask": "0x1" 2283 }, 2284 { 2285 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", 2286 "EventCode": "0xB7", 2287 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", 2288 "MSRIndex": "0x1A6", 2289 "MSRValue": "0x1810", 2290 "SampleAfterValue": "100000", 2291 "UMask": "0x1" 2292 }, 2293 { 2294 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", 2295 "EventCode": "0xB7", 2296 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", 2297 "MSRIndex": "0x1A6", 2298 "MSRValue": "0x3810", 2299 "SampleAfterValue": "100000", 2300 "UMask": "0x1" 2301 }, 2302 { 2303 "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", 2304 "EventCode": "0xB7", 2305 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", 2306 "MSRIndex": "0x1A6", 2307 "MSRValue": "0x1010", 2308 "SampleAfterValue": "100000", 2309 "UMask": "0x1" 2310 }, 2311 { 2312 "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", 2313 "EventCode": "0xB7", 2314 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", 2315 "MSRIndex": "0x1A6", 2316 "MSRValue": "0x810", 2317 "SampleAfterValue": "100000", 2318 "UMask": "0x1" 2319 }, 2320 { 2321 "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", 2322 "EventCode": "0xB7", 2323 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", 2324 "MSRIndex": "0x1A6", 2325 "MSRValue": "0x7F40", 2326 "SampleAfterValue": "100000", 2327 "UMask": "0x1" 2328 }, 2329 { 2330 "BriefDescription": "All offcore prefetch code reads", 2331 "EventCode": "0xB7", 2332 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", 2333 "MSRIndex": "0x1A6", 2334 "MSRValue": "0xFF40", 2335 "SampleAfterValue": "100000", 2336 "UMask": "0x1" 2337 }, 2338 { 2339 "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", 2340 "EventCode": "0xB7", 2341 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", 2342 "MSRIndex": "0x1A6", 2343 "MSRValue": "0x8040", 2344 "SampleAfterValue": "100000", 2345 "UMask": "0x1" 2346 }, 2347 { 2348 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", 2349 "EventCode": "0xB7", 2350 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", 2351 "MSRIndex": "0x1A6", 2352 "MSRValue": "0x140", 2353 "SampleAfterValue": "100000", 2354 "UMask": "0x1" 2355 }, 2356 { 2357 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", 2358 "EventCode": "0xB7", 2359 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2360 "MSRIndex": "0x1A6", 2361 "MSRValue": "0x240", 2362 "SampleAfterValue": "100000", 2363 "UMask": "0x1" 2364 }, 2365 { 2366 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", 2367 "EventCode": "0xB7", 2368 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2369 "MSRIndex": "0x1A6", 2370 "MSRValue": "0x440", 2371 "SampleAfterValue": "100000", 2372 "UMask": "0x1" 2373 }, 2374 { 2375 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", 2376 "EventCode": "0xB7", 2377 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", 2378 "MSRIndex": "0x1A6", 2379 "MSRValue": "0x740", 2380 "SampleAfterValue": "100000", 2381 "UMask": "0x1" 2382 }, 2383 { 2384 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", 2385 "EventCode": "0xB7", 2386 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", 2387 "MSRIndex": "0x1A6", 2388 "MSRValue": "0x4740", 2389 "SampleAfterValue": "100000", 2390 "UMask": "0x1" 2391 }, 2392 { 2393 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", 2394 "EventCode": "0xB7", 2395 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", 2396 "MSRIndex": "0x1A6", 2397 "MSRValue": "0x1840", 2398 "SampleAfterValue": "100000", 2399 "UMask": "0x1" 2400 }, 2401 { 2402 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", 2403 "EventCode": "0xB7", 2404 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", 2405 "MSRIndex": "0x1A6", 2406 "MSRValue": "0x3840", 2407 "SampleAfterValue": "100000", 2408 "UMask": "0x1" 2409 }, 2410 { 2411 "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", 2412 "EventCode": "0xB7", 2413 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", 2414 "MSRIndex": "0x1A6", 2415 "MSRValue": "0x1040", 2416 "SampleAfterValue": "100000", 2417 "UMask": "0x1" 2418 }, 2419 { 2420 "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", 2421 "EventCode": "0xB7", 2422 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", 2423 "MSRIndex": "0x1A6", 2424 "MSRValue": "0x840", 2425 "SampleAfterValue": "100000", 2426 "UMask": "0x1" 2427 }, 2428 { 2429 "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", 2430 "EventCode": "0xB7", 2431 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", 2432 "MSRIndex": "0x1A6", 2433 "MSRValue": "0x7F20", 2434 "SampleAfterValue": "100000", 2435 "UMask": "0x1" 2436 }, 2437 { 2438 "BriefDescription": "All offcore prefetch RFO requests", 2439 "EventCode": "0xB7", 2440 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", 2441 "MSRIndex": "0x1A6", 2442 "MSRValue": "0xFF20", 2443 "SampleAfterValue": "100000", 2444 "UMask": "0x1" 2445 }, 2446 { 2447 "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", 2448 "EventCode": "0xB7", 2449 "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", 2450 "MSRIndex": "0x1A6", 2451 "MSRValue": "0x8020", 2452 "SampleAfterValue": "100000", 2453 "UMask": "0x1" 2454 }, 2455 { 2456 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", 2457 "EventCode": "0xB7", 2458 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", 2459 "MSRIndex": "0x1A6", 2460 "MSRValue": "0x120", 2461 "SampleAfterValue": "100000", 2462 "UMask": "0x1" 2463 }, 2464 { 2465 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", 2466 "EventCode": "0xB7", 2467 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", 2468 "MSRIndex": "0x1A6", 2469 "MSRValue": "0x220", 2470 "SampleAfterValue": "100000", 2471 "UMask": "0x1" 2472 }, 2473 { 2474 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", 2475 "EventCode": "0xB7", 2476 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", 2477 "MSRIndex": "0x1A6", 2478 "MSRValue": "0x420", 2479 "SampleAfterValue": "100000", 2480 "UMask": "0x1" 2481 }, 2482 { 2483 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", 2484 "EventCode": "0xB7", 2485 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", 2486 "MSRIndex": "0x1A6", 2487 "MSRValue": "0x720", 2488 "SampleAfterValue": "100000", 2489 "UMask": "0x1" 2490 }, 2491 { 2492 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", 2493 "EventCode": "0xB7", 2494 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", 2495 "MSRIndex": "0x1A6", 2496 "MSRValue": "0x4720", 2497 "SampleAfterValue": "100000", 2498 "UMask": "0x1" 2499 }, 2500 { 2501 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", 2502 "EventCode": "0xB7", 2503 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", 2504 "MSRIndex": "0x1A6", 2505 "MSRValue": "0x1820", 2506 "SampleAfterValue": "100000", 2507 "UMask": "0x1" 2508 }, 2509 { 2510 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", 2511 "EventCode": "0xB7", 2512 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", 2513 "MSRIndex": "0x1A6", 2514 "MSRValue": "0x3820", 2515 "SampleAfterValue": "100000", 2516 "UMask": "0x1" 2517 }, 2518 { 2519 "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", 2520 "EventCode": "0xB7", 2521 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", 2522 "MSRIndex": "0x1A6", 2523 "MSRValue": "0x1020", 2524 "SampleAfterValue": "100000", 2525 "UMask": "0x1" 2526 }, 2527 { 2528 "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", 2529 "EventCode": "0xB7", 2530 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", 2531 "MSRIndex": "0x1A6", 2532 "MSRValue": "0x820", 2533 "SampleAfterValue": "100000", 2534 "UMask": "0x1" 2535 }, 2536 { 2537 "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", 2538 "EventCode": "0xB7", 2539 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", 2540 "MSRIndex": "0x1A6", 2541 "MSRValue": "0x7F70", 2542 "SampleAfterValue": "100000", 2543 "UMask": "0x1" 2544 }, 2545 { 2546 "BriefDescription": "All offcore prefetch requests", 2547 "EventCode": "0xB7", 2548 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", 2549 "MSRIndex": "0x1A6", 2550 "MSRValue": "0xFF70", 2551 "SampleAfterValue": "100000", 2552 "UMask": "0x1" 2553 }, 2554 { 2555 "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", 2556 "EventCode": "0xB7", 2557 "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", 2558 "MSRIndex": "0x1A6", 2559 "MSRValue": "0x8070", 2560 "SampleAfterValue": "100000", 2561 "UMask": "0x1" 2562 }, 2563 { 2564 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", 2565 "EventCode": "0xB7", 2566 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", 2567 "MSRIndex": "0x1A6", 2568 "MSRValue": "0x170", 2569 "SampleAfterValue": "100000", 2570 "UMask": "0x1" 2571 }, 2572 { 2573 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", 2574 "EventCode": "0xB7", 2575 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", 2576 "MSRIndex": "0x1A6", 2577 "MSRValue": "0x270", 2578 "SampleAfterValue": "100000", 2579 "UMask": "0x1" 2580 }, 2581 { 2582 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", 2583 "EventCode": "0xB7", 2584 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", 2585 "MSRIndex": "0x1A6", 2586 "MSRValue": "0x470", 2587 "SampleAfterValue": "100000", 2588 "UMask": "0x1" 2589 }, 2590 { 2591 "BriefDescription": "Offcore prefetch requests satisfied by the LLC", 2592 "EventCode": "0xB7", 2593 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", 2594 "MSRIndex": "0x1A6", 2595 "MSRValue": "0x770", 2596 "SampleAfterValue": "100000", 2597 "UMask": "0x1" 2598 }, 2599 { 2600 "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", 2601 "EventCode": "0xB7", 2602 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", 2603 "MSRIndex": "0x1A6", 2604 "MSRValue": "0x4770", 2605 "SampleAfterValue": "100000", 2606 "UMask": "0x1" 2607 }, 2608 { 2609 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", 2610 "EventCode": "0xB7", 2611 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", 2612 "MSRIndex": "0x1A6", 2613 "MSRValue": "0x1870", 2614 "SampleAfterValue": "100000", 2615 "UMask": "0x1" 2616 }, 2617 { 2618 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", 2619 "EventCode": "0xB7", 2620 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", 2621 "MSRIndex": "0x1A6", 2622 "MSRValue": "0x3870", 2623 "SampleAfterValue": "100000", 2624 "UMask": "0x1" 2625 }, 2626 { 2627 "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", 2628 "EventCode": "0xB7", 2629 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", 2630 "MSRIndex": "0x1A6", 2631 "MSRValue": "0x1070", 2632 "SampleAfterValue": "100000", 2633 "UMask": "0x1" 2634 }, 2635 { 2636 "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", 2637 "EventCode": "0xB7", 2638 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", 2639 "MSRIndex": "0x1A6", 2640 "MSRValue": "0x870", 2641 "SampleAfterValue": "100000", 2642 "UMask": "0x1" 2643 }, 2644 { 2645 "BriefDescription": "Super Queue lock splits across a cache line", 2646 "EventCode": "0xF4", 2647 "EventName": "SQ_MISC.SPLIT_LOCK", 2648 "SampleAfterValue": "2000000", 2649 "UMask": "0x10" 2650 }, 2651 { 2652 "BriefDescription": "Loads delayed with at-Retirement block code", 2653 "EventCode": "0x6", 2654 "EventName": "STORE_BLOCKS.AT_RET", 2655 "SampleAfterValue": "200000", 2656 "UMask": "0x4" 2657 }, 2658 { 2659 "BriefDescription": "Cacheable loads delayed with L1D block code", 2660 "EventCode": "0x6", 2661 "EventName": "STORE_BLOCKS.L1D_BLOCK", 2662 "SampleAfterValue": "200000", 2663 "UMask": "0x8" 2664 } 2665] 2666