1[
2    {
3        "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
4        "EventCode": "0x12",
5        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
6        "SampleAfterValue": "100003",
7        "UMask": "0xe",
8        "Unit": "cpu_core"
9    },
10    {
11        "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
12        "EventCode": "0x13",
13        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
14        "SampleAfterValue": "100003",
15        "UMask": "0xe",
16        "Unit": "cpu_core"
17    },
18    {
19        "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
20        "EventCode": "0x85",
21        "EventName": "ITLB_MISSES.WALK_COMPLETED",
22        "SampleAfterValue": "200003",
23        "UMask": "0xe",
24        "Unit": "cpu_atom"
25    },
26    {
27        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
28        "EventCode": "0x11",
29        "EventName": "ITLB_MISSES.WALK_COMPLETED",
30        "SampleAfterValue": "100003",
31        "UMask": "0xe",
32        "Unit": "cpu_core"
33    }
34]
35