1[
2    {
3        "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
4        "CollectPEBSRecord": "2",
5        "Counter": "0,1,2,3,4,5,6,7",
6        "EventCode": "0x85",
7        "EventName": "ITLB_MISSES.WALK_COMPLETED",
8        "PEBScounters": "0,1,2,3,4,5,6,7",
9        "SampleAfterValue": "200003",
10        "UMask": "0xe",
11        "Unit": "cpu_atom"
12    },
13    {
14        "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
15        "CollectPEBSRecord": "2",
16        "Counter": "0,1,2,3",
17        "EventCode": "0x12",
18        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
19        "PEBScounters": "0,1,2,3",
20        "SampleAfterValue": "100003",
21        "UMask": "0xe",
22        "Unit": "cpu_core"
23    },
24    {
25        "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
26        "CollectPEBSRecord": "2",
27        "Counter": "0,1,2,3",
28        "EventCode": "0x13",
29        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
30        "PEBScounters": "0,1,2,3",
31        "SampleAfterValue": "100003",
32        "UMask": "0xe",
33        "Unit": "cpu_core"
34    },
35    {
36        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
37        "CollectPEBSRecord": "2",
38        "Counter": "0,1,2,3",
39        "EventCode": "0x11",
40        "EventName": "ITLB_MISSES.WALK_COMPLETED",
41        "PEBScounters": "0,1,2,3",
42        "SampleAfterValue": "100003",
43        "UMask": "0xe",
44        "Unit": "cpu_core"
45    }
46]
47