1*1ab4ef06SIan Rogers[ 2*1ab4ef06SIan Rogers { 3*1ab4ef06SIan Rogers "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.", 4*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 5*1ab4ef06SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 6*1ab4ef06SIan Rogers "EventCode": "0x85", 7*1ab4ef06SIan Rogers "EventName": "ITLB_MISSES.WALK_COMPLETED", 8*1ab4ef06SIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 9*1ab4ef06SIan Rogers "SampleAfterValue": "200003", 10*1ab4ef06SIan Rogers "UMask": "0xe", 11*1ab4ef06SIan Rogers "Unit": "cpu_atom" 12*1ab4ef06SIan Rogers }, 13*1ab4ef06SIan Rogers { 14*1ab4ef06SIan Rogers "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", 15*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 16*1ab4ef06SIan Rogers "Counter": "0,1,2,3", 17*1ab4ef06SIan Rogers "EventCode": "0x12", 18*1ab4ef06SIan Rogers "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", 19*1ab4ef06SIan Rogers "PEBScounters": "0,1,2,3", 20*1ab4ef06SIan Rogers "SampleAfterValue": "100003", 21*1ab4ef06SIan Rogers "UMask": "0xe", 22*1ab4ef06SIan Rogers "Unit": "cpu_core" 23*1ab4ef06SIan Rogers }, 24*1ab4ef06SIan Rogers { 25*1ab4ef06SIan Rogers "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", 26*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 27*1ab4ef06SIan Rogers "Counter": "0,1,2,3", 28*1ab4ef06SIan Rogers "EventCode": "0x13", 29*1ab4ef06SIan Rogers "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", 30*1ab4ef06SIan Rogers "PEBScounters": "0,1,2,3", 31*1ab4ef06SIan Rogers "SampleAfterValue": "100003", 32*1ab4ef06SIan Rogers "UMask": "0xe", 33*1ab4ef06SIan Rogers "Unit": "cpu_core" 34*1ab4ef06SIan Rogers }, 35*1ab4ef06SIan Rogers { 36*1ab4ef06SIan Rogers "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", 37*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 38*1ab4ef06SIan Rogers "Counter": "0,1,2,3", 39*1ab4ef06SIan Rogers "EventCode": "0x11", 40*1ab4ef06SIan Rogers "EventName": "ITLB_MISSES.WALK_COMPLETED", 41*1ab4ef06SIan Rogers "PEBScounters": "0,1,2,3", 42*1ab4ef06SIan Rogers "SampleAfterValue": "100003", 43*1ab4ef06SIan Rogers "UMask": "0xe", 44*1ab4ef06SIan Rogers "Unit": "cpu_core" 45*1ab4ef06SIan Rogers } 46*1ab4ef06SIan Rogers] 47