1[
2    {
3        "BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
4        "CollectPEBSRecord": "2",
5        "Counter": "0,1,2,3,4,5,6,7",
6        "EventCode": "0xc4",
7        "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
8        "PEBS": "1",
9        "PEBScounters": "0,1,2,3,4,5,6,7",
10        "SampleAfterValue": "200003",
11        "Unit": "cpu_atom"
12    },
13    {
14        "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.",
15        "CollectPEBSRecord": "2",
16        "Counter": "0,1,2,3,4,5,6,7",
17        "EventCode": "0xc5",
18        "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
19        "PEBS": "1",
20        "PEBScounters": "0,1,2,3,4,5,6,7",
21        "SampleAfterValue": "200003",
22        "Unit": "cpu_atom"
23    },
24    {
25        "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
26        "CollectPEBSRecord": "2",
27        "Counter": "33",
28        "EventName": "CPU_CLK_UNHALTED.CORE",
29        "PEBScounters": "33",
30        "SampleAfterValue": "2000003",
31        "UMask": "0x2",
32        "Unit": "cpu_atom"
33    },
34    {
35        "BriefDescription": "Counts the number of unhalted core clock cycles[This event is alias to CPU_CLK_UNHALTED.THREAD_P]",
36        "CollectPEBSRecord": "2",
37        "Counter": "0,1,2,3,4,5,6,7",
38        "EventCode": "0x3c",
39        "EventName": "CPU_CLK_UNHALTED.CORE_P",
40        "PEBScounters": "0,1,2,3,4,5,6,7",
41        "SampleAfterValue": "2000003",
42        "Unit": "cpu_atom"
43    },
44    {
45        "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
46        "CollectPEBSRecord": "2",
47        "Counter": "34",
48        "EventName": "CPU_CLK_UNHALTED.REF_TSC",
49        "PEBScounters": "34",
50        "SampleAfterValue": "2000003",
51        "UMask": "0x3",
52        "Unit": "cpu_atom"
53    },
54    {
55        "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
56        "CollectPEBSRecord": "2",
57        "Counter": "33",
58        "EventName": "CPU_CLK_UNHALTED.THREAD",
59        "PEBScounters": "33",
60        "SampleAfterValue": "2000003",
61        "UMask": "0x2",
62        "Unit": "cpu_atom"
63    },
64    {
65        "BriefDescription": "Counts the number of unhalted core clock cycles[This event is alias to CPU_CLK_UNHALTED.CORE_P]",
66        "CollectPEBSRecord": "2",
67        "Counter": "0,1,2,3,4,5,6,7",
68        "EventCode": "0x3c",
69        "EventName": "CPU_CLK_UNHALTED.THREAD_P",
70        "PEBScounters": "0,1,2,3,4,5,6,7",
71        "SampleAfterValue": "2000003",
72        "Unit": "cpu_atom"
73    },
74    {
75        "BriefDescription": "Fixed Counter: Counts the number of instructions retired",
76        "CollectPEBSRecord": "2",
77        "Counter": "32",
78        "EventName": "INST_RETIRED.ANY",
79        "PEBS": "1",
80        "PEBScounters": "32",
81        "SampleAfterValue": "2000003",
82        "UMask": "0x1",
83        "Unit": "cpu_atom"
84    },
85    {
86        "BriefDescription": "Counts the number of instructions retired",
87        "CollectPEBSRecord": "2",
88        "Counter": "0,1,2,3,4,5,6,7",
89        "EventCode": "0xc0",
90        "EventName": "INST_RETIRED.ANY_P",
91        "PEBS": "1",
92        "PEBScounters": "0,1,2,3,4,5,6,7",
93        "SampleAfterValue": "2000003",
94        "Unit": "cpu_atom"
95    },
96    {
97        "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
98        "CollectPEBSRecord": "2",
99        "Counter": "0,1,2,3,4,5,6,7",
100        "EventCode": "0x73",
101        "EventName": "TOPDOWN_BAD_SPECULATION.ALL",
102        "PEBScounters": "0,1,2,3,4,5,6,7",
103        "SampleAfterValue": "1000003",
104        "Unit": "cpu_atom"
105    },
106    {
107        "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls",
108        "CollectPEBSRecord": "2",
109        "Counter": "0,1,2,3,4,5,6,7",
110        "EventCode": "0x74",
111        "EventName": "TOPDOWN_BE_BOUND.ALL",
112        "PEBScounters": "0,1,2,3,4,5,6,7",
113        "SampleAfterValue": "1000003",
114        "Unit": "cpu_atom"
115    },
116    {
117        "BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls",
118        "CollectPEBSRecord": "2",
119        "Counter": "0,1,2,3,4,5,6,7",
120        "EventCode": "0x71",
121        "EventName": "TOPDOWN_FE_BOUND.ALL",
122        "PEBScounters": "0,1,2,3,4,5,6,7",
123        "SampleAfterValue": "1000003",
124        "Unit": "cpu_atom"
125    },
126    {
127        "BriefDescription": "Counts the number of consumed retirement slots.  Similar to UOPS_RETIRED.ALL",
128        "CollectPEBSRecord": "2",
129        "Counter": "0,1,2,3,4,5,6,7",
130        "EventCode": "0x72",
131        "EventName": "TOPDOWN_RETIRING.ALL",
132        "PEBS": "1",
133        "PEBScounters": "0,1,2,3,4,5,6,7",
134        "SampleAfterValue": "1000003",
135        "Unit": "cpu_atom"
136    },
137    {
138        "BriefDescription": "All branch instructions retired.",
139        "CollectPEBSRecord": "2",
140        "Counter": "0,1,2,3,4,5,6,7",
141        "EventCode": "0xc4",
142        "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
143        "PEBS": "1",
144        "PEBScounters": "0,1,2,3,4,5,6,7",
145        "SampleAfterValue": "400009",
146        "Unit": "cpu_core"
147    },
148    {
149        "BriefDescription": "All mispredicted branch instructions retired.",
150        "CollectPEBSRecord": "2",
151        "Counter": "0,1,2,3,4,5,6,7",
152        "EventCode": "0xc5",
153        "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
154        "PEBS": "1",
155        "PEBScounters": "0,1,2,3,4,5,6,7",
156        "SampleAfterValue": "400009",
157        "Unit": "cpu_core"
158    },
159    {
160        "BriefDescription": "Reference cycles when the core is not in halt state.",
161        "CollectPEBSRecord": "2",
162        "Counter": "34",
163        "EventName": "CPU_CLK_UNHALTED.REF_TSC",
164        "PEBScounters": "34",
165        "SampleAfterValue": "2000003",
166        "UMask": "0x3",
167        "Unit": "cpu_core"
168    },
169    {
170        "BriefDescription": "Reference cycles when the core is not in halt state.",
171        "CollectPEBSRecord": "2",
172        "Counter": "0,1,2,3,4,5,6,7",
173        "EventCode": "0x3c",
174        "EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
175        "PEBScounters": "0,1,2,3,4,5,6,7",
176        "SampleAfterValue": "2000003",
177        "UMask": "0x1",
178        "Unit": "cpu_core"
179    },
180    {
181        "BriefDescription": "Core cycles when the thread is not in halt state",
182        "CollectPEBSRecord": "2",
183        "Counter": "33",
184        "EventName": "CPU_CLK_UNHALTED.THREAD",
185        "PEBScounters": "33",
186        "SampleAfterValue": "2000003",
187        "UMask": "0x2",
188        "Unit": "cpu_core"
189    },
190    {
191        "BriefDescription": "Thread cycles when thread is not in halt state",
192        "CollectPEBSRecord": "2",
193        "Counter": "0,1,2,3,4,5,6,7",
194        "EventCode": "0x3c",
195        "EventName": "CPU_CLK_UNHALTED.THREAD_P",
196        "PEBScounters": "0,1,2,3,4,5,6,7",
197        "SampleAfterValue": "2000003",
198        "Unit": "cpu_core"
199    },
200    {
201        "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
202        "CollectPEBSRecord": "2",
203        "Counter": "32",
204        "EventName": "INST_RETIRED.ANY",
205        "PEBS": "1",
206        "PEBScounters": "32",
207        "SampleAfterValue": "2000003",
208        "UMask": "0x1",
209        "Unit": "cpu_core"
210    },
211    {
212        "BriefDescription": "Number of instructions retired. General Counter - architectural event",
213        "CollectPEBSRecord": "2",
214        "Counter": "0,1,2,3,4,5,6,7",
215        "EventCode": "0xc0",
216        "EventName": "INST_RETIRED.ANY_P",
217        "PEBS": "1",
218        "PEBScounters": "1,2,3,4,5,6,7",
219        "SampleAfterValue": "2000003",
220        "Unit": "cpu_core"
221    },
222    {
223        "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
224        "CollectPEBSRecord": "2",
225        "Counter": "0,1,2,3",
226        "EventCode": "0x03",
227        "EventName": "LD_BLOCKS.STORE_FORWARD",
228        "PEBScounters": "0,1,2,3",
229        "SampleAfterValue": "100003",
230        "UMask": "0x82",
231        "Unit": "cpu_core"
232    },
233    {
234        "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
235        "CollectPEBSRecord": "2",
236        "Counter": "35",
237        "EventName": "TOPDOWN.SLOTS",
238        "PEBScounters": "35",
239        "SampleAfterValue": "10000003",
240        "UMask": "0x4",
241        "Unit": "cpu_core"
242    },
243    {
244        "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
245        "CollectPEBSRecord": "2",
246        "Counter": "0,1,2,3,4,5,6,7",
247        "EventCode": "0xa4",
248        "EventName": "TOPDOWN.SLOTS_P",
249        "PEBScounters": "0,1,2,3,4,5,6,7",
250        "SampleAfterValue": "10000003",
251        "UMask": "0x1",
252        "Unit": "cpu_core"
253    }
254]
255