1[
2    {
3        "BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
4        "EventCode": "0xc4",
5        "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
6        "PEBS": "1",
7        "SampleAfterValue": "200003",
8        "Unit": "cpu_atom"
9    },
10    {
11        "BriefDescription": "All branch instructions retired.",
12        "EventCode": "0xc4",
13        "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
14        "PEBS": "1",
15        "SampleAfterValue": "400009",
16        "Unit": "cpu_core"
17    },
18    {
19        "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.",
20        "EventCode": "0xc5",
21        "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
22        "PEBS": "1",
23        "SampleAfterValue": "200003",
24        "Unit": "cpu_atom"
25    },
26    {
27        "BriefDescription": "All mispredicted branch instructions retired.",
28        "EventCode": "0xc5",
29        "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
30        "PEBS": "1",
31        "SampleAfterValue": "400009",
32        "Unit": "cpu_core"
33    },
34    {
35        "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
36        "EventName": "CPU_CLK_UNHALTED.CORE",
37        "SampleAfterValue": "2000003",
38        "UMask": "0x2",
39        "Unit": "cpu_atom"
40    },
41    {
42        "BriefDescription": "Counts the number of unhalted core clock cycles[This event is alias to CPU_CLK_UNHALTED.THREAD_P]",
43        "EventCode": "0x3c",
44        "EventName": "CPU_CLK_UNHALTED.CORE_P",
45        "SampleAfterValue": "2000003",
46        "Unit": "cpu_atom"
47    },
48    {
49        "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
50        "EventName": "CPU_CLK_UNHALTED.REF_TSC",
51        "SampleAfterValue": "2000003",
52        "UMask": "0x3",
53        "Unit": "cpu_atom"
54    },
55    {
56        "BriefDescription": "Reference cycles when the core is not in halt state.",
57        "EventName": "CPU_CLK_UNHALTED.REF_TSC",
58        "SampleAfterValue": "2000003",
59        "UMask": "0x3",
60        "Unit": "cpu_core"
61    },
62    {
63        "BriefDescription": "Reference cycles when the core is not in halt state.",
64        "EventCode": "0x3c",
65        "EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
66        "SampleAfterValue": "2000003",
67        "UMask": "0x1",
68        "Unit": "cpu_core"
69    },
70    {
71        "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
72        "EventName": "CPU_CLK_UNHALTED.THREAD",
73        "SampleAfterValue": "2000003",
74        "UMask": "0x2",
75        "Unit": "cpu_atom"
76    },
77    {
78        "BriefDescription": "Core cycles when the thread is not in halt state",
79        "EventName": "CPU_CLK_UNHALTED.THREAD",
80        "SampleAfterValue": "2000003",
81        "UMask": "0x2",
82        "Unit": "cpu_core"
83    },
84    {
85        "BriefDescription": "Counts the number of unhalted core clock cycles[This event is alias to CPU_CLK_UNHALTED.CORE_P]",
86        "EventCode": "0x3c",
87        "EventName": "CPU_CLK_UNHALTED.THREAD_P",
88        "SampleAfterValue": "2000003",
89        "Unit": "cpu_atom"
90    },
91    {
92        "BriefDescription": "Thread cycles when thread is not in halt state",
93        "EventCode": "0x3c",
94        "EventName": "CPU_CLK_UNHALTED.THREAD_P",
95        "SampleAfterValue": "2000003",
96        "Unit": "cpu_core"
97    },
98    {
99        "BriefDescription": "Fixed Counter: Counts the number of instructions retired",
100        "EventName": "INST_RETIRED.ANY",
101        "PEBS": "1",
102        "SampleAfterValue": "2000003",
103        "UMask": "0x1",
104        "Unit": "cpu_atom"
105    },
106    {
107        "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
108        "EventName": "INST_RETIRED.ANY",
109        "PEBS": "1",
110        "SampleAfterValue": "2000003",
111        "UMask": "0x1",
112        "Unit": "cpu_core"
113    },
114    {
115        "BriefDescription": "Counts the number of instructions retired",
116        "EventCode": "0xc0",
117        "EventName": "INST_RETIRED.ANY_P",
118        "PEBS": "1",
119        "SampleAfterValue": "2000003",
120        "Unit": "cpu_atom"
121    },
122    {
123        "BriefDescription": "Number of instructions retired. General Counter - architectural event",
124        "EventCode": "0xc0",
125        "EventName": "INST_RETIRED.ANY_P",
126        "PEBS": "1",
127        "SampleAfterValue": "2000003",
128        "Unit": "cpu_core"
129    },
130    {
131        "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
132        "EventCode": "0x03",
133        "EventName": "LD_BLOCKS.STORE_FORWARD",
134        "SampleAfterValue": "100003",
135        "UMask": "0x82",
136        "Unit": "cpu_core"
137    },
138    {
139        "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
140        "EventName": "TOPDOWN.SLOTS",
141        "SampleAfterValue": "10000003",
142        "UMask": "0x4",
143        "Unit": "cpu_core"
144    },
145    {
146        "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
147        "EventCode": "0xa4",
148        "EventName": "TOPDOWN.SLOTS_P",
149        "SampleAfterValue": "10000003",
150        "UMask": "0x1",
151        "Unit": "cpu_core"
152    },
153    {
154        "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
155        "EventCode": "0x73",
156        "EventName": "TOPDOWN_BAD_SPECULATION.ALL",
157        "SampleAfterValue": "1000003",
158        "Unit": "cpu_atom"
159    },
160    {
161        "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls",
162        "EventCode": "0x74",
163        "EventName": "TOPDOWN_BE_BOUND.ALL",
164        "SampleAfterValue": "1000003",
165        "Unit": "cpu_atom"
166    },
167    {
168        "BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls",
169        "EventCode": "0x71",
170        "EventName": "TOPDOWN_FE_BOUND.ALL",
171        "SampleAfterValue": "1000003",
172        "Unit": "cpu_atom"
173    },
174    {
175        "BriefDescription": "Counts the number of consumed retirement slots.  Similar to UOPS_RETIRED.ALL",
176        "EventCode": "0x72",
177        "EventName": "TOPDOWN_RETIRING.ALL",
178        "PEBS": "1",
179        "SampleAfterValue": "1000003",
180        "Unit": "cpu_atom"
181    }
182]
183