1*1ab4ef06SIan Rogers[ 2*1ab4ef06SIan Rogers { 3*1ab4ef06SIan Rogers "BriefDescription": "Counts the total number of branch instructions retired for all branch types.", 4*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 5*1ab4ef06SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 6*1ab4ef06SIan Rogers "EventCode": "0xc4", 7*1ab4ef06SIan Rogers "EventName": "BR_INST_RETIRED.ALL_BRANCHES", 8*1ab4ef06SIan Rogers "PEBS": "1", 9*1ab4ef06SIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 10*1ab4ef06SIan Rogers "SampleAfterValue": "200003", 11*1ab4ef06SIan Rogers "Unit": "cpu_atom" 12*1ab4ef06SIan Rogers }, 13*1ab4ef06SIan Rogers { 14*1ab4ef06SIan Rogers "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.", 15*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 16*1ab4ef06SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 17*1ab4ef06SIan Rogers "EventCode": "0xc5", 18*1ab4ef06SIan Rogers "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", 19*1ab4ef06SIan Rogers "PEBS": "1", 20*1ab4ef06SIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 21*1ab4ef06SIan Rogers "SampleAfterValue": "200003", 22*1ab4ef06SIan Rogers "Unit": "cpu_atom" 23*1ab4ef06SIan Rogers }, 24*1ab4ef06SIan Rogers { 25*1ab4ef06SIan Rogers "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", 26*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 27*1ab4ef06SIan Rogers "Counter": "33", 28*1ab4ef06SIan Rogers "EventName": "CPU_CLK_UNHALTED.CORE", 29*1ab4ef06SIan Rogers "PEBScounters": "33", 30*1ab4ef06SIan Rogers "SampleAfterValue": "2000003", 31*1ab4ef06SIan Rogers "UMask": "0x2", 32*1ab4ef06SIan Rogers "Unit": "cpu_atom" 33*1ab4ef06SIan Rogers }, 34*1ab4ef06SIan Rogers { 35*1ab4ef06SIan Rogers "BriefDescription": "Counts the number of unhalted core clock cycles[This event is alias to CPU_CLK_UNHALTED.THREAD_P]", 36*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 37*1ab4ef06SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 38*1ab4ef06SIan Rogers "EventCode": "0x3c", 39*1ab4ef06SIan Rogers "EventName": "CPU_CLK_UNHALTED.CORE_P", 40*1ab4ef06SIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 41*1ab4ef06SIan Rogers "SampleAfterValue": "2000003", 42*1ab4ef06SIan Rogers "Unit": "cpu_atom" 43*1ab4ef06SIan Rogers }, 44*1ab4ef06SIan Rogers { 45*1ab4ef06SIan Rogers "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles", 46*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 47*1ab4ef06SIan Rogers "Counter": "34", 48*1ab4ef06SIan Rogers "EventName": "CPU_CLK_UNHALTED.REF_TSC", 49*1ab4ef06SIan Rogers "PEBScounters": "34", 50*1ab4ef06SIan Rogers "SampleAfterValue": "2000003", 51*1ab4ef06SIan Rogers "UMask": "0x3", 52*1ab4ef06SIan Rogers "Unit": "cpu_atom" 53*1ab4ef06SIan Rogers }, 54*1ab4ef06SIan Rogers { 55*1ab4ef06SIan Rogers "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", 56*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 57*1ab4ef06SIan Rogers "Counter": "33", 58*1ab4ef06SIan Rogers "EventName": "CPU_CLK_UNHALTED.THREAD", 59*1ab4ef06SIan Rogers "PEBScounters": "33", 60*1ab4ef06SIan Rogers "SampleAfterValue": "2000003", 61*1ab4ef06SIan Rogers "UMask": "0x2", 62*1ab4ef06SIan Rogers "Unit": "cpu_atom" 63*1ab4ef06SIan Rogers }, 64*1ab4ef06SIan Rogers { 65*1ab4ef06SIan Rogers "BriefDescription": "Counts the number of unhalted core clock cycles[This event is alias to CPU_CLK_UNHALTED.CORE_P]", 66*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 67*1ab4ef06SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 68*1ab4ef06SIan Rogers "EventCode": "0x3c", 69*1ab4ef06SIan Rogers "EventName": "CPU_CLK_UNHALTED.THREAD_P", 70*1ab4ef06SIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 71*1ab4ef06SIan Rogers "SampleAfterValue": "2000003", 72*1ab4ef06SIan Rogers "Unit": "cpu_atom" 73*1ab4ef06SIan Rogers }, 74*1ab4ef06SIan Rogers { 75*1ab4ef06SIan Rogers "BriefDescription": "Fixed Counter: Counts the number of instructions retired", 76*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 77*1ab4ef06SIan Rogers "Counter": "32", 78*1ab4ef06SIan Rogers "EventName": "INST_RETIRED.ANY", 79*1ab4ef06SIan Rogers "PEBS": "1", 80*1ab4ef06SIan Rogers "PEBScounters": "32", 81*1ab4ef06SIan Rogers "SampleAfterValue": "2000003", 82*1ab4ef06SIan Rogers "UMask": "0x1", 83*1ab4ef06SIan Rogers "Unit": "cpu_atom" 84*1ab4ef06SIan Rogers }, 85*1ab4ef06SIan Rogers { 86*1ab4ef06SIan Rogers "BriefDescription": "Counts the number of instructions retired", 87*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 88*1ab4ef06SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 89*1ab4ef06SIan Rogers "EventCode": "0xc0", 90*1ab4ef06SIan Rogers "EventName": "INST_RETIRED.ANY_P", 91*1ab4ef06SIan Rogers "PEBS": "1", 92*1ab4ef06SIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 93*1ab4ef06SIan Rogers "SampleAfterValue": "2000003", 94*1ab4ef06SIan Rogers "Unit": "cpu_atom" 95*1ab4ef06SIan Rogers }, 96*1ab4ef06SIan Rogers { 97*1ab4ef06SIan Rogers "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", 98*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 99*1ab4ef06SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 100*1ab4ef06SIan Rogers "EventCode": "0x73", 101*1ab4ef06SIan Rogers "EventName": "TOPDOWN_BAD_SPECULATION.ALL", 102*1ab4ef06SIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 103*1ab4ef06SIan Rogers "SampleAfterValue": "1000003", 104*1ab4ef06SIan Rogers "Unit": "cpu_atom" 105*1ab4ef06SIan Rogers }, 106*1ab4ef06SIan Rogers { 107*1ab4ef06SIan Rogers "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls", 108*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 109*1ab4ef06SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 110*1ab4ef06SIan Rogers "EventCode": "0x74", 111*1ab4ef06SIan Rogers "EventName": "TOPDOWN_BE_BOUND.ALL", 112*1ab4ef06SIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 113*1ab4ef06SIan Rogers "SampleAfterValue": "1000003", 114*1ab4ef06SIan Rogers "Unit": "cpu_atom" 115*1ab4ef06SIan Rogers }, 116*1ab4ef06SIan Rogers { 117*1ab4ef06SIan Rogers "BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls", 118*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 119*1ab4ef06SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 120*1ab4ef06SIan Rogers "EventCode": "0x71", 121*1ab4ef06SIan Rogers "EventName": "TOPDOWN_FE_BOUND.ALL", 122*1ab4ef06SIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 123*1ab4ef06SIan Rogers "SampleAfterValue": "1000003", 124*1ab4ef06SIan Rogers "Unit": "cpu_atom" 125*1ab4ef06SIan Rogers }, 126*1ab4ef06SIan Rogers { 127*1ab4ef06SIan Rogers "BriefDescription": "Counts the number of consumed retirement slots. Similar to UOPS_RETIRED.ALL", 128*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 129*1ab4ef06SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 130*1ab4ef06SIan Rogers "EventCode": "0x72", 131*1ab4ef06SIan Rogers "EventName": "TOPDOWN_RETIRING.ALL", 132*1ab4ef06SIan Rogers "PEBS": "1", 133*1ab4ef06SIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 134*1ab4ef06SIan Rogers "SampleAfterValue": "1000003", 135*1ab4ef06SIan Rogers "Unit": "cpu_atom" 136*1ab4ef06SIan Rogers }, 137*1ab4ef06SIan Rogers { 138*1ab4ef06SIan Rogers "BriefDescription": "All branch instructions retired.", 139*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 140*1ab4ef06SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 141*1ab4ef06SIan Rogers "EventCode": "0xc4", 142*1ab4ef06SIan Rogers "EventName": "BR_INST_RETIRED.ALL_BRANCHES", 143*1ab4ef06SIan Rogers "PEBS": "1", 144*1ab4ef06SIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 145*1ab4ef06SIan Rogers "SampleAfterValue": "400009", 146*1ab4ef06SIan Rogers "Unit": "cpu_core" 147*1ab4ef06SIan Rogers }, 148*1ab4ef06SIan Rogers { 149*1ab4ef06SIan Rogers "BriefDescription": "All mispredicted branch instructions retired.", 150*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 151*1ab4ef06SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 152*1ab4ef06SIan Rogers "EventCode": "0xc5", 153*1ab4ef06SIan Rogers "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", 154*1ab4ef06SIan Rogers "PEBS": "1", 155*1ab4ef06SIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 156*1ab4ef06SIan Rogers "SampleAfterValue": "400009", 157*1ab4ef06SIan Rogers "Unit": "cpu_core" 158*1ab4ef06SIan Rogers }, 159*1ab4ef06SIan Rogers { 160*1ab4ef06SIan Rogers "BriefDescription": "Reference cycles when the core is not in halt state.", 161*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 162*1ab4ef06SIan Rogers "Counter": "34", 163*1ab4ef06SIan Rogers "EventName": "CPU_CLK_UNHALTED.REF_TSC", 164*1ab4ef06SIan Rogers "PEBScounters": "34", 165*1ab4ef06SIan Rogers "SampleAfterValue": "2000003", 166*1ab4ef06SIan Rogers "UMask": "0x3", 167*1ab4ef06SIan Rogers "Unit": "cpu_core" 168*1ab4ef06SIan Rogers }, 169*1ab4ef06SIan Rogers { 170*1ab4ef06SIan Rogers "BriefDescription": "Reference cycles when the core is not in halt state.", 171*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 172*1ab4ef06SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 173*1ab4ef06SIan Rogers "EventCode": "0x3c", 174*1ab4ef06SIan Rogers "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", 175*1ab4ef06SIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 176*1ab4ef06SIan Rogers "SampleAfterValue": "2000003", 177*1ab4ef06SIan Rogers "UMask": "0x1", 178*1ab4ef06SIan Rogers "Unit": "cpu_core" 179*1ab4ef06SIan Rogers }, 180*1ab4ef06SIan Rogers { 181*1ab4ef06SIan Rogers "BriefDescription": "Core cycles when the thread is not in halt state", 182*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 183*1ab4ef06SIan Rogers "Counter": "33", 184*1ab4ef06SIan Rogers "EventName": "CPU_CLK_UNHALTED.THREAD", 185*1ab4ef06SIan Rogers "PEBScounters": "33", 186*1ab4ef06SIan Rogers "SampleAfterValue": "2000003", 187*1ab4ef06SIan Rogers "UMask": "0x2", 188*1ab4ef06SIan Rogers "Unit": "cpu_core" 189*1ab4ef06SIan Rogers }, 190*1ab4ef06SIan Rogers { 191*1ab4ef06SIan Rogers "BriefDescription": "Thread cycles when thread is not in halt state", 192*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 193*1ab4ef06SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 194*1ab4ef06SIan Rogers "EventCode": "0x3c", 195*1ab4ef06SIan Rogers "EventName": "CPU_CLK_UNHALTED.THREAD_P", 196*1ab4ef06SIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 197*1ab4ef06SIan Rogers "SampleAfterValue": "2000003", 198*1ab4ef06SIan Rogers "Unit": "cpu_core" 199*1ab4ef06SIan Rogers }, 200*1ab4ef06SIan Rogers { 201*1ab4ef06SIan Rogers "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", 202*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 203*1ab4ef06SIan Rogers "Counter": "32", 204*1ab4ef06SIan Rogers "EventName": "INST_RETIRED.ANY", 205*1ab4ef06SIan Rogers "PEBS": "1", 206*1ab4ef06SIan Rogers "PEBScounters": "32", 207*1ab4ef06SIan Rogers "SampleAfterValue": "2000003", 208*1ab4ef06SIan Rogers "UMask": "0x1", 209*1ab4ef06SIan Rogers "Unit": "cpu_core" 210*1ab4ef06SIan Rogers }, 211*1ab4ef06SIan Rogers { 212*1ab4ef06SIan Rogers "BriefDescription": "Number of instructions retired. General Counter - architectural event", 213*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 214*1ab4ef06SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 215*1ab4ef06SIan Rogers "EventCode": "0xc0", 216*1ab4ef06SIan Rogers "EventName": "INST_RETIRED.ANY_P", 217*1ab4ef06SIan Rogers "PEBS": "1", 218*1ab4ef06SIan Rogers "PEBScounters": "1,2,3,4,5,6,7", 219*1ab4ef06SIan Rogers "SampleAfterValue": "2000003", 220*1ab4ef06SIan Rogers "Unit": "cpu_core" 221*1ab4ef06SIan Rogers }, 222*1ab4ef06SIan Rogers { 223*1ab4ef06SIan Rogers "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", 224*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 225*1ab4ef06SIan Rogers "Counter": "0,1,2,3", 226*1ab4ef06SIan Rogers "EventCode": "0x03", 227*1ab4ef06SIan Rogers "EventName": "LD_BLOCKS.STORE_FORWARD", 228*1ab4ef06SIan Rogers "PEBScounters": "0,1,2,3", 229*1ab4ef06SIan Rogers "SampleAfterValue": "100003", 230*1ab4ef06SIan Rogers "UMask": "0x82", 231*1ab4ef06SIan Rogers "Unit": "cpu_core" 232*1ab4ef06SIan Rogers }, 233*1ab4ef06SIan Rogers { 234*1ab4ef06SIan Rogers "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", 235*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 236*1ab4ef06SIan Rogers "Counter": "35", 237*1ab4ef06SIan Rogers "EventName": "TOPDOWN.SLOTS", 238*1ab4ef06SIan Rogers "PEBScounters": "35", 239*1ab4ef06SIan Rogers "SampleAfterValue": "10000003", 240*1ab4ef06SIan Rogers "UMask": "0x4", 241*1ab4ef06SIan Rogers "Unit": "cpu_core" 242*1ab4ef06SIan Rogers }, 243*1ab4ef06SIan Rogers { 244*1ab4ef06SIan Rogers "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", 245*1ab4ef06SIan Rogers "CollectPEBSRecord": "2", 246*1ab4ef06SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 247*1ab4ef06SIan Rogers "EventCode": "0xa4", 248*1ab4ef06SIan Rogers "EventName": "TOPDOWN.SLOTS_P", 249*1ab4ef06SIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 250*1ab4ef06SIan Rogers "SampleAfterValue": "10000003", 251*1ab4ef06SIan Rogers "UMask": "0x1", 252*1ab4ef06SIan Rogers "Unit": "cpu_core" 253*1ab4ef06SIan Rogers } 254*1ab4ef06SIan Rogers] 255