11ab4ef06SIan Rogers[ 21ab4ef06SIan Rogers { 3*dfc83cc8SIan Rogers "BriefDescription": "Counts streaming stores that have any type of response.", 41ab4ef06SIan Rogers "EventCode": "0x2A,0x2B", 5*dfc83cc8SIan Rogers "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", 61ab4ef06SIan Rogers "MSRIndex": "0x1a6,0x1a7", 7*dfc83cc8SIan Rogers "MSRValue": "0x10800", 81ab4ef06SIan Rogers "SampleAfterValue": "100003", 91ab4ef06SIan Rogers "UMask": "0x1", 101ab4ef06SIan Rogers "Unit": "cpu_core" 111ab4ef06SIan Rogers }, 121ab4ef06SIan Rogers { 13*dfc83cc8SIan Rogers "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.", 14*dfc83cc8SIan Rogers "EventCode": "0xa5", 15*dfc83cc8SIan Rogers "EventName": "RS.EMPTY", 16*dfc83cc8SIan Rogers "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)", 17*dfc83cc8SIan Rogers "SampleAfterValue": "1000003", 18*dfc83cc8SIan Rogers "UMask": "0x7", 19*dfc83cc8SIan Rogers "Unit": "cpu_core" 20*dfc83cc8SIan Rogers }, 21*dfc83cc8SIan Rogers { 22*dfc83cc8SIan Rogers "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.", 23*dfc83cc8SIan Rogers "CounterMask": "1", 24*dfc83cc8SIan Rogers "EdgeDetect": "1", 25*dfc83cc8SIan Rogers "EventCode": "0xa5", 26*dfc83cc8SIan Rogers "EventName": "RS.EMPTY_COUNT", 27*dfc83cc8SIan Rogers "Invert": "1", 28*dfc83cc8SIan Rogers "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)", 295362e4d1SIan Rogers "SampleAfterValue": "100003", 30*dfc83cc8SIan Rogers "UMask": "0x7", 31*dfc83cc8SIan Rogers "Unit": "cpu_core" 32*dfc83cc8SIan Rogers }, 33*dfc83cc8SIan Rogers { 34*dfc83cc8SIan Rogers "BriefDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will only put the CPU into C0.1 activity state (not C0.2 activity state)", 35*dfc83cc8SIan Rogers "EventCode": "0x75", 36*dfc83cc8SIan Rogers "EventName": "SERIALIZATION.C01_MS_SCB", 37*dfc83cc8SIan Rogers "SampleAfterValue": "200003", 38*dfc83cc8SIan Rogers "UMask": "0x4", 395362e4d1SIan Rogers "Unit": "cpu_atom" 405362e4d1SIan Rogers }, 415362e4d1SIan Rogers { 42*dfc83cc8SIan Rogers "BriefDescription": "Cycles the uncore cannot take further requests", 43*dfc83cc8SIan Rogers "CounterMask": "1", 44*dfc83cc8SIan Rogers "EventCode": "0x2d", 45*dfc83cc8SIan Rogers "EventName": "XQ.FULL_CYCLES", 46*dfc83cc8SIan Rogers "PublicDescription": "number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache).", 47*dfc83cc8SIan Rogers "SampleAfterValue": "1000003", 481ab4ef06SIan Rogers "UMask": "0x1", 491ab4ef06SIan Rogers "Unit": "cpu_core" 501ab4ef06SIan Rogers } 511ab4ef06SIan Rogers] 52