11ab4ef06SIan Rogers[ 21ab4ef06SIan Rogers { 3*ab0cfb79SIan Rogers "BriefDescription": "ASSISTS.PAGE_FAULT", 4*ab0cfb79SIan Rogers "EventCode": "0xc1", 5*ab0cfb79SIan Rogers "EventName": "ASSISTS.PAGE_FAULT", 6*ab0cfb79SIan Rogers "SampleAfterValue": "1000003", 7*ab0cfb79SIan Rogers "UMask": "0x8", 8*ab0cfb79SIan Rogers "Unit": "cpu_core" 9*ab0cfb79SIan Rogers }, 10*ab0cfb79SIan Rogers { 11dfc83cc8SIan Rogers "BriefDescription": "Counts streaming stores that have any type of response.", 121ab4ef06SIan Rogers "EventCode": "0x2A,0x2B", 13dfc83cc8SIan Rogers "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", 141ab4ef06SIan Rogers "MSRIndex": "0x1a6,0x1a7", 15dfc83cc8SIan Rogers "MSRValue": "0x10800", 161ab4ef06SIan Rogers "SampleAfterValue": "100003", 171ab4ef06SIan Rogers "UMask": "0x1", 181ab4ef06SIan Rogers "Unit": "cpu_core" 191ab4ef06SIan Rogers }, 201ab4ef06SIan Rogers { 21dfc83cc8SIan Rogers "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.", 22dfc83cc8SIan Rogers "EventCode": "0xa5", 23dfc83cc8SIan Rogers "EventName": "RS.EMPTY", 24dfc83cc8SIan Rogers "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)", 25dfc83cc8SIan Rogers "SampleAfterValue": "1000003", 26dfc83cc8SIan Rogers "UMask": "0x7", 27dfc83cc8SIan Rogers "Unit": "cpu_core" 28dfc83cc8SIan Rogers }, 29dfc83cc8SIan Rogers { 30dfc83cc8SIan Rogers "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.", 31dfc83cc8SIan Rogers "CounterMask": "1", 32dfc83cc8SIan Rogers "EdgeDetect": "1", 33dfc83cc8SIan Rogers "EventCode": "0xa5", 34dfc83cc8SIan Rogers "EventName": "RS.EMPTY_COUNT", 35dfc83cc8SIan Rogers "Invert": "1", 36dfc83cc8SIan Rogers "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)", 375362e4d1SIan Rogers "SampleAfterValue": "100003", 38dfc83cc8SIan Rogers "UMask": "0x7", 39dfc83cc8SIan Rogers "Unit": "cpu_core" 40dfc83cc8SIan Rogers }, 41dfc83cc8SIan Rogers { 42*ab0cfb79SIan Rogers "BriefDescription": "RS.EMPTY_RESOURCE", 43*ab0cfb79SIan Rogers "EventCode": "0xa5", 44*ab0cfb79SIan Rogers "EventName": "RS.EMPTY_RESOURCE", 45*ab0cfb79SIan Rogers "SampleAfterValue": "1000003", 46*ab0cfb79SIan Rogers "UMask": "0x1", 47*ab0cfb79SIan Rogers "Unit": "cpu_core" 48*ab0cfb79SIan Rogers }, 49*ab0cfb79SIan Rogers { 50dfc83cc8SIan Rogers "BriefDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will only put the CPU into C0.1 activity state (not C0.2 activity state)", 51dfc83cc8SIan Rogers "EventCode": "0x75", 52dfc83cc8SIan Rogers "EventName": "SERIALIZATION.C01_MS_SCB", 53dfc83cc8SIan Rogers "SampleAfterValue": "200003", 54dfc83cc8SIan Rogers "UMask": "0x4", 555362e4d1SIan Rogers "Unit": "cpu_atom" 565362e4d1SIan Rogers }, 575362e4d1SIan Rogers { 58dfc83cc8SIan Rogers "BriefDescription": "Cycles the uncore cannot take further requests", 59dfc83cc8SIan Rogers "CounterMask": "1", 60dfc83cc8SIan Rogers "EventCode": "0x2d", 61dfc83cc8SIan Rogers "EventName": "XQ.FULL_CYCLES", 62dfc83cc8SIan Rogers "PublicDescription": "number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache).", 63dfc83cc8SIan Rogers "SampleAfterValue": "1000003", 641ab4ef06SIan Rogers "UMask": "0x1", 651ab4ef06SIan Rogers "Unit": "cpu_core" 661ab4ef06SIan Rogers } 671ab4ef06SIan Rogers] 68