1[
2    {
3        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
4        "Data_LA": "1",
5        "EventCode": "0xcd",
6        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
7        "MSRIndex": "0x3F6",
8        "MSRValue": "0x80",
9        "PEBS": "2",
10        "SampleAfterValue": "1009",
11        "UMask": "0x1",
12        "Unit": "cpu_core"
13    },
14    {
15        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
16        "Data_LA": "1",
17        "EventCode": "0xcd",
18        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
19        "MSRIndex": "0x3F6",
20        "MSRValue": "0x10",
21        "PEBS": "2",
22        "SampleAfterValue": "20011",
23        "UMask": "0x1",
24        "Unit": "cpu_core"
25    },
26    {
27        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
28        "Data_LA": "1",
29        "EventCode": "0xcd",
30        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
31        "MSRIndex": "0x3F6",
32        "MSRValue": "0x100",
33        "PEBS": "2",
34        "SampleAfterValue": "503",
35        "UMask": "0x1",
36        "Unit": "cpu_core"
37    },
38    {
39        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
40        "Data_LA": "1",
41        "EventCode": "0xcd",
42        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
43        "MSRIndex": "0x3F6",
44        "MSRValue": "0x20",
45        "PEBS": "2",
46        "SampleAfterValue": "100007",
47        "UMask": "0x1",
48        "Unit": "cpu_core"
49    },
50    {
51        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
52        "Data_LA": "1",
53        "EventCode": "0xcd",
54        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
55        "MSRIndex": "0x3F6",
56        "MSRValue": "0x4",
57        "PEBS": "2",
58        "SampleAfterValue": "100003",
59        "UMask": "0x1",
60        "Unit": "cpu_core"
61    },
62    {
63        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
64        "Data_LA": "1",
65        "EventCode": "0xcd",
66        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
67        "MSRIndex": "0x3F6",
68        "MSRValue": "0x200",
69        "PEBS": "2",
70        "SampleAfterValue": "101",
71        "UMask": "0x1",
72        "Unit": "cpu_core"
73    },
74    {
75        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
76        "Data_LA": "1",
77        "EventCode": "0xcd",
78        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
79        "MSRIndex": "0x3F6",
80        "MSRValue": "0x40",
81        "PEBS": "2",
82        "SampleAfterValue": "2003",
83        "UMask": "0x1",
84        "Unit": "cpu_core"
85    },
86    {
87        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
88        "Data_LA": "1",
89        "EventCode": "0xcd",
90        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
91        "MSRIndex": "0x3F6",
92        "MSRValue": "0x8",
93        "PEBS": "2",
94        "SampleAfterValue": "50021",
95        "UMask": "0x1",
96        "Unit": "cpu_core"
97    },
98    {
99        "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.",
100        "Data_LA": "1",
101        "EventCode": "0xcd",
102        "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE",
103        "PEBS": "2",
104        "SampleAfterValue": "1000003",
105        "UMask": "0x2",
106        "Unit": "cpu_core"
107    },
108    {
109        "BriefDescription": "Counts cacheable demand data reads were not supplied by the L3 cache.",
110        "EventCode": "0xB7",
111        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
112        "MSRIndex": "0x1a6,0x1a7",
113        "MSRValue": "0x3FBFC00001",
114        "SampleAfterValue": "100003",
115        "UMask": "0x1",
116        "Unit": "cpu_atom"
117    },
118    {
119        "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
120        "EventCode": "0x2A,0x2B",
121        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
122        "MSRIndex": "0x1a6,0x1a7",
123        "MSRValue": "0x3FBFC00001",
124        "SampleAfterValue": "100003",
125        "UMask": "0x1",
126        "Unit": "cpu_core"
127    },
128    {
129        "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO were not supplied by the L3 cache.",
130        "EventCode": "0xB7",
131        "EventName": "OCR.DEMAND_RFO.L3_MISS",
132        "MSRIndex": "0x1a6,0x1a7",
133        "MSRValue": "0x3FBFC00002",
134        "SampleAfterValue": "100003",
135        "UMask": "0x1",
136        "Unit": "cpu_atom"
137    },
138    {
139        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
140        "EventCode": "0x2A,0x2B",
141        "EventName": "OCR.DEMAND_RFO.L3_MISS",
142        "MSRIndex": "0x1a6,0x1a7",
143        "MSRValue": "0x3FBFC00002",
144        "SampleAfterValue": "100003",
145        "UMask": "0x1",
146        "Unit": "cpu_core"
147    }
148]
149