1[
2    {
3        "BriefDescription": "Counts cacheable demand data reads were not supplied by the L3 cache.",
4        "Counter": "0,1,2,3,4,5,6,7",
5        "EventCode": "0xB7",
6        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
7        "MSRIndex": "0x1a6,0x1a7",
8        "MSRValue": "0x3FBFC00001",
9        "SampleAfterValue": "100003",
10        "UMask": "0x1",
11        "Unit": "cpu_atom"
12    },
13    {
14        "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO were not supplied by the L3 cache.",
15        "Counter": "0,1,2,3,4,5,6,7",
16        "EventCode": "0xB7",
17        "EventName": "OCR.DEMAND_RFO.L3_MISS",
18        "MSRIndex": "0x1a6,0x1a7",
19        "MSRValue": "0x3FBFC00002",
20        "SampleAfterValue": "100003",
21        "UMask": "0x1",
22        "Unit": "cpu_atom"
23    },
24    {
25        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
26        "CollectPEBSRecord": "2",
27        "Counter": "1,2,3,4,5,6,7",
28        "Data_LA": "1",
29        "EventCode": "0xcd",
30        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
31        "MSRIndex": "0x3F6",
32        "MSRValue": "0x80",
33        "PEBS": "2",
34        "PEBScounters": "1,2,3,4,5,6,7",
35        "SampleAfterValue": "1009",
36        "TakenAlone": "1",
37        "UMask": "0x1",
38        "Unit": "cpu_core"
39    },
40    {
41        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
42        "CollectPEBSRecord": "2",
43        "Counter": "1,2,3,4,5,6,7",
44        "Data_LA": "1",
45        "EventCode": "0xcd",
46        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
47        "MSRIndex": "0x3F6",
48        "MSRValue": "0x10",
49        "PEBS": "2",
50        "PEBScounters": "1,2,3,4,5,6,7",
51        "SampleAfterValue": "20011",
52        "TakenAlone": "1",
53        "UMask": "0x1",
54        "Unit": "cpu_core"
55    },
56    {
57        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
58        "CollectPEBSRecord": "2",
59        "Counter": "1,2,3,4,5,6,7",
60        "Data_LA": "1",
61        "EventCode": "0xcd",
62        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
63        "MSRIndex": "0x3F6",
64        "MSRValue": "0x100",
65        "PEBS": "2",
66        "PEBScounters": "1,2,3,4,5,6,7",
67        "SampleAfterValue": "503",
68        "TakenAlone": "1",
69        "UMask": "0x1",
70        "Unit": "cpu_core"
71    },
72    {
73        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
74        "CollectPEBSRecord": "2",
75        "Counter": "1,2,3,4,5,6,7",
76        "Data_LA": "1",
77        "EventCode": "0xcd",
78        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
79        "MSRIndex": "0x3F6",
80        "MSRValue": "0x20",
81        "PEBS": "2",
82        "PEBScounters": "1,2,3,4,5,6,7",
83        "SampleAfterValue": "100007",
84        "TakenAlone": "1",
85        "UMask": "0x1",
86        "Unit": "cpu_core"
87    },
88    {
89        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
90        "CollectPEBSRecord": "2",
91        "Counter": "1,2,3,4,5,6,7",
92        "Data_LA": "1",
93        "EventCode": "0xcd",
94        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
95        "MSRIndex": "0x3F6",
96        "MSRValue": "0x4",
97        "PEBS": "2",
98        "PEBScounters": "1,2,3,4,5,6,7",
99        "SampleAfterValue": "100003",
100        "TakenAlone": "1",
101        "UMask": "0x1",
102        "Unit": "cpu_core"
103    },
104    {
105        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
106        "CollectPEBSRecord": "2",
107        "Counter": "1,2,3,4,5,6,7",
108        "Data_LA": "1",
109        "EventCode": "0xcd",
110        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
111        "MSRIndex": "0x3F6",
112        "MSRValue": "0x200",
113        "PEBS": "2",
114        "PEBScounters": "1,2,3,4,5,6,7",
115        "SampleAfterValue": "101",
116        "TakenAlone": "1",
117        "UMask": "0x1",
118        "Unit": "cpu_core"
119    },
120    {
121        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
122        "CollectPEBSRecord": "2",
123        "Counter": "1,2,3,4,5,6,7",
124        "Data_LA": "1",
125        "EventCode": "0xcd",
126        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
127        "MSRIndex": "0x3F6",
128        "MSRValue": "0x40",
129        "PEBS": "2",
130        "PEBScounters": "1,2,3,4,5,6,7",
131        "SampleAfterValue": "2003",
132        "TakenAlone": "1",
133        "UMask": "0x1",
134        "Unit": "cpu_core"
135    },
136    {
137        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
138        "CollectPEBSRecord": "2",
139        "Counter": "1,2,3,4,5,6,7",
140        "Data_LA": "1",
141        "EventCode": "0xcd",
142        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
143        "MSRIndex": "0x3F6",
144        "MSRValue": "0x8",
145        "PEBS": "2",
146        "PEBScounters": "1,2,3,4,5,6,7",
147        "SampleAfterValue": "50021",
148        "TakenAlone": "1",
149        "UMask": "0x1",
150        "Unit": "cpu_core"
151    },
152    {
153        "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.",
154        "CollectPEBSRecord": "2",
155        "Data_LA": "1",
156        "EventCode": "0xcd",
157        "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE",
158        "PEBS": "2",
159        "SampleAfterValue": "1000003",
160        "UMask": "0x2",
161        "Unit": "cpu_core"
162    },
163    {
164        "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
165        "Counter": "0,1,2,3,4,5,6,7",
166        "EventCode": "0x2A,0x2B",
167        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
168        "MSRIndex": "0x1a6,0x1a7",
169        "MSRValue": "0x3FBFC00001",
170        "SampleAfterValue": "100003",
171        "UMask": "0x1",
172        "Unit": "cpu_core"
173    },
174    {
175        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
176        "Counter": "0,1,2,3,4,5,6,7",
177        "EventCode": "0x2A,0x2B",
178        "EventName": "OCR.DEMAND_RFO.L3_MISS",
179        "MSRIndex": "0x1a6,0x1a7",
180        "MSRValue": "0x3FBFC00002",
181        "SampleAfterValue": "100003",
182        "UMask": "0x1",
183        "Unit": "cpu_core"
184    }
185]
186