1[
2    {
3        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
4        "Data_LA": "1",
5        "EventCode": "0xcd",
6        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
7        "MSRIndex": "0x3F6",
8        "MSRValue": "0x80",
9        "PEBS": "2",
10        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
11        "SampleAfterValue": "1009",
12        "UMask": "0x1",
13        "Unit": "cpu_core"
14    },
15    {
16        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
17        "Data_LA": "1",
18        "EventCode": "0xcd",
19        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
20        "MSRIndex": "0x3F6",
21        "MSRValue": "0x10",
22        "PEBS": "2",
23        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
24        "SampleAfterValue": "20011",
25        "UMask": "0x1",
26        "Unit": "cpu_core"
27    },
28    {
29        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
30        "Data_LA": "1",
31        "EventCode": "0xcd",
32        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
33        "MSRIndex": "0x3F6",
34        "MSRValue": "0x100",
35        "PEBS": "2",
36        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
37        "SampleAfterValue": "503",
38        "UMask": "0x1",
39        "Unit": "cpu_core"
40    },
41    {
42        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
43        "Data_LA": "1",
44        "EventCode": "0xcd",
45        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
46        "MSRIndex": "0x3F6",
47        "MSRValue": "0x20",
48        "PEBS": "2",
49        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
50        "SampleAfterValue": "100007",
51        "UMask": "0x1",
52        "Unit": "cpu_core"
53    },
54    {
55        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
56        "Data_LA": "1",
57        "EventCode": "0xcd",
58        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
59        "MSRIndex": "0x3F6",
60        "MSRValue": "0x4",
61        "PEBS": "2",
62        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
63        "SampleAfterValue": "100003",
64        "UMask": "0x1",
65        "Unit": "cpu_core"
66    },
67    {
68        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
69        "Data_LA": "1",
70        "EventCode": "0xcd",
71        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
72        "MSRIndex": "0x3F6",
73        "MSRValue": "0x200",
74        "PEBS": "2",
75        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
76        "SampleAfterValue": "101",
77        "UMask": "0x1",
78        "Unit": "cpu_core"
79    },
80    {
81        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
82        "Data_LA": "1",
83        "EventCode": "0xcd",
84        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
85        "MSRIndex": "0x3F6",
86        "MSRValue": "0x40",
87        "PEBS": "2",
88        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
89        "SampleAfterValue": "2003",
90        "UMask": "0x1",
91        "Unit": "cpu_core"
92    },
93    {
94        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
95        "Data_LA": "1",
96        "EventCode": "0xcd",
97        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
98        "MSRIndex": "0x3F6",
99        "MSRValue": "0x8",
100        "PEBS": "2",
101        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
102        "SampleAfterValue": "50021",
103        "UMask": "0x1",
104        "Unit": "cpu_core"
105    },
106    {
107        "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.",
108        "Data_LA": "1",
109        "EventCode": "0xcd",
110        "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE",
111        "PEBS": "2",
112        "PublicDescription": "Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8",
113        "SampleAfterValue": "1000003",
114        "UMask": "0x2",
115        "Unit": "cpu_core"
116    },
117    {
118        "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
119        "EventCode": "0xB7",
120        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
121        "MSRIndex": "0x1a6,0x1a7",
122        "MSRValue": "0x3FBFC00001",
123        "SampleAfterValue": "100003",
124        "UMask": "0x1",
125        "Unit": "cpu_atom"
126    },
127    {
128        "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
129        "EventCode": "0x2A,0x2B",
130        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
131        "MSRIndex": "0x1a6,0x1a7",
132        "MSRValue": "0x3FBFC00001",
133        "SampleAfterValue": "100003",
134        "UMask": "0x1",
135        "Unit": "cpu_core"
136    },
137    {
138        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
139        "EventCode": "0xB7",
140        "EventName": "OCR.DEMAND_RFO.L3_MISS",
141        "MSRIndex": "0x1a6,0x1a7",
142        "MSRValue": "0x3FBFC00002",
143        "SampleAfterValue": "100003",
144        "UMask": "0x1",
145        "Unit": "cpu_atom"
146    },
147    {
148        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
149        "EventCode": "0x2A,0x2B",
150        "EventName": "OCR.DEMAND_RFO.L3_MISS",
151        "MSRIndex": "0x1a6,0x1a7",
152        "MSRValue": "0x3FBFC00002",
153        "SampleAfterValue": "100003",
154        "UMask": "0x1",
155        "Unit": "cpu_core"
156    }
157]
158