1[
2    {
3        "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.",
4        "EventCode": "0x80",
5        "EventName": "ICACHE.ACCESSES",
6        "SampleAfterValue": "200003",
7        "UMask": "0x3",
8        "Unit": "cpu_atom"
9    },
10    {
11        "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -",
12        "EventCode": "0x80",
13        "EventName": "ICACHE.MISSES",
14        "SampleAfterValue": "200003",
15        "UMask": "0x2",
16        "Unit": "cpu_atom"
17    },
18    {
19        "BriefDescription": "This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.",
20        "EventCode": "0x9c",
21        "EventName": "IDQ_BUBBLES.CORE",
22        "PublicDescription": "This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.\nThe count may be distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.",
23        "SampleAfterValue": "1000003",
24        "UMask": "0x1",
25        "Unit": "cpu_core"
26    }
27]
28