1[
2    {
3        "BriefDescription": "L2 code requests",
4        "EventCode": "0x24",
5        "EventName": "L2_RQSTS.ALL_CODE_RD",
6        "SampleAfterValue": "200003",
7        "UMask": "0xe4",
8        "Unit": "cpu_core"
9    },
10    {
11        "BriefDescription": "Demand Data Read access L2 cache",
12        "EventCode": "0x24",
13        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
14        "SampleAfterValue": "200003",
15        "UMask": "0xe1",
16        "Unit": "cpu_core"
17    },
18    {
19        "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
20        "EventCode": "0x2e",
21        "EventName": "LONGEST_LAT_CACHE.MISS",
22        "SampleAfterValue": "200003",
23        "UMask": "0x41",
24        "Unit": "cpu_atom"
25    },
26    {
27        "BriefDescription": "Core-originated cacheable requests that missed L3  (Except hardware prefetches to the L3)",
28        "EventCode": "0x2e",
29        "EventName": "LONGEST_LAT_CACHE.MISS",
30        "SampleAfterValue": "100003",
31        "UMask": "0x41",
32        "Unit": "cpu_core"
33    },
34    {
35        "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
36        "EventCode": "0x2e",
37        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
38        "SampleAfterValue": "200003",
39        "UMask": "0x4f",
40        "Unit": "cpu_atom"
41    },
42    {
43        "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
44        "EventCode": "0x2e",
45        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
46        "SampleAfterValue": "100003",
47        "UMask": "0x4f",
48        "Unit": "cpu_core"
49    },
50    {
51        "BriefDescription": "Retired load instructions.",
52        "Data_LA": "1",
53        "EventCode": "0xd0",
54        "EventName": "MEM_INST_RETIRED.ALL_LOADS",
55        "PEBS": "1",
56        "SampleAfterValue": "1000003",
57        "UMask": "0x81",
58        "Unit": "cpu_core"
59    },
60    {
61        "BriefDescription": "Retired store instructions.",
62        "Data_LA": "1",
63        "EventCode": "0xd0",
64        "EventName": "MEM_INST_RETIRED.ALL_STORES",
65        "PEBS": "1",
66        "SampleAfterValue": "1000003",
67        "UMask": "0x82",
68        "Unit": "cpu_core"
69    },
70    {
71        "BriefDescription": "Counts the number of load ops retired.",
72        "Data_LA": "1",
73        "EventCode": "0xd0",
74        "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
75        "PEBS": "1",
76        "SampleAfterValue": "200003",
77        "UMask": "0x81",
78        "Unit": "cpu_atom"
79    },
80    {
81        "BriefDescription": "Counts the number of store ops retired.",
82        "Data_LA": "1",
83        "EventCode": "0xd0",
84        "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
85        "PEBS": "1",
86        "SampleAfterValue": "200003",
87        "UMask": "0x82",
88        "Unit": "cpu_atom"
89    },
90    {
91        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
92        "Data_LA": "1",
93        "EventCode": "0xd0",
94        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
95        "MSRIndex": "0x3F6",
96        "MSRValue": "0x80",
97        "PEBS": "2",
98        "SampleAfterValue": "1000003",
99        "UMask": "0x5",
100        "Unit": "cpu_atom"
101    },
102    {
103        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
104        "Data_LA": "1",
105        "EventCode": "0xd0",
106        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
107        "MSRIndex": "0x3F6",
108        "MSRValue": "0x10",
109        "PEBS": "2",
110        "SampleAfterValue": "1000003",
111        "UMask": "0x5",
112        "Unit": "cpu_atom"
113    },
114    {
115        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
116        "Data_LA": "1",
117        "EventCode": "0xd0",
118        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
119        "MSRIndex": "0x3F6",
120        "MSRValue": "0x100",
121        "PEBS": "2",
122        "SampleAfterValue": "1000003",
123        "UMask": "0x5",
124        "Unit": "cpu_atom"
125    },
126    {
127        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
128        "Data_LA": "1",
129        "EventCode": "0xd0",
130        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
131        "MSRIndex": "0x3F6",
132        "MSRValue": "0x20",
133        "PEBS": "2",
134        "SampleAfterValue": "1000003",
135        "UMask": "0x5",
136        "Unit": "cpu_atom"
137    },
138    {
139        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
140        "Data_LA": "1",
141        "EventCode": "0xd0",
142        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
143        "MSRIndex": "0x3F6",
144        "MSRValue": "0x4",
145        "PEBS": "2",
146        "SampleAfterValue": "1000003",
147        "UMask": "0x5",
148        "Unit": "cpu_atom"
149    },
150    {
151        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
152        "Data_LA": "1",
153        "EventCode": "0xd0",
154        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
155        "MSRIndex": "0x3F6",
156        "MSRValue": "0x200",
157        "PEBS": "2",
158        "SampleAfterValue": "1000003",
159        "UMask": "0x5",
160        "Unit": "cpu_atom"
161    },
162    {
163        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
164        "Data_LA": "1",
165        "EventCode": "0xd0",
166        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
167        "MSRIndex": "0x3F6",
168        "MSRValue": "0x40",
169        "PEBS": "2",
170        "SampleAfterValue": "1000003",
171        "UMask": "0x5",
172        "Unit": "cpu_atom"
173    },
174    {
175        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
176        "Data_LA": "1",
177        "EventCode": "0xd0",
178        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
179        "MSRIndex": "0x3F6",
180        "MSRValue": "0x8",
181        "PEBS": "2",
182        "SampleAfterValue": "1000003",
183        "UMask": "0x5",
184        "Unit": "cpu_atom"
185    },
186    {
187        "BriefDescription": "Counts the number of  stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
188        "Data_LA": "1",
189        "EventCode": "0xd0",
190        "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
191        "PEBS": "2",
192        "SampleAfterValue": "1000003",
193        "UMask": "0x6",
194        "Unit": "cpu_atom"
195    }
196]
197