11ab4ef06SIan Rogers[ 21ab4ef06SIan Rogers { 31ab4ef06SIan Rogers "BriefDescription": "L2 code requests", 41ab4ef06SIan Rogers "EventCode": "0x24", 51ab4ef06SIan Rogers "EventName": "L2_RQSTS.ALL_CODE_RD", 61ab4ef06SIan Rogers "SampleAfterValue": "200003", 71ab4ef06SIan Rogers "UMask": "0xe4", 81ab4ef06SIan Rogers "Unit": "cpu_core" 91ab4ef06SIan Rogers }, 101ab4ef06SIan Rogers { 111ab4ef06SIan Rogers "BriefDescription": "Demand Data Read access L2 cache", 121ab4ef06SIan Rogers "EventCode": "0x24", 131ab4ef06SIan Rogers "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", 141ab4ef06SIan Rogers "SampleAfterValue": "200003", 151ab4ef06SIan Rogers "UMask": "0xe1", 161ab4ef06SIan Rogers "Unit": "cpu_core" 171ab4ef06SIan Rogers }, 181ab4ef06SIan Rogers { 19*5362e4d1SIan Rogers "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.", 201ab4ef06SIan Rogers "EventCode": "0x2e", 211ab4ef06SIan Rogers "EventName": "LONGEST_LAT_CACHE.MISS", 22*5362e4d1SIan Rogers "SampleAfterValue": "200003", 23*5362e4d1SIan Rogers "UMask": "0x41", 24*5362e4d1SIan Rogers "Unit": "cpu_atom" 25*5362e4d1SIan Rogers }, 26*5362e4d1SIan Rogers { 27*5362e4d1SIan Rogers "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", 28*5362e4d1SIan Rogers "EventCode": "0x2e", 29*5362e4d1SIan Rogers "EventName": "LONGEST_LAT_CACHE.MISS", 301ab4ef06SIan Rogers "SampleAfterValue": "100003", 311ab4ef06SIan Rogers "UMask": "0x41", 321ab4ef06SIan Rogers "Unit": "cpu_core" 331ab4ef06SIan Rogers }, 341ab4ef06SIan Rogers { 35*5362e4d1SIan Rogers "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.", 361ab4ef06SIan Rogers "EventCode": "0x2e", 371ab4ef06SIan Rogers "EventName": "LONGEST_LAT_CACHE.REFERENCE", 38*5362e4d1SIan Rogers "SampleAfterValue": "200003", 39*5362e4d1SIan Rogers "UMask": "0x4f", 40*5362e4d1SIan Rogers "Unit": "cpu_atom" 41*5362e4d1SIan Rogers }, 42*5362e4d1SIan Rogers { 43*5362e4d1SIan Rogers "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)", 44*5362e4d1SIan Rogers "EventCode": "0x2e", 45*5362e4d1SIan Rogers "EventName": "LONGEST_LAT_CACHE.REFERENCE", 461ab4ef06SIan Rogers "SampleAfterValue": "100003", 471ab4ef06SIan Rogers "UMask": "0x4f", 481ab4ef06SIan Rogers "Unit": "cpu_core" 491ab4ef06SIan Rogers }, 501ab4ef06SIan Rogers { 511ab4ef06SIan Rogers "BriefDescription": "Retired load instructions.", 521ab4ef06SIan Rogers "Data_LA": "1", 531ab4ef06SIan Rogers "EventCode": "0xd0", 541ab4ef06SIan Rogers "EventName": "MEM_INST_RETIRED.ALL_LOADS", 551ab4ef06SIan Rogers "PEBS": "1", 561ab4ef06SIan Rogers "SampleAfterValue": "1000003", 571ab4ef06SIan Rogers "UMask": "0x81", 581ab4ef06SIan Rogers "Unit": "cpu_core" 591ab4ef06SIan Rogers }, 601ab4ef06SIan Rogers { 611ab4ef06SIan Rogers "BriefDescription": "Retired store instructions.", 621ab4ef06SIan Rogers "Data_LA": "1", 631ab4ef06SIan Rogers "EventCode": "0xd0", 641ab4ef06SIan Rogers "EventName": "MEM_INST_RETIRED.ALL_STORES", 651ab4ef06SIan Rogers "PEBS": "1", 661ab4ef06SIan Rogers "SampleAfterValue": "1000003", 671ab4ef06SIan Rogers "UMask": "0x82", 681ab4ef06SIan Rogers "Unit": "cpu_core" 69*5362e4d1SIan Rogers }, 70*5362e4d1SIan Rogers { 71*5362e4d1SIan Rogers "BriefDescription": "Counts the number of load ops retired.", 72*5362e4d1SIan Rogers "Data_LA": "1", 73*5362e4d1SIan Rogers "EventCode": "0xd0", 74*5362e4d1SIan Rogers "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", 75*5362e4d1SIan Rogers "PEBS": "1", 76*5362e4d1SIan Rogers "SampleAfterValue": "200003", 77*5362e4d1SIan Rogers "UMask": "0x81", 78*5362e4d1SIan Rogers "Unit": "cpu_atom" 79*5362e4d1SIan Rogers }, 80*5362e4d1SIan Rogers { 81*5362e4d1SIan Rogers "BriefDescription": "Counts the number of store ops retired.", 82*5362e4d1SIan Rogers "Data_LA": "1", 83*5362e4d1SIan Rogers "EventCode": "0xd0", 84*5362e4d1SIan Rogers "EventName": "MEM_UOPS_RETIRED.ALL_STORES", 85*5362e4d1SIan Rogers "PEBS": "1", 86*5362e4d1SIan Rogers "SampleAfterValue": "200003", 87*5362e4d1SIan Rogers "UMask": "0x82", 88*5362e4d1SIan Rogers "Unit": "cpu_atom" 89*5362e4d1SIan Rogers }, 90*5362e4d1SIan Rogers { 91*5362e4d1SIan Rogers "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", 92*5362e4d1SIan Rogers "Data_LA": "1", 93*5362e4d1SIan Rogers "EventCode": "0xd0", 94*5362e4d1SIan Rogers "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", 95*5362e4d1SIan Rogers "MSRIndex": "0x3F6", 96*5362e4d1SIan Rogers "MSRValue": "0x80", 97*5362e4d1SIan Rogers "PEBS": "2", 98*5362e4d1SIan Rogers "SampleAfterValue": "1000003", 99*5362e4d1SIan Rogers "UMask": "0x5", 100*5362e4d1SIan Rogers "Unit": "cpu_atom" 101*5362e4d1SIan Rogers }, 102*5362e4d1SIan Rogers { 103*5362e4d1SIan Rogers "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", 104*5362e4d1SIan Rogers "Data_LA": "1", 105*5362e4d1SIan Rogers "EventCode": "0xd0", 106*5362e4d1SIan Rogers "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", 107*5362e4d1SIan Rogers "MSRIndex": "0x3F6", 108*5362e4d1SIan Rogers "MSRValue": "0x10", 109*5362e4d1SIan Rogers "PEBS": "2", 110*5362e4d1SIan Rogers "SampleAfterValue": "1000003", 111*5362e4d1SIan Rogers "UMask": "0x5", 112*5362e4d1SIan Rogers "Unit": "cpu_atom" 113*5362e4d1SIan Rogers }, 114*5362e4d1SIan Rogers { 115*5362e4d1SIan Rogers "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", 116*5362e4d1SIan Rogers "Data_LA": "1", 117*5362e4d1SIan Rogers "EventCode": "0xd0", 118*5362e4d1SIan Rogers "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", 119*5362e4d1SIan Rogers "MSRIndex": "0x3F6", 120*5362e4d1SIan Rogers "MSRValue": "0x100", 121*5362e4d1SIan Rogers "PEBS": "2", 122*5362e4d1SIan Rogers "SampleAfterValue": "1000003", 123*5362e4d1SIan Rogers "UMask": "0x5", 124*5362e4d1SIan Rogers "Unit": "cpu_atom" 125*5362e4d1SIan Rogers }, 126*5362e4d1SIan Rogers { 127*5362e4d1SIan Rogers "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", 128*5362e4d1SIan Rogers "Data_LA": "1", 129*5362e4d1SIan Rogers "EventCode": "0xd0", 130*5362e4d1SIan Rogers "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", 131*5362e4d1SIan Rogers "MSRIndex": "0x3F6", 132*5362e4d1SIan Rogers "MSRValue": "0x20", 133*5362e4d1SIan Rogers "PEBS": "2", 134*5362e4d1SIan Rogers "SampleAfterValue": "1000003", 135*5362e4d1SIan Rogers "UMask": "0x5", 136*5362e4d1SIan Rogers "Unit": "cpu_atom" 137*5362e4d1SIan Rogers }, 138*5362e4d1SIan Rogers { 139*5362e4d1SIan Rogers "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", 140*5362e4d1SIan Rogers "Data_LA": "1", 141*5362e4d1SIan Rogers "EventCode": "0xd0", 142*5362e4d1SIan Rogers "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", 143*5362e4d1SIan Rogers "MSRIndex": "0x3F6", 144*5362e4d1SIan Rogers "MSRValue": "0x4", 145*5362e4d1SIan Rogers "PEBS": "2", 146*5362e4d1SIan Rogers "SampleAfterValue": "1000003", 147*5362e4d1SIan Rogers "UMask": "0x5", 148*5362e4d1SIan Rogers "Unit": "cpu_atom" 149*5362e4d1SIan Rogers }, 150*5362e4d1SIan Rogers { 151*5362e4d1SIan Rogers "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", 152*5362e4d1SIan Rogers "Data_LA": "1", 153*5362e4d1SIan Rogers "EventCode": "0xd0", 154*5362e4d1SIan Rogers "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", 155*5362e4d1SIan Rogers "MSRIndex": "0x3F6", 156*5362e4d1SIan Rogers "MSRValue": "0x200", 157*5362e4d1SIan Rogers "PEBS": "2", 158*5362e4d1SIan Rogers "SampleAfterValue": "1000003", 159*5362e4d1SIan Rogers "UMask": "0x5", 160*5362e4d1SIan Rogers "Unit": "cpu_atom" 161*5362e4d1SIan Rogers }, 162*5362e4d1SIan Rogers { 163*5362e4d1SIan Rogers "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", 164*5362e4d1SIan Rogers "Data_LA": "1", 165*5362e4d1SIan Rogers "EventCode": "0xd0", 166*5362e4d1SIan Rogers "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", 167*5362e4d1SIan Rogers "MSRIndex": "0x3F6", 168*5362e4d1SIan Rogers "MSRValue": "0x40", 169*5362e4d1SIan Rogers "PEBS": "2", 170*5362e4d1SIan Rogers "SampleAfterValue": "1000003", 171*5362e4d1SIan Rogers "UMask": "0x5", 172*5362e4d1SIan Rogers "Unit": "cpu_atom" 173*5362e4d1SIan Rogers }, 174*5362e4d1SIan Rogers { 175*5362e4d1SIan Rogers "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", 176*5362e4d1SIan Rogers "Data_LA": "1", 177*5362e4d1SIan Rogers "EventCode": "0xd0", 178*5362e4d1SIan Rogers "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", 179*5362e4d1SIan Rogers "MSRIndex": "0x3F6", 180*5362e4d1SIan Rogers "MSRValue": "0x8", 181*5362e4d1SIan Rogers "PEBS": "2", 182*5362e4d1SIan Rogers "SampleAfterValue": "1000003", 183*5362e4d1SIan Rogers "UMask": "0x5", 184*5362e4d1SIan Rogers "Unit": "cpu_atom" 185*5362e4d1SIan Rogers }, 186*5362e4d1SIan Rogers { 187*5362e4d1SIan Rogers "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES", 188*5362e4d1SIan Rogers "Data_LA": "1", 189*5362e4d1SIan Rogers "EventCode": "0xd0", 190*5362e4d1SIan Rogers "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", 191*5362e4d1SIan Rogers "PEBS": "2", 192*5362e4d1SIan Rogers "SampleAfterValue": "1000003", 193*5362e4d1SIan Rogers "UMask": "0x6", 194*5362e4d1SIan Rogers "Unit": "cpu_atom" 1951ab4ef06SIan Rogers } 1961ab4ef06SIan Rogers] 197