1[
2    {
3        "BriefDescription": "Counts the number of times the machine clears due to memory ordering hazards",
4        "EventCode": "0xC3",
5        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
6        "SampleAfterValue": "200003",
7        "UMask": "0x2"
8    },
9    {
10        "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for responses from DDR (local and far)",
11        "EventCode": "0xB7",
12        "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR",
13        "MSRIndex": "0x1a6,0x1a7",
14        "MSRValue": "0x0181800044",
15        "SampleAfterValue": "100007",
16        "UMask": "0x1"
17    },
18    {
19        "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for data responses from DRAM Far.",
20        "EventCode": "0xB7",
21        "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_FAR",
22        "MSRIndex": "0x1a6,0x1a7",
23        "MSRValue": "0x0101000044",
24        "SampleAfterValue": "100007",
25        "UMask": "0x1"
26    },
27    {
28        "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for data responses from DRAM Local.",
29        "EventCode": "0xB7",
30        "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_NEAR",
31        "MSRIndex": "0x1a6,0x1a7",
32        "MSRValue": "0x0080800044",
33        "SampleAfterValue": "100007",
34        "UMask": "0x1"
35    },
36    {
37        "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for responses from MCDRAM (local and far)",
38        "EventCode": "0xB7",
39        "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM",
40        "MSRIndex": "0x1a6,0x1a7",
41        "MSRValue": "0x0180600044",
42        "SampleAfterValue": "100007",
43        "UMask": "0x1"
44    },
45    {
46        "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
47        "EventCode": "0xB7",
48        "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_FAR",
49        "MSRIndex": "0x1a6,0x1a7",
50        "MSRValue": "0x0100400044",
51        "SampleAfterValue": "100007",
52        "UMask": "0x1"
53    },
54    {
55        "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for data responses from MCDRAM Local.",
56        "EventCode": "0xB7",
57        "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_NEAR",
58        "MSRIndex": "0x1a6,0x1a7",
59        "MSRValue": "0x0080200044",
60        "SampleAfterValue": "100007",
61        "UMask": "0x1"
62    },
63    {
64        "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from DDR (local and far)",
65        "EventCode": "0xB7",
66        "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR",
67        "MSRIndex": "0x1a6,0x1a7",
68        "MSRValue": "0x0181803091",
69        "SampleAfterValue": "100007",
70        "UMask": "0x1"
71    },
72    {
73        "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from DRAM Far.",
74        "EventCode": "0xB7",
75        "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_FAR",
76        "MSRIndex": "0x1a6,0x1a7",
77        "MSRValue": "0x0101003091",
78        "SampleAfterValue": "100007",
79        "UMask": "0x1"
80    },
81    {
82        "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from DRAM Local.",
83        "EventCode": "0xB7",
84        "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_NEAR",
85        "MSRIndex": "0x1a6,0x1a7",
86        "MSRValue": "0x0080803091",
87        "SampleAfterValue": "100007",
88        "UMask": "0x1"
89    },
90    {
91        "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from MCDRAM (local and far)",
92        "EventCode": "0xB7",
93        "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM",
94        "MSRIndex": "0x1a6,0x1a7",
95        "MSRValue": "0x0180603091",
96        "SampleAfterValue": "100007",
97        "UMask": "0x1"
98    },
99    {
100        "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
101        "EventCode": "0xB7",
102        "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_FAR",
103        "MSRIndex": "0x1a6,0x1a7",
104        "MSRValue": "0x0100403091",
105        "SampleAfterValue": "100007",
106        "UMask": "0x1"
107    },
108    {
109        "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from MCDRAM Local.",
110        "EventCode": "0xB7",
111        "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_NEAR",
112        "MSRIndex": "0x1a6,0x1a7",
113        "MSRValue": "0x0080203091",
114        "SampleAfterValue": "100007",
115        "UMask": "0x1"
116    },
117    {
118        "BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Far.",
119        "EventCode": "0xB7",
120        "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_FAR",
121        "MSRIndex": "0x1a6,0x1a7",
122        "MSRValue": "0x0101000070",
123        "SampleAfterValue": "100007",
124        "UMask": "0x1"
125    },
126    {
127        "BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Local.",
128        "EventCode": "0xB7",
129        "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_NEAR",
130        "MSRIndex": "0x1a6,0x1a7",
131        "MSRValue": "0x0080800070",
132        "SampleAfterValue": "100007",
133        "UMask": "0x1"
134    },
135    {
136        "BriefDescription": "Counts any Prefetch requests that accounts for responses from MCDRAM (local and far)",
137        "EventCode": "0xB7",
138        "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM",
139        "MSRIndex": "0x1a6,0x1a7",
140        "MSRValue": "0x0180600070",
141        "SampleAfterValue": "100007",
142        "UMask": "0x1"
143    },
144    {
145        "BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
146        "EventCode": "0xB7",
147        "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_FAR",
148        "MSRIndex": "0x1a6,0x1a7",
149        "MSRValue": "0x0100400070",
150        "SampleAfterValue": "100007",
151        "UMask": "0x1"
152    },
153    {
154        "BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Local.",
155        "EventCode": "0xB7",
156        "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_NEAR",
157        "MSRIndex": "0x1a6,0x1a7",
158        "MSRValue": "0x0080200070",
159        "SampleAfterValue": "100007",
160        "UMask": "0x1"
161    },
162    {
163        "BriefDescription": "Counts any Read request  that accounts for responses from DDR (local and far)",
164        "EventCode": "0xB7",
165        "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR",
166        "MSRIndex": "0x1a6,0x1a7",
167        "MSRValue": "0x01818032f7",
168        "SampleAfterValue": "100007",
169        "UMask": "0x1"
170    },
171    {
172        "BriefDescription": "Counts any Read request  that accounts for data responses from DRAM Far.",
173        "EventCode": "0xB7",
174        "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_FAR",
175        "MSRIndex": "0x1a6,0x1a7",
176        "MSRValue": "0x01010032f7",
177        "SampleAfterValue": "100007",
178        "UMask": "0x1"
179    },
180    {
181        "BriefDescription": "Counts any Read request  that accounts for data responses from DRAM Local.",
182        "EventCode": "0xB7",
183        "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_NEAR",
184        "MSRIndex": "0x1a6,0x1a7",
185        "MSRValue": "0x00808032f7",
186        "SampleAfterValue": "100007",
187        "UMask": "0x1"
188    },
189    {
190        "BriefDescription": "Counts any Read request  that accounts for responses from MCDRAM (local and far)",
191        "EventCode": "0xB7",
192        "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM",
193        "MSRIndex": "0x1a6,0x1a7",
194        "MSRValue": "0x01806032f7",
195        "SampleAfterValue": "100007",
196        "UMask": "0x1"
197    },
198    {
199        "BriefDescription": "Counts any Read request  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
200        "EventCode": "0xB7",
201        "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_FAR",
202        "MSRIndex": "0x1a6,0x1a7",
203        "MSRValue": "0x01004032f7",
204        "SampleAfterValue": "100007",
205        "UMask": "0x1"
206    },
207    {
208        "BriefDescription": "Counts any Read request  that accounts for data responses from MCDRAM Local.",
209        "EventCode": "0xB7",
210        "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_NEAR",
211        "MSRIndex": "0x1a6,0x1a7",
212        "MSRValue": "0x00802032f7",
213        "SampleAfterValue": "100007",
214        "UMask": "0x1"
215    },
216    {
217        "BriefDescription": "Counts any request that accounts for responses from DDR (local and far)",
218        "EventCode": "0xB7",
219        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR",
220        "MSRIndex": "0x1a6,0x1a7",
221        "MSRValue": "0x0181808000",
222        "SampleAfterValue": "100007",
223        "UMask": "0x1"
224    },
225    {
226        "BriefDescription": "Counts any request that accounts for data responses from DRAM Far.",
227        "EventCode": "0xB7",
228        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_FAR",
229        "MSRIndex": "0x1a6,0x1a7",
230        "MSRValue": "0x0101008000",
231        "SampleAfterValue": "100007",
232        "UMask": "0x1"
233    },
234    {
235        "BriefDescription": "Counts any request that accounts for data responses from DRAM Local.",
236        "EventCode": "0xB7",
237        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_NEAR",
238        "MSRIndex": "0x1a6,0x1a7",
239        "MSRValue": "0x0080808000",
240        "SampleAfterValue": "100007",
241        "UMask": "0x1"
242    },
243    {
244        "BriefDescription": "Counts any request that accounts for responses from MCDRAM (local and far)",
245        "EventCode": "0xB7",
246        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM",
247        "MSRIndex": "0x1a6,0x1a7",
248        "MSRValue": "0x0180608000",
249        "SampleAfterValue": "100007",
250        "UMask": "0x1"
251    },
252    {
253        "BriefDescription": "Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
254        "EventCode": "0xB7",
255        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_FAR",
256        "MSRIndex": "0x1a6,0x1a7",
257        "MSRValue": "0x0100408000",
258        "SampleAfterValue": "100007",
259        "UMask": "0x1"
260    },
261    {
262        "BriefDescription": "Counts any request that accounts for data responses from MCDRAM Local.",
263        "EventCode": "0xB7",
264        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_NEAR",
265        "MSRIndex": "0x1a6,0x1a7",
266        "MSRValue": "0x0080208000",
267        "SampleAfterValue": "100007",
268        "UMask": "0x1"
269    },
270    {
271        "BriefDescription": "Counts Demand cacheable data write requests  that accounts for responses from DDR (local and far)",
272        "EventCode": "0xB7",
273        "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR",
274        "MSRIndex": "0x1a6,0x1a7",
275        "MSRValue": "0x0181800022",
276        "SampleAfterValue": "100007",
277        "UMask": "0x1"
278    },
279    {
280        "BriefDescription": "Counts Demand cacheable data write requests  that accounts for data responses from DRAM Far.",
281        "EventCode": "0xB7",
282        "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_FAR",
283        "MSRIndex": "0x1a6,0x1a7",
284        "MSRValue": "0x0101000022",
285        "SampleAfterValue": "100007",
286        "UMask": "0x1"
287    },
288    {
289        "BriefDescription": "Counts Demand cacheable data write requests  that accounts for data responses from DRAM Local.",
290        "EventCode": "0xB7",
291        "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_NEAR",
292        "MSRIndex": "0x1a6,0x1a7",
293        "MSRValue": "0x0080800022",
294        "SampleAfterValue": "100007",
295        "UMask": "0x1"
296    },
297    {
298        "BriefDescription": "Counts Demand cacheable data write requests  that accounts for responses from MCDRAM (local and far)",
299        "EventCode": "0xB7",
300        "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM",
301        "MSRIndex": "0x1a6,0x1a7",
302        "MSRValue": "0x0180600022",
303        "SampleAfterValue": "100007",
304        "UMask": "0x1"
305    },
306    {
307        "BriefDescription": "Counts Demand cacheable data write requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
308        "EventCode": "0xB7",
309        "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_FAR",
310        "MSRIndex": "0x1a6,0x1a7",
311        "MSRValue": "0x0100400022",
312        "SampleAfterValue": "100007",
313        "UMask": "0x1"
314    },
315    {
316        "BriefDescription": "Counts Demand cacheable data write requests  that accounts for data responses from MCDRAM Local.",
317        "EventCode": "0xB7",
318        "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_NEAR",
319        "MSRIndex": "0x1a6,0x1a7",
320        "MSRValue": "0x0080200022",
321        "SampleAfterValue": "100007",
322        "UMask": "0x1"
323    },
324    {
325        "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from DDR (local and far)",
326        "EventCode": "0xB7",
327        "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR",
328        "MSRIndex": "0x1a6,0x1a7",
329        "MSRValue": "0x0181800400",
330        "SampleAfterValue": "100007",
331        "UMask": "0x1"
332    },
333    {
334        "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Far.",
335        "EventCode": "0xB7",
336        "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_FAR",
337        "MSRIndex": "0x1a6,0x1a7",
338        "MSRValue": "0x0101000400",
339        "SampleAfterValue": "100007",
340        "UMask": "0x1"
341    },
342    {
343        "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Local.",
344        "EventCode": "0xB7",
345        "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_NEAR",
346        "MSRIndex": "0x1a6,0x1a7",
347        "MSRValue": "0x0080800400",
348        "SampleAfterValue": "100007",
349        "UMask": "0x1"
350    },
351    {
352        "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from MCDRAM (local and far)",
353        "EventCode": "0xB7",
354        "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM",
355        "MSRIndex": "0x1a6,0x1a7",
356        "MSRValue": "0x0180600400",
357        "SampleAfterValue": "100007",
358        "UMask": "0x1"
359    },
360    {
361        "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
362        "EventCode": "0xB7",
363        "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_FAR",
364        "MSRIndex": "0x1a6,0x1a7",
365        "MSRValue": "0x0100400400",
366        "SampleAfterValue": "100007",
367        "UMask": "0x1"
368    },
369    {
370        "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Local.",
371        "EventCode": "0xB7",
372        "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_NEAR",
373        "MSRIndex": "0x1a6,0x1a7",
374        "MSRValue": "0x0080200400",
375        "SampleAfterValue": "100007",
376        "UMask": "0x1"
377    },
378    {
379        "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from DDR (local and far)",
380        "EventCode": "0xB7",
381        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR",
382        "MSRIndex": "0x1a6,0x1a7",
383        "MSRValue": "0x0181800004",
384        "SampleAfterValue": "100007",
385        "UMask": "0x1"
386    },
387    {
388        "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Far.",
389        "EventCode": "0xB7",
390        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_FAR",
391        "MSRIndex": "0x1a6,0x1a7",
392        "MSRValue": "0x0101000004",
393        "SampleAfterValue": "100007",
394        "UMask": "0x1"
395    },
396    {
397        "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Local.",
398        "EventCode": "0xB7",
399        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_NEAR",
400        "MSRIndex": "0x1a6,0x1a7",
401        "MSRValue": "0x0080800004",
402        "SampleAfterValue": "100007",
403        "UMask": "0x1"
404    },
405    {
406        "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from MCDRAM (local and far)",
407        "EventCode": "0xB7",
408        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM",
409        "MSRIndex": "0x1a6,0x1a7",
410        "MSRValue": "0x0180600004",
411        "SampleAfterValue": "100007",
412        "UMask": "0x1"
413    },
414    {
415        "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
416        "EventCode": "0xB7",
417        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_FAR",
418        "MSRIndex": "0x1a6,0x1a7",
419        "MSRValue": "0x0100400004",
420        "SampleAfterValue": "100007",
421        "UMask": "0x1"
422    },
423    {
424        "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Local.",
425        "EventCode": "0xB7",
426        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_NEAR",
427        "MSRIndex": "0x1a6,0x1a7",
428        "MSRValue": "0x0080200004",
429        "SampleAfterValue": "100007",
430        "UMask": "0x1"
431    },
432    {
433        "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from DDR (local and far)",
434        "EventCode": "0xB7",
435        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR",
436        "MSRIndex": "0x1a6,0x1a7",
437        "MSRValue": "0x0181800001",
438        "SampleAfterValue": "100007",
439        "UMask": "0x1"
440    },
441    {
442        "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Far.",
443        "EventCode": "0xB7",
444        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_FAR",
445        "MSRIndex": "0x1a6,0x1a7",
446        "MSRValue": "0x0101000001",
447        "SampleAfterValue": "100007",
448        "UMask": "0x1"
449    },
450    {
451        "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Local.",
452        "EventCode": "0xB7",
453        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_NEAR",
454        "MSRIndex": "0x1a6,0x1a7",
455        "MSRValue": "0x0080800001",
456        "SampleAfterValue": "100007",
457        "UMask": "0x1"
458    },
459    {
460        "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from MCDRAM (local and far)",
461        "EventCode": "0xB7",
462        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM",
463        "MSRIndex": "0x1a6,0x1a7",
464        "MSRValue": "0x0180600001",
465        "SampleAfterValue": "100007",
466        "UMask": "0x1"
467    },
468    {
469        "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
470        "EventCode": "0xB7",
471        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_FAR",
472        "MSRIndex": "0x1a6,0x1a7",
473        "MSRValue": "0x0100400001",
474        "SampleAfterValue": "100007",
475        "UMask": "0x1"
476    },
477    {
478        "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Local.",
479        "EventCode": "0xB7",
480        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_NEAR",
481        "MSRIndex": "0x1a6,0x1a7",
482        "MSRValue": "0x0080200001",
483        "SampleAfterValue": "100007",
484        "UMask": "0x1"
485    },
486    {
487        "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from DDR (local and far)",
488        "EventCode": "0xB7",
489        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR",
490        "MSRIndex": "0x1a6,0x1a7",
491        "MSRValue": "0x0181800002",
492        "SampleAfterValue": "100007",
493        "UMask": "0x1"
494    },
495    {
496        "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Far.",
497        "EventCode": "0xB7",
498        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_FAR",
499        "MSRIndex": "0x1a6,0x1a7",
500        "MSRValue": "0x0101000002",
501        "SampleAfterValue": "100007",
502        "UMask": "0x1"
503    },
504    {
505        "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Local.",
506        "EventCode": "0xB7",
507        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_NEAR",
508        "MSRIndex": "0x1a6,0x1a7",
509        "MSRValue": "0x0080800002",
510        "SampleAfterValue": "100007",
511        "UMask": "0x1"
512    },
513    {
514        "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from MCDRAM (local and far)",
515        "EventCode": "0xB7",
516        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM",
517        "MSRIndex": "0x1a6,0x1a7",
518        "MSRValue": "0x0180600002",
519        "SampleAfterValue": "100007",
520        "UMask": "0x1"
521    },
522    {
523        "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
524        "EventCode": "0xB7",
525        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_FAR",
526        "MSRIndex": "0x1a6,0x1a7",
527        "MSRValue": "0x0100400002",
528        "SampleAfterValue": "100007",
529        "UMask": "0x1"
530    },
531    {
532        "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Local.",
533        "EventCode": "0xB7",
534        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_NEAR",
535        "MSRIndex": "0x1a6,0x1a7",
536        "MSRValue": "0x0080200002",
537        "SampleAfterValue": "100007",
538        "UMask": "0x1"
539    },
540    {
541        "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from DDR (local and far)",
542        "EventCode": "0xB7",
543        "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR",
544        "MSRIndex": "0x1a6,0x1a7",
545        "MSRValue": "0x0181800080",
546        "SampleAfterValue": "100007",
547        "UMask": "0x1"
548    },
549    {
550        "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from DRAM Far.",
551        "EventCode": "0xB7",
552        "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_FAR",
553        "MSRIndex": "0x1a6,0x1a7",
554        "MSRValue": "0x0101000080",
555        "SampleAfterValue": "100007",
556        "UMask": "0x1"
557    },
558    {
559        "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from DRAM Local.",
560        "EventCode": "0xB7",
561        "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_NEAR",
562        "MSRIndex": "0x1a6,0x1a7",
563        "MSRValue": "0x0080800080",
564        "SampleAfterValue": "100007",
565        "UMask": "0x1"
566    },
567    {
568        "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from MCDRAM (local and far)",
569        "EventCode": "0xB7",
570        "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM",
571        "MSRIndex": "0x1a6,0x1a7",
572        "MSRValue": "0x0180600080",
573        "SampleAfterValue": "100007",
574        "UMask": "0x1"
575    },
576    {
577        "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
578        "EventCode": "0xB7",
579        "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_FAR",
580        "MSRIndex": "0x1a6,0x1a7",
581        "MSRValue": "0x0100400080",
582        "SampleAfterValue": "100007",
583        "UMask": "0x1"
584    },
585    {
586        "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from MCDRAM Local.",
587        "EventCode": "0xB7",
588        "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_NEAR",
589        "MSRIndex": "0x1a6,0x1a7",
590        "MSRValue": "0x0080200080",
591        "SampleAfterValue": "100007",
592        "UMask": "0x1"
593    },
594    {
595        "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from any NON_DRAM system address. This includes MMIO transactions",
596        "EventCode": "0xB7",
597        "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.NON_DRAM",
598        "MSRIndex": "0x1a6,0x1a7",
599        "MSRValue": "0x2000020080",
600        "SampleAfterValue": "100007",
601        "UMask": "0x1"
602    },
603    {
604        "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Far.",
605        "EventCode": "0xB7",
606        "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_FAR",
607        "MSRIndex": "0x1a7",
608        "MSRValue": "0x0101000100",
609        "SampleAfterValue": "100007",
610        "UMask": "0x1"
611    },
612    {
613        "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Local.",
614        "EventCode": "0xB7",
615        "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_NEAR",
616        "MSRIndex": "0x1a7",
617        "MSRValue": "0x0080800100",
618        "SampleAfterValue": "100007",
619        "UMask": "0x1"
620    },
621    {
622        "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from MCDRAM (local and far)",
623        "EventCode": "0xB7",
624        "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM",
625        "MSRIndex": "0x1a7",
626        "MSRValue": "0x0180600100",
627        "SampleAfterValue": "100007",
628        "UMask": "0x1"
629    },
630    {
631        "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
632        "EventCode": "0xB7",
633        "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_FAR",
634        "MSRIndex": "0x1a7",
635        "MSRValue": "0x0100400100",
636        "SampleAfterValue": "100007",
637        "UMask": "0x1"
638    },
639    {
640        "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Local.",
641        "EventCode": "0xB7",
642        "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_NEAR",
643        "MSRIndex": "0x1a7",
644        "MSRValue": "0x0080200100",
645        "SampleAfterValue": "100007",
646        "UMask": "0x1"
647    },
648    {
649        "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from DDR (local and far)",
650        "EventCode": "0xB7",
651        "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR",
652        "MSRIndex": "0x1a6,0x1a7",
653        "MSRValue": "0x0181802000",
654        "SampleAfterValue": "100007",
655        "UMask": "0x1"
656    },
657    {
658        "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Far.",
659        "EventCode": "0xB7",
660        "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_FAR",
661        "MSRIndex": "0x1a6,0x1a7",
662        "MSRValue": "0x0101002000",
663        "SampleAfterValue": "100007",
664        "UMask": "0x1"
665    },
666    {
667        "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Local.",
668        "EventCode": "0xB7",
669        "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_NEAR",
670        "MSRIndex": "0x1a6,0x1a7",
671        "MSRValue": "0x0080802000",
672        "SampleAfterValue": "100007",
673        "UMask": "0x1"
674    },
675    {
676        "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
677        "EventCode": "0xB7",
678        "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_FAR",
679        "MSRIndex": "0x1a6,0x1a7",
680        "MSRValue": "0x0100402000",
681        "SampleAfterValue": "100007",
682        "UMask": "0x1"
683    },
684    {
685        "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Local.",
686        "EventCode": "0xB7",
687        "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_NEAR",
688        "MSRIndex": "0x1a6,0x1a7",
689        "MSRValue": "0x0080202000",
690        "SampleAfterValue": "100007",
691        "UMask": "0x1"
692    },
693    {
694        "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from DDR (local and far)",
695        "EventCode": "0xB7",
696        "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR",
697        "MSRIndex": "0x1a6,0x1a7",
698        "MSRValue": "0x0181800040",
699        "SampleAfterValue": "100007",
700        "UMask": "0x1"
701    },
702    {
703        "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Far.",
704        "EventCode": "0xB7",
705        "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_FAR",
706        "MSRIndex": "0x1a6,0x1a7",
707        "MSRValue": "0x0101000040",
708        "SampleAfterValue": "100007",
709        "UMask": "0x1"
710    },
711    {
712        "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Local.",
713        "EventCode": "0xB7",
714        "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_NEAR",
715        "MSRIndex": "0x1a6,0x1a7",
716        "MSRValue": "0x0080800040",
717        "SampleAfterValue": "100007",
718        "UMask": "0x1"
719    },
720    {
721        "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
722        "EventCode": "0xB7",
723        "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_FAR",
724        "MSRIndex": "0x1a6,0x1a7",
725        "MSRValue": "0x0100400040",
726        "SampleAfterValue": "100007",
727        "UMask": "0x1"
728    },
729    {
730        "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Local.",
731        "EventCode": "0xB7",
732        "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_NEAR",
733        "MSRIndex": "0x1a6,0x1a7",
734        "MSRValue": "0x0080200040",
735        "SampleAfterValue": "100007",
736        "UMask": "0x1"
737    },
738    {
739        "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from DDR (local and far)",
740        "EventCode": "0xB7",
741        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR",
742        "MSRIndex": "0x1a6,0x1a7",
743        "MSRValue": "0x0181800020",
744        "SampleAfterValue": "100007",
745        "UMask": "0x1"
746    },
747    {
748        "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Far.",
749        "EventCode": "0xB7",
750        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_FAR",
751        "MSRIndex": "0x1a6,0x1a7",
752        "MSRValue": "0x0101000020",
753        "SampleAfterValue": "100007",
754        "UMask": "0x1"
755    },
756    {
757        "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Local.",
758        "EventCode": "0xB7",
759        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_NEAR",
760        "MSRIndex": "0x1a6,0x1a7",
761        "MSRValue": "0x0080800020",
762        "SampleAfterValue": "100007",
763        "UMask": "0x1"
764    },
765    {
766        "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from MCDRAM (local and far)",
767        "EventCode": "0xB7",
768        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM",
769        "MSRIndex": "0x1a6,0x1a7",
770        "MSRValue": "0x0180600020",
771        "SampleAfterValue": "100007",
772        "UMask": "0x1"
773    },
774    {
775        "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
776        "EventCode": "0xB7",
777        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_FAR",
778        "MSRIndex": "0x1a6,0x1a7",
779        "MSRValue": "0x0100400020",
780        "SampleAfterValue": "100007",
781        "UMask": "0x1"
782    },
783    {
784        "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Local.",
785        "EventCode": "0xB7",
786        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_NEAR",
787        "MSRIndex": "0x1a6,0x1a7",
788        "MSRValue": "0x0080200020",
789        "SampleAfterValue": "100007",
790        "UMask": "0x1"
791    },
792    {
793        "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from any NON_DRAM system address. This includes MMIO transactions",
794        "EventCode": "0xB7",
795        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.NON_DRAM",
796        "MSRIndex": "0x1a6,0x1a7",
797        "MSRValue": "0x2000020020",
798        "SampleAfterValue": "100007",
799        "UMask": "0x1"
800    },
801    {
802        "BriefDescription": "Counts Software Prefetches that accounts for responses from DDR (local and far)",
803        "EventCode": "0xB7",
804        "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR",
805        "MSRIndex": "0x1a6,0x1a7",
806        "MSRValue": "0x0181801000",
807        "SampleAfterValue": "100007",
808        "UMask": "0x1"
809    },
810    {
811        "BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Far.",
812        "EventCode": "0xB7",
813        "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_FAR",
814        "MSRIndex": "0x1a6,0x1a7",
815        "MSRValue": "0x0101001000",
816        "SampleAfterValue": "100007",
817        "UMask": "0x1"
818    },
819    {
820        "BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Local.",
821        "EventCode": "0xB7",
822        "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_NEAR",
823        "MSRIndex": "0x1a6,0x1a7",
824        "MSRValue": "0x0080801000",
825        "SampleAfterValue": "100007",
826        "UMask": "0x1"
827    },
828    {
829        "BriefDescription": "Counts Software Prefetches that accounts for responses from MCDRAM (local and far)",
830        "EventCode": "0xB7",
831        "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM",
832        "MSRIndex": "0x1a6,0x1a7",
833        "MSRValue": "0x0180601000",
834        "SampleAfterValue": "100007",
835        "UMask": "0x1"
836    },
837    {
838        "BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
839        "EventCode": "0xB7",
840        "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_FAR",
841        "MSRIndex": "0x1a6,0x1a7",
842        "MSRValue": "0x0100401000",
843        "SampleAfterValue": "100007",
844        "UMask": "0x1"
845    },
846    {
847        "BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Local.",
848        "EventCode": "0xB7",
849        "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_NEAR",
850        "MSRIndex": "0x1a6,0x1a7",
851        "MSRValue": "0x0080201000",
852        "SampleAfterValue": "100007",
853        "UMask": "0x1"
854    },
855    {
856        "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from DDR (local and far)",
857        "EventCode": "0xB7",
858        "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR",
859        "MSRIndex": "0x1a6,0x1a7",
860        "MSRValue": "0x0181800200",
861        "SampleAfterValue": "100007",
862        "UMask": "0x1"
863    },
864    {
865        "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from DRAM Far.",
866        "EventCode": "0xB7",
867        "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_FAR",
868        "MSRIndex": "0x1a6,0x1a7",
869        "MSRValue": "0x0101000200",
870        "SampleAfterValue": "100007",
871        "UMask": "0x1"
872    },
873    {
874        "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from DRAM Local.",
875        "EventCode": "0xB7",
876        "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_NEAR",
877        "MSRIndex": "0x1a6,0x1a7",
878        "MSRValue": "0x0080800200",
879        "SampleAfterValue": "100007",
880        "UMask": "0x1"
881    },
882    {
883        "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from MCDRAM (local and far)",
884        "EventCode": "0xB7",
885        "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM",
886        "MSRIndex": "0x1a6,0x1a7",
887        "MSRValue": "0x0180600200",
888        "SampleAfterValue": "100007",
889        "UMask": "0x1"
890    },
891    {
892        "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
893        "EventCode": "0xB7",
894        "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_FAR",
895        "MSRIndex": "0x1a6,0x1a7",
896        "MSRValue": "0x0100400200",
897        "SampleAfterValue": "100007",
898        "UMask": "0x1"
899    },
900    {
901        "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from MCDRAM Local.",
902        "EventCode": "0xB7",
903        "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_NEAR",
904        "MSRIndex": "0x1a6,0x1a7",
905        "MSRValue": "0x0080200200",
906        "SampleAfterValue": "100007",
907        "UMask": "0x1"
908    }
909]
910