155d42d27SAndi Kleen[ 255d42d27SAndi Kleen { 3*ff3d02b2SIan Rogers "BriefDescription": "Counts the number of times the machine clears due to memory ordering hazards", 4*ff3d02b2SIan Rogers "EventCode": "0xC3", 555d42d27SAndi Kleen "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 655d42d27SAndi Kleen "SampleAfterValue": "200003", 7*ff3d02b2SIan Rogers "UMask": "0x2" 855d42d27SAndi Kleen }, 955d42d27SAndi Kleen { 10*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from DDR (local and far)", 1155d42d27SAndi Kleen "EventCode": "0xB7", 1255d42d27SAndi Kleen "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR", 1355d42d27SAndi Kleen "MSRIndex": "0x1a6,0x1a7", 14*ff3d02b2SIan Rogers "MSRValue": "0x0181800044", 1555d42d27SAndi Kleen "SampleAfterValue": "100007", 16*ff3d02b2SIan Rogers "UMask": "0x1" 1755d42d27SAndi Kleen }, 1855d42d27SAndi Kleen { 19*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Far.", 20*ff3d02b2SIan Rogers "EventCode": "0xB7", 21*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_FAR", 22*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 23*ff3d02b2SIan Rogers "MSRValue": "0x0101000044", 24*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 25*ff3d02b2SIan Rogers "UMask": "0x1" 26*ff3d02b2SIan Rogers }, 27*ff3d02b2SIan Rogers { 28*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Local.", 29*ff3d02b2SIan Rogers "EventCode": "0xB7", 30*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_NEAR", 31*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 32*ff3d02b2SIan Rogers "MSRValue": "0x0080800044", 33*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 34*ff3d02b2SIan Rogers "UMask": "0x1" 35*ff3d02b2SIan Rogers }, 36*ff3d02b2SIan Rogers { 37*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from MCDRAM (local and far)", 38*ff3d02b2SIan Rogers "EventCode": "0xB7", 39*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM", 40*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 41*ff3d02b2SIan Rogers "MSRValue": "0x0180600044", 42*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 43*ff3d02b2SIan Rogers "UMask": "0x1" 44*ff3d02b2SIan Rogers }, 45*ff3d02b2SIan Rogers { 46*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 47*ff3d02b2SIan Rogers "EventCode": "0xB7", 48*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_FAR", 49*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 50*ff3d02b2SIan Rogers "MSRValue": "0x0100400044", 51*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 52*ff3d02b2SIan Rogers "UMask": "0x1" 53*ff3d02b2SIan Rogers }, 54*ff3d02b2SIan Rogers { 55*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Local.", 56*ff3d02b2SIan Rogers "EventCode": "0xB7", 57*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_NEAR", 58*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 59*ff3d02b2SIan Rogers "MSRValue": "0x0080200044", 60*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 61*ff3d02b2SIan Rogers "UMask": "0x1" 62*ff3d02b2SIan Rogers }, 63*ff3d02b2SIan Rogers { 64*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from DDR (local and far)", 65*ff3d02b2SIan Rogers "EventCode": "0xB7", 66*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR", 67*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 68*ff3d02b2SIan Rogers "MSRValue": "0x0181803091", 69*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 70*ff3d02b2SIan Rogers "UMask": "0x1" 71*ff3d02b2SIan Rogers }, 72*ff3d02b2SIan Rogers { 73*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Far.", 74*ff3d02b2SIan Rogers "EventCode": "0xB7", 75*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_FAR", 76*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 77*ff3d02b2SIan Rogers "MSRValue": "0x0101003091", 78*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 79*ff3d02b2SIan Rogers "UMask": "0x1" 80*ff3d02b2SIan Rogers }, 81*ff3d02b2SIan Rogers { 82*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Local.", 83*ff3d02b2SIan Rogers "EventCode": "0xB7", 84*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_NEAR", 85*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 86*ff3d02b2SIan Rogers "MSRValue": "0x0080803091", 87*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 88*ff3d02b2SIan Rogers "UMask": "0x1" 89*ff3d02b2SIan Rogers }, 90*ff3d02b2SIan Rogers { 91*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from MCDRAM (local and far)", 92*ff3d02b2SIan Rogers "EventCode": "0xB7", 93*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM", 94*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 95*ff3d02b2SIan Rogers "MSRValue": "0x0180603091", 96*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 97*ff3d02b2SIan Rogers "UMask": "0x1" 98*ff3d02b2SIan Rogers }, 99*ff3d02b2SIan Rogers { 100*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 101*ff3d02b2SIan Rogers "EventCode": "0xB7", 102*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_FAR", 103*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 104*ff3d02b2SIan Rogers "MSRValue": "0x0100403091", 105*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 106*ff3d02b2SIan Rogers "UMask": "0x1" 107*ff3d02b2SIan Rogers }, 108*ff3d02b2SIan Rogers { 109*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Local.", 110*ff3d02b2SIan Rogers "EventCode": "0xB7", 111*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_NEAR", 112*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 113*ff3d02b2SIan Rogers "MSRValue": "0x0080203091", 114*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 115*ff3d02b2SIan Rogers "UMask": "0x1" 116*ff3d02b2SIan Rogers }, 117*ff3d02b2SIan Rogers { 118*ff3d02b2SIan Rogers "BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Far.", 119*ff3d02b2SIan Rogers "EventCode": "0xB7", 120*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_FAR", 121*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 122*ff3d02b2SIan Rogers "MSRValue": "0x0101000070", 123*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 124*ff3d02b2SIan Rogers "UMask": "0x1" 125*ff3d02b2SIan Rogers }, 126*ff3d02b2SIan Rogers { 127*ff3d02b2SIan Rogers "BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Local.", 128*ff3d02b2SIan Rogers "EventCode": "0xB7", 129*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_NEAR", 130*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 131*ff3d02b2SIan Rogers "MSRValue": "0x0080800070", 132*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 133*ff3d02b2SIan Rogers "UMask": "0x1" 134*ff3d02b2SIan Rogers }, 135*ff3d02b2SIan Rogers { 136*ff3d02b2SIan Rogers "BriefDescription": "Counts any Prefetch requests that accounts for responses from MCDRAM (local and far)", 137*ff3d02b2SIan Rogers "EventCode": "0xB7", 138*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM", 139*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 140*ff3d02b2SIan Rogers "MSRValue": "0x0180600070", 141*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 142*ff3d02b2SIan Rogers "UMask": "0x1" 143*ff3d02b2SIan Rogers }, 144*ff3d02b2SIan Rogers { 145*ff3d02b2SIan Rogers "BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 146*ff3d02b2SIan Rogers "EventCode": "0xB7", 147*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_FAR", 148*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 149*ff3d02b2SIan Rogers "MSRValue": "0x0100400070", 150*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 151*ff3d02b2SIan Rogers "UMask": "0x1" 152*ff3d02b2SIan Rogers }, 153*ff3d02b2SIan Rogers { 154*ff3d02b2SIan Rogers "BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Local.", 155*ff3d02b2SIan Rogers "EventCode": "0xB7", 156*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_NEAR", 157*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 158*ff3d02b2SIan Rogers "MSRValue": "0x0080200070", 159*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 160*ff3d02b2SIan Rogers "UMask": "0x1" 161*ff3d02b2SIan Rogers }, 162*ff3d02b2SIan Rogers { 163*ff3d02b2SIan Rogers "BriefDescription": "Counts any Read request that accounts for responses from DDR (local and far)", 164*ff3d02b2SIan Rogers "EventCode": "0xB7", 16555d42d27SAndi Kleen "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR", 16655d42d27SAndi Kleen "MSRIndex": "0x1a6,0x1a7", 167*ff3d02b2SIan Rogers "MSRValue": "0x01818032f7", 16855d42d27SAndi Kleen "SampleAfterValue": "100007", 169*ff3d02b2SIan Rogers "UMask": "0x1" 170*ff3d02b2SIan Rogers }, 171*ff3d02b2SIan Rogers { 172*ff3d02b2SIan Rogers "BriefDescription": "Counts any Read request that accounts for data responses from DRAM Far.", 173*ff3d02b2SIan Rogers "EventCode": "0xB7", 174*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_FAR", 175*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 176*ff3d02b2SIan Rogers "MSRValue": "0x01010032f7", 177*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 178*ff3d02b2SIan Rogers "UMask": "0x1" 179*ff3d02b2SIan Rogers }, 180*ff3d02b2SIan Rogers { 181*ff3d02b2SIan Rogers "BriefDescription": "Counts any Read request that accounts for data responses from DRAM Local.", 182*ff3d02b2SIan Rogers "EventCode": "0xB7", 183*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_NEAR", 184*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 185*ff3d02b2SIan Rogers "MSRValue": "0x00808032f7", 186*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 187*ff3d02b2SIan Rogers "UMask": "0x1" 188*ff3d02b2SIan Rogers }, 189*ff3d02b2SIan Rogers { 190*ff3d02b2SIan Rogers "BriefDescription": "Counts any Read request that accounts for responses from MCDRAM (local and far)", 191*ff3d02b2SIan Rogers "EventCode": "0xB7", 192*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM", 193*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 194*ff3d02b2SIan Rogers "MSRValue": "0x01806032f7", 195*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 196*ff3d02b2SIan Rogers "UMask": "0x1" 197*ff3d02b2SIan Rogers }, 198*ff3d02b2SIan Rogers { 199*ff3d02b2SIan Rogers "BriefDescription": "Counts any Read request that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 200*ff3d02b2SIan Rogers "EventCode": "0xB7", 201*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_FAR", 202*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 203*ff3d02b2SIan Rogers "MSRValue": "0x01004032f7", 204*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 205*ff3d02b2SIan Rogers "UMask": "0x1" 206*ff3d02b2SIan Rogers }, 207*ff3d02b2SIan Rogers { 208*ff3d02b2SIan Rogers "BriefDescription": "Counts any Read request that accounts for data responses from MCDRAM Local.", 209*ff3d02b2SIan Rogers "EventCode": "0xB7", 210*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_NEAR", 211*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 212*ff3d02b2SIan Rogers "MSRValue": "0x00802032f7", 213*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 214*ff3d02b2SIan Rogers "UMask": "0x1" 215*ff3d02b2SIan Rogers }, 216*ff3d02b2SIan Rogers { 217*ff3d02b2SIan Rogers "BriefDescription": "Counts any request that accounts for responses from DDR (local and far)", 218*ff3d02b2SIan Rogers "EventCode": "0xB7", 219*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR", 220*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 221*ff3d02b2SIan Rogers "MSRValue": "0x0181808000", 222*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 223*ff3d02b2SIan Rogers "UMask": "0x1" 224*ff3d02b2SIan Rogers }, 225*ff3d02b2SIan Rogers { 226*ff3d02b2SIan Rogers "BriefDescription": "Counts any request that accounts for data responses from DRAM Far.", 227*ff3d02b2SIan Rogers "EventCode": "0xB7", 228*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_FAR", 229*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 230*ff3d02b2SIan Rogers "MSRValue": "0x0101008000", 231*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 232*ff3d02b2SIan Rogers "UMask": "0x1" 233*ff3d02b2SIan Rogers }, 234*ff3d02b2SIan Rogers { 235*ff3d02b2SIan Rogers "BriefDescription": "Counts any request that accounts for data responses from DRAM Local.", 236*ff3d02b2SIan Rogers "EventCode": "0xB7", 237*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_NEAR", 238*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 239*ff3d02b2SIan Rogers "MSRValue": "0x0080808000", 240*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 241*ff3d02b2SIan Rogers "UMask": "0x1" 242*ff3d02b2SIan Rogers }, 243*ff3d02b2SIan Rogers { 244*ff3d02b2SIan Rogers "BriefDescription": "Counts any request that accounts for responses from MCDRAM (local and far)", 245*ff3d02b2SIan Rogers "EventCode": "0xB7", 246*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM", 247*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 248*ff3d02b2SIan Rogers "MSRValue": "0x0180608000", 249*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 250*ff3d02b2SIan Rogers "UMask": "0x1" 251*ff3d02b2SIan Rogers }, 252*ff3d02b2SIan Rogers { 253*ff3d02b2SIan Rogers "BriefDescription": "Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 254*ff3d02b2SIan Rogers "EventCode": "0xB7", 255*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_FAR", 256*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 257*ff3d02b2SIan Rogers "MSRValue": "0x0100408000", 258*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 259*ff3d02b2SIan Rogers "UMask": "0x1" 260*ff3d02b2SIan Rogers }, 261*ff3d02b2SIan Rogers { 262*ff3d02b2SIan Rogers "BriefDescription": "Counts any request that accounts for data responses from MCDRAM Local.", 263*ff3d02b2SIan Rogers "EventCode": "0xB7", 264*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_NEAR", 265*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 266*ff3d02b2SIan Rogers "MSRValue": "0x0080208000", 267*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 268*ff3d02b2SIan Rogers "UMask": "0x1" 269*ff3d02b2SIan Rogers }, 270*ff3d02b2SIan Rogers { 271*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from DDR (local and far)", 272*ff3d02b2SIan Rogers "EventCode": "0xB7", 273*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR", 274*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 275*ff3d02b2SIan Rogers "MSRValue": "0x0181800022", 276*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 277*ff3d02b2SIan Rogers "UMask": "0x1" 278*ff3d02b2SIan Rogers }, 279*ff3d02b2SIan Rogers { 280*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from DRAM Far.", 281*ff3d02b2SIan Rogers "EventCode": "0xB7", 282*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_FAR", 283*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 284*ff3d02b2SIan Rogers "MSRValue": "0x0101000022", 285*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 286*ff3d02b2SIan Rogers "UMask": "0x1" 287*ff3d02b2SIan Rogers }, 288*ff3d02b2SIan Rogers { 289*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from DRAM Local.", 290*ff3d02b2SIan Rogers "EventCode": "0xB7", 291*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_NEAR", 292*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 293*ff3d02b2SIan Rogers "MSRValue": "0x0080800022", 294*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 295*ff3d02b2SIan Rogers "UMask": "0x1" 296*ff3d02b2SIan Rogers }, 297*ff3d02b2SIan Rogers { 298*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from MCDRAM (local and far)", 299*ff3d02b2SIan Rogers "EventCode": "0xB7", 300*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM", 301*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 302*ff3d02b2SIan Rogers "MSRValue": "0x0180600022", 303*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 304*ff3d02b2SIan Rogers "UMask": "0x1" 305*ff3d02b2SIan Rogers }, 306*ff3d02b2SIan Rogers { 307*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 308*ff3d02b2SIan Rogers "EventCode": "0xB7", 309*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_FAR", 310*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 311*ff3d02b2SIan Rogers "MSRValue": "0x0100400022", 312*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 313*ff3d02b2SIan Rogers "UMask": "0x1" 314*ff3d02b2SIan Rogers }, 315*ff3d02b2SIan Rogers { 316*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Local.", 317*ff3d02b2SIan Rogers "EventCode": "0xB7", 318*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_NEAR", 319*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 320*ff3d02b2SIan Rogers "MSRValue": "0x0080200022", 321*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 322*ff3d02b2SIan Rogers "UMask": "0x1" 323*ff3d02b2SIan Rogers }, 324*ff3d02b2SIan Rogers { 325*ff3d02b2SIan Rogers "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from DDR (local and far)", 326*ff3d02b2SIan Rogers "EventCode": "0xB7", 327*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR", 328*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 329*ff3d02b2SIan Rogers "MSRValue": "0x0181800400", 330*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 331*ff3d02b2SIan Rogers "UMask": "0x1" 332*ff3d02b2SIan Rogers }, 333*ff3d02b2SIan Rogers { 334*ff3d02b2SIan Rogers "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Far.", 335*ff3d02b2SIan Rogers "EventCode": "0xB7", 336*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_FAR", 337*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 338*ff3d02b2SIan Rogers "MSRValue": "0x0101000400", 339*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 340*ff3d02b2SIan Rogers "UMask": "0x1" 341*ff3d02b2SIan Rogers }, 342*ff3d02b2SIan Rogers { 343*ff3d02b2SIan Rogers "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Local.", 344*ff3d02b2SIan Rogers "EventCode": "0xB7", 345*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_NEAR", 346*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 347*ff3d02b2SIan Rogers "MSRValue": "0x0080800400", 348*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 349*ff3d02b2SIan Rogers "UMask": "0x1" 350*ff3d02b2SIan Rogers }, 351*ff3d02b2SIan Rogers { 352*ff3d02b2SIan Rogers "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from MCDRAM (local and far)", 353*ff3d02b2SIan Rogers "EventCode": "0xB7", 354*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM", 355*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 356*ff3d02b2SIan Rogers "MSRValue": "0x0180600400", 357*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 358*ff3d02b2SIan Rogers "UMask": "0x1" 359*ff3d02b2SIan Rogers }, 360*ff3d02b2SIan Rogers { 361*ff3d02b2SIan Rogers "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 362*ff3d02b2SIan Rogers "EventCode": "0xB7", 363*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_FAR", 364*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 365*ff3d02b2SIan Rogers "MSRValue": "0x0100400400", 366*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 367*ff3d02b2SIan Rogers "UMask": "0x1" 368*ff3d02b2SIan Rogers }, 369*ff3d02b2SIan Rogers { 370*ff3d02b2SIan Rogers "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Local.", 371*ff3d02b2SIan Rogers "EventCode": "0xB7", 372*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_NEAR", 373*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 374*ff3d02b2SIan Rogers "MSRValue": "0x0080200400", 375*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 376*ff3d02b2SIan Rogers "UMask": "0x1" 377*ff3d02b2SIan Rogers }, 378*ff3d02b2SIan Rogers { 379*ff3d02b2SIan Rogers "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from DDR (local and far)", 380*ff3d02b2SIan Rogers "EventCode": "0xB7", 381*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR", 382*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 383*ff3d02b2SIan Rogers "MSRValue": "0x0181800004", 384*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 385*ff3d02b2SIan Rogers "UMask": "0x1" 386*ff3d02b2SIan Rogers }, 387*ff3d02b2SIan Rogers { 388*ff3d02b2SIan Rogers "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Far.", 389*ff3d02b2SIan Rogers "EventCode": "0xB7", 390*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_FAR", 391*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 392*ff3d02b2SIan Rogers "MSRValue": "0x0101000004", 393*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 394*ff3d02b2SIan Rogers "UMask": "0x1" 395*ff3d02b2SIan Rogers }, 396*ff3d02b2SIan Rogers { 397*ff3d02b2SIan Rogers "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Local.", 398*ff3d02b2SIan Rogers "EventCode": "0xB7", 399*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_NEAR", 400*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 401*ff3d02b2SIan Rogers "MSRValue": "0x0080800004", 402*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 403*ff3d02b2SIan Rogers "UMask": "0x1" 404*ff3d02b2SIan Rogers }, 405*ff3d02b2SIan Rogers { 406*ff3d02b2SIan Rogers "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from MCDRAM (local and far)", 407*ff3d02b2SIan Rogers "EventCode": "0xB7", 408*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM", 409*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 410*ff3d02b2SIan Rogers "MSRValue": "0x0180600004", 411*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 412*ff3d02b2SIan Rogers "UMask": "0x1" 413*ff3d02b2SIan Rogers }, 414*ff3d02b2SIan Rogers { 415*ff3d02b2SIan Rogers "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 416*ff3d02b2SIan Rogers "EventCode": "0xB7", 417*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_FAR", 418*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 419*ff3d02b2SIan Rogers "MSRValue": "0x0100400004", 420*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 421*ff3d02b2SIan Rogers "UMask": "0x1" 422*ff3d02b2SIan Rogers }, 423*ff3d02b2SIan Rogers { 424*ff3d02b2SIan Rogers "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Local.", 425*ff3d02b2SIan Rogers "EventCode": "0xB7", 426*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_NEAR", 427*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 428*ff3d02b2SIan Rogers "MSRValue": "0x0080200004", 429*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 430*ff3d02b2SIan Rogers "UMask": "0x1" 431*ff3d02b2SIan Rogers }, 432*ff3d02b2SIan Rogers { 433*ff3d02b2SIan Rogers "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from DDR (local and far)", 434*ff3d02b2SIan Rogers "EventCode": "0xB7", 435*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR", 436*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 437*ff3d02b2SIan Rogers "MSRValue": "0x0181800001", 438*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 439*ff3d02b2SIan Rogers "UMask": "0x1" 440*ff3d02b2SIan Rogers }, 441*ff3d02b2SIan Rogers { 442*ff3d02b2SIan Rogers "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Far.", 443*ff3d02b2SIan Rogers "EventCode": "0xB7", 444*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_FAR", 445*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 446*ff3d02b2SIan Rogers "MSRValue": "0x0101000001", 447*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 448*ff3d02b2SIan Rogers "UMask": "0x1" 449*ff3d02b2SIan Rogers }, 450*ff3d02b2SIan Rogers { 451*ff3d02b2SIan Rogers "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Local.", 452*ff3d02b2SIan Rogers "EventCode": "0xB7", 453*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_NEAR", 454*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 455*ff3d02b2SIan Rogers "MSRValue": "0x0080800001", 456*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 457*ff3d02b2SIan Rogers "UMask": "0x1" 458*ff3d02b2SIan Rogers }, 459*ff3d02b2SIan Rogers { 460*ff3d02b2SIan Rogers "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from MCDRAM (local and far)", 461*ff3d02b2SIan Rogers "EventCode": "0xB7", 462*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM", 463*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 464*ff3d02b2SIan Rogers "MSRValue": "0x0180600001", 465*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 466*ff3d02b2SIan Rogers "UMask": "0x1" 467*ff3d02b2SIan Rogers }, 468*ff3d02b2SIan Rogers { 469*ff3d02b2SIan Rogers "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 470*ff3d02b2SIan Rogers "EventCode": "0xB7", 471*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_FAR", 472*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 473*ff3d02b2SIan Rogers "MSRValue": "0x0100400001", 474*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 475*ff3d02b2SIan Rogers "UMask": "0x1" 476*ff3d02b2SIan Rogers }, 477*ff3d02b2SIan Rogers { 478*ff3d02b2SIan Rogers "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Local.", 479*ff3d02b2SIan Rogers "EventCode": "0xB7", 480*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_NEAR", 481*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 482*ff3d02b2SIan Rogers "MSRValue": "0x0080200001", 483*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 484*ff3d02b2SIan Rogers "UMask": "0x1" 485*ff3d02b2SIan Rogers }, 486*ff3d02b2SIan Rogers { 487*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from DDR (local and far)", 488*ff3d02b2SIan Rogers "EventCode": "0xB7", 489*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR", 490*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 491*ff3d02b2SIan Rogers "MSRValue": "0x0181800002", 492*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 493*ff3d02b2SIan Rogers "UMask": "0x1" 494*ff3d02b2SIan Rogers }, 495*ff3d02b2SIan Rogers { 496*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Far.", 497*ff3d02b2SIan Rogers "EventCode": "0xB7", 498*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_FAR", 499*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 500*ff3d02b2SIan Rogers "MSRValue": "0x0101000002", 501*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 502*ff3d02b2SIan Rogers "UMask": "0x1" 503*ff3d02b2SIan Rogers }, 504*ff3d02b2SIan Rogers { 505*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Local.", 506*ff3d02b2SIan Rogers "EventCode": "0xB7", 507*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_NEAR", 508*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 509*ff3d02b2SIan Rogers "MSRValue": "0x0080800002", 510*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 511*ff3d02b2SIan Rogers "UMask": "0x1" 512*ff3d02b2SIan Rogers }, 513*ff3d02b2SIan Rogers { 514*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from MCDRAM (local and far)", 515*ff3d02b2SIan Rogers "EventCode": "0xB7", 516*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM", 517*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 518*ff3d02b2SIan Rogers "MSRValue": "0x0180600002", 519*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 520*ff3d02b2SIan Rogers "UMask": "0x1" 521*ff3d02b2SIan Rogers }, 522*ff3d02b2SIan Rogers { 523*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 524*ff3d02b2SIan Rogers "EventCode": "0xB7", 525*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_FAR", 526*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 527*ff3d02b2SIan Rogers "MSRValue": "0x0100400002", 528*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 529*ff3d02b2SIan Rogers "UMask": "0x1" 530*ff3d02b2SIan Rogers }, 531*ff3d02b2SIan Rogers { 532*ff3d02b2SIan Rogers "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Local.", 533*ff3d02b2SIan Rogers "EventCode": "0xB7", 534*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_NEAR", 535*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 536*ff3d02b2SIan Rogers "MSRValue": "0x0080200002", 537*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 538*ff3d02b2SIan Rogers "UMask": "0x1" 539*ff3d02b2SIan Rogers }, 540*ff3d02b2SIan Rogers { 541*ff3d02b2SIan Rogers "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from DDR (local and far)", 542*ff3d02b2SIan Rogers "EventCode": "0xB7", 543*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR", 544*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 545*ff3d02b2SIan Rogers "MSRValue": "0x0181800080", 546*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 547*ff3d02b2SIan Rogers "UMask": "0x1" 548*ff3d02b2SIan Rogers }, 549*ff3d02b2SIan Rogers { 550*ff3d02b2SIan Rogers "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Far.", 551*ff3d02b2SIan Rogers "EventCode": "0xB7", 552*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_FAR", 553*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 554*ff3d02b2SIan Rogers "MSRValue": "0x0101000080", 555*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 556*ff3d02b2SIan Rogers "UMask": "0x1" 557*ff3d02b2SIan Rogers }, 558*ff3d02b2SIan Rogers { 559*ff3d02b2SIan Rogers "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Local.", 560*ff3d02b2SIan Rogers "EventCode": "0xB7", 561*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_NEAR", 562*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 563*ff3d02b2SIan Rogers "MSRValue": "0x0080800080", 564*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 565*ff3d02b2SIan Rogers "UMask": "0x1" 566*ff3d02b2SIan Rogers }, 567*ff3d02b2SIan Rogers { 568*ff3d02b2SIan Rogers "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from MCDRAM (local and far)", 569*ff3d02b2SIan Rogers "EventCode": "0xB7", 570*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM", 571*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 572*ff3d02b2SIan Rogers "MSRValue": "0x0180600080", 573*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 574*ff3d02b2SIan Rogers "UMask": "0x1" 575*ff3d02b2SIan Rogers }, 576*ff3d02b2SIan Rogers { 577*ff3d02b2SIan Rogers "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 578*ff3d02b2SIan Rogers "EventCode": "0xB7", 579*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_FAR", 580*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 581*ff3d02b2SIan Rogers "MSRValue": "0x0100400080", 582*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 583*ff3d02b2SIan Rogers "UMask": "0x1" 584*ff3d02b2SIan Rogers }, 585*ff3d02b2SIan Rogers { 586*ff3d02b2SIan Rogers "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Local.", 587*ff3d02b2SIan Rogers "EventCode": "0xB7", 588*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_NEAR", 589*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 590*ff3d02b2SIan Rogers "MSRValue": "0x0080200080", 591*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 592*ff3d02b2SIan Rogers "UMask": "0x1" 593*ff3d02b2SIan Rogers }, 594*ff3d02b2SIan Rogers { 595*ff3d02b2SIan Rogers "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from any NON_DRAM system address. This includes MMIO transactions", 596*ff3d02b2SIan Rogers "EventCode": "0xB7", 597*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.NON_DRAM", 598*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 599*ff3d02b2SIan Rogers "MSRValue": "0x2000020080", 600*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 601*ff3d02b2SIan Rogers "UMask": "0x1" 602*ff3d02b2SIan Rogers }, 603*ff3d02b2SIan Rogers { 604*ff3d02b2SIan Rogers "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Far.", 605*ff3d02b2SIan Rogers "EventCode": "0xB7", 606*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_FAR", 607*ff3d02b2SIan Rogers "MSRIndex": "0x1a7", 608*ff3d02b2SIan Rogers "MSRValue": "0x0101000100", 609*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 610*ff3d02b2SIan Rogers "UMask": "0x1" 611*ff3d02b2SIan Rogers }, 612*ff3d02b2SIan Rogers { 613*ff3d02b2SIan Rogers "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Local.", 614*ff3d02b2SIan Rogers "EventCode": "0xB7", 615*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_NEAR", 616*ff3d02b2SIan Rogers "MSRIndex": "0x1a7", 617*ff3d02b2SIan Rogers "MSRValue": "0x0080800100", 618*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 619*ff3d02b2SIan Rogers "UMask": "0x1" 620*ff3d02b2SIan Rogers }, 621*ff3d02b2SIan Rogers { 622*ff3d02b2SIan Rogers "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from MCDRAM (local and far)", 623*ff3d02b2SIan Rogers "EventCode": "0xB7", 624*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM", 625*ff3d02b2SIan Rogers "MSRIndex": "0x1a7", 626*ff3d02b2SIan Rogers "MSRValue": "0x0180600100", 627*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 628*ff3d02b2SIan Rogers "UMask": "0x1" 629*ff3d02b2SIan Rogers }, 630*ff3d02b2SIan Rogers { 631*ff3d02b2SIan Rogers "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 632*ff3d02b2SIan Rogers "EventCode": "0xB7", 633*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_FAR", 634*ff3d02b2SIan Rogers "MSRIndex": "0x1a7", 635*ff3d02b2SIan Rogers "MSRValue": "0x0100400100", 636*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 637*ff3d02b2SIan Rogers "UMask": "0x1" 638*ff3d02b2SIan Rogers }, 639*ff3d02b2SIan Rogers { 640*ff3d02b2SIan Rogers "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Local.", 641*ff3d02b2SIan Rogers "EventCode": "0xB7", 642*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_NEAR", 643*ff3d02b2SIan Rogers "MSRIndex": "0x1a7", 644*ff3d02b2SIan Rogers "MSRValue": "0x0080200100", 645*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 646*ff3d02b2SIan Rogers "UMask": "0x1" 647*ff3d02b2SIan Rogers }, 648*ff3d02b2SIan Rogers { 649*ff3d02b2SIan Rogers "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from DDR (local and far)", 650*ff3d02b2SIan Rogers "EventCode": "0xB7", 651*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR", 652*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 653*ff3d02b2SIan Rogers "MSRValue": "0x0181802000", 654*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 655*ff3d02b2SIan Rogers "UMask": "0x1" 656*ff3d02b2SIan Rogers }, 657*ff3d02b2SIan Rogers { 658*ff3d02b2SIan Rogers "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Far.", 659*ff3d02b2SIan Rogers "EventCode": "0xB7", 660*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_FAR", 661*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 662*ff3d02b2SIan Rogers "MSRValue": "0x0101002000", 663*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 664*ff3d02b2SIan Rogers "UMask": "0x1" 665*ff3d02b2SIan Rogers }, 666*ff3d02b2SIan Rogers { 667*ff3d02b2SIan Rogers "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Local.", 668*ff3d02b2SIan Rogers "EventCode": "0xB7", 669*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_NEAR", 670*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 671*ff3d02b2SIan Rogers "MSRValue": "0x0080802000", 672*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 673*ff3d02b2SIan Rogers "UMask": "0x1" 674*ff3d02b2SIan Rogers }, 675*ff3d02b2SIan Rogers { 676*ff3d02b2SIan Rogers "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 677*ff3d02b2SIan Rogers "EventCode": "0xB7", 678*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_FAR", 679*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 680*ff3d02b2SIan Rogers "MSRValue": "0x0100402000", 681*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 682*ff3d02b2SIan Rogers "UMask": "0x1" 683*ff3d02b2SIan Rogers }, 684*ff3d02b2SIan Rogers { 685*ff3d02b2SIan Rogers "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Local.", 686*ff3d02b2SIan Rogers "EventCode": "0xB7", 687*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_NEAR", 688*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 689*ff3d02b2SIan Rogers "MSRValue": "0x0080202000", 690*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 691*ff3d02b2SIan Rogers "UMask": "0x1" 692*ff3d02b2SIan Rogers }, 693*ff3d02b2SIan Rogers { 694*ff3d02b2SIan Rogers "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from DDR (local and far)", 695*ff3d02b2SIan Rogers "EventCode": "0xB7", 696*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR", 697*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 698*ff3d02b2SIan Rogers "MSRValue": "0x0181800040", 699*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 700*ff3d02b2SIan Rogers "UMask": "0x1" 701*ff3d02b2SIan Rogers }, 702*ff3d02b2SIan Rogers { 703*ff3d02b2SIan Rogers "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Far.", 704*ff3d02b2SIan Rogers "EventCode": "0xB7", 705*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_FAR", 706*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 707*ff3d02b2SIan Rogers "MSRValue": "0x0101000040", 708*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 709*ff3d02b2SIan Rogers "UMask": "0x1" 710*ff3d02b2SIan Rogers }, 711*ff3d02b2SIan Rogers { 712*ff3d02b2SIan Rogers "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Local.", 713*ff3d02b2SIan Rogers "EventCode": "0xB7", 714*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_NEAR", 715*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 716*ff3d02b2SIan Rogers "MSRValue": "0x0080800040", 717*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 718*ff3d02b2SIan Rogers "UMask": "0x1" 719*ff3d02b2SIan Rogers }, 720*ff3d02b2SIan Rogers { 721*ff3d02b2SIan Rogers "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 722*ff3d02b2SIan Rogers "EventCode": "0xB7", 723*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_FAR", 724*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 725*ff3d02b2SIan Rogers "MSRValue": "0x0100400040", 726*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 727*ff3d02b2SIan Rogers "UMask": "0x1" 728*ff3d02b2SIan Rogers }, 729*ff3d02b2SIan Rogers { 730*ff3d02b2SIan Rogers "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Local.", 731*ff3d02b2SIan Rogers "EventCode": "0xB7", 732*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_NEAR", 733*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 734*ff3d02b2SIan Rogers "MSRValue": "0x0080200040", 735*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 736*ff3d02b2SIan Rogers "UMask": "0x1" 737*ff3d02b2SIan Rogers }, 738*ff3d02b2SIan Rogers { 739*ff3d02b2SIan Rogers "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from DDR (local and far)", 740*ff3d02b2SIan Rogers "EventCode": "0xB7", 741*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR", 742*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 743*ff3d02b2SIan Rogers "MSRValue": "0x0181800020", 744*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 745*ff3d02b2SIan Rogers "UMask": "0x1" 746*ff3d02b2SIan Rogers }, 747*ff3d02b2SIan Rogers { 748*ff3d02b2SIan Rogers "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Far.", 749*ff3d02b2SIan Rogers "EventCode": "0xB7", 750*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_FAR", 751*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 752*ff3d02b2SIan Rogers "MSRValue": "0x0101000020", 753*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 754*ff3d02b2SIan Rogers "UMask": "0x1" 755*ff3d02b2SIan Rogers }, 756*ff3d02b2SIan Rogers { 757*ff3d02b2SIan Rogers "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Local.", 758*ff3d02b2SIan Rogers "EventCode": "0xB7", 759*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_NEAR", 760*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 761*ff3d02b2SIan Rogers "MSRValue": "0x0080800020", 762*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 763*ff3d02b2SIan Rogers "UMask": "0x1" 764*ff3d02b2SIan Rogers }, 765*ff3d02b2SIan Rogers { 766*ff3d02b2SIan Rogers "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from MCDRAM (local and far)", 767*ff3d02b2SIan Rogers "EventCode": "0xB7", 768*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM", 769*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 770*ff3d02b2SIan Rogers "MSRValue": "0x0180600020", 771*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 772*ff3d02b2SIan Rogers "UMask": "0x1" 773*ff3d02b2SIan Rogers }, 774*ff3d02b2SIan Rogers { 775*ff3d02b2SIan Rogers "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 776*ff3d02b2SIan Rogers "EventCode": "0xB7", 777*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_FAR", 778*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 779*ff3d02b2SIan Rogers "MSRValue": "0x0100400020", 780*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 781*ff3d02b2SIan Rogers "UMask": "0x1" 782*ff3d02b2SIan Rogers }, 783*ff3d02b2SIan Rogers { 784*ff3d02b2SIan Rogers "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Local.", 785*ff3d02b2SIan Rogers "EventCode": "0xB7", 786*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_NEAR", 787*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 788*ff3d02b2SIan Rogers "MSRValue": "0x0080200020", 789*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 790*ff3d02b2SIan Rogers "UMask": "0x1" 791*ff3d02b2SIan Rogers }, 792*ff3d02b2SIan Rogers { 793*ff3d02b2SIan Rogers "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from any NON_DRAM system address. This includes MMIO transactions", 794*ff3d02b2SIan Rogers "EventCode": "0xB7", 795*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.NON_DRAM", 796*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 797*ff3d02b2SIan Rogers "MSRValue": "0x2000020020", 798*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 799*ff3d02b2SIan Rogers "UMask": "0x1" 800*ff3d02b2SIan Rogers }, 801*ff3d02b2SIan Rogers { 802*ff3d02b2SIan Rogers "BriefDescription": "Counts Software Prefetches that accounts for responses from DDR (local and far)", 803*ff3d02b2SIan Rogers "EventCode": "0xB7", 804*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR", 805*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 806*ff3d02b2SIan Rogers "MSRValue": "0x0181801000", 807*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 808*ff3d02b2SIan Rogers "UMask": "0x1" 809*ff3d02b2SIan Rogers }, 810*ff3d02b2SIan Rogers { 811*ff3d02b2SIan Rogers "BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Far.", 812*ff3d02b2SIan Rogers "EventCode": "0xB7", 813*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_FAR", 814*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 815*ff3d02b2SIan Rogers "MSRValue": "0x0101001000", 816*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 817*ff3d02b2SIan Rogers "UMask": "0x1" 818*ff3d02b2SIan Rogers }, 819*ff3d02b2SIan Rogers { 820*ff3d02b2SIan Rogers "BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Local.", 821*ff3d02b2SIan Rogers "EventCode": "0xB7", 822*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_NEAR", 823*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 824*ff3d02b2SIan Rogers "MSRValue": "0x0080801000", 825*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 826*ff3d02b2SIan Rogers "UMask": "0x1" 827*ff3d02b2SIan Rogers }, 828*ff3d02b2SIan Rogers { 829*ff3d02b2SIan Rogers "BriefDescription": "Counts Software Prefetches that accounts for responses from MCDRAM (local and far)", 830*ff3d02b2SIan Rogers "EventCode": "0xB7", 831*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM", 832*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 833*ff3d02b2SIan Rogers "MSRValue": "0x0180601000", 834*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 835*ff3d02b2SIan Rogers "UMask": "0x1" 836*ff3d02b2SIan Rogers }, 837*ff3d02b2SIan Rogers { 838*ff3d02b2SIan Rogers "BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 839*ff3d02b2SIan Rogers "EventCode": "0xB7", 840*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_FAR", 841*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 842*ff3d02b2SIan Rogers "MSRValue": "0x0100401000", 843*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 844*ff3d02b2SIan Rogers "UMask": "0x1" 845*ff3d02b2SIan Rogers }, 846*ff3d02b2SIan Rogers { 847*ff3d02b2SIan Rogers "BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Local.", 848*ff3d02b2SIan Rogers "EventCode": "0xB7", 849*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_NEAR", 850*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 851*ff3d02b2SIan Rogers "MSRValue": "0x0080201000", 852*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 853*ff3d02b2SIan Rogers "UMask": "0x1" 854*ff3d02b2SIan Rogers }, 855*ff3d02b2SIan Rogers { 856*ff3d02b2SIan Rogers "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from DDR (local and far)", 857*ff3d02b2SIan Rogers "EventCode": "0xB7", 858*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR", 859*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 860*ff3d02b2SIan Rogers "MSRValue": "0x0181800200", 861*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 862*ff3d02b2SIan Rogers "UMask": "0x1" 863*ff3d02b2SIan Rogers }, 864*ff3d02b2SIan Rogers { 865*ff3d02b2SIan Rogers "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Far.", 866*ff3d02b2SIan Rogers "EventCode": "0xB7", 867*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_FAR", 868*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 869*ff3d02b2SIan Rogers "MSRValue": "0x0101000200", 870*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 871*ff3d02b2SIan Rogers "UMask": "0x1" 872*ff3d02b2SIan Rogers }, 873*ff3d02b2SIan Rogers { 874*ff3d02b2SIan Rogers "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Local.", 875*ff3d02b2SIan Rogers "EventCode": "0xB7", 876*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_NEAR", 877*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 878*ff3d02b2SIan Rogers "MSRValue": "0x0080800200", 879*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 880*ff3d02b2SIan Rogers "UMask": "0x1" 881*ff3d02b2SIan Rogers }, 882*ff3d02b2SIan Rogers { 883*ff3d02b2SIan Rogers "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from MCDRAM (local and far)", 884*ff3d02b2SIan Rogers "EventCode": "0xB7", 885*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM", 886*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 887*ff3d02b2SIan Rogers "MSRValue": "0x0180600200", 888*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 889*ff3d02b2SIan Rogers "UMask": "0x1" 890*ff3d02b2SIan Rogers }, 891*ff3d02b2SIan Rogers { 892*ff3d02b2SIan Rogers "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 893*ff3d02b2SIan Rogers "EventCode": "0xB7", 894*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_FAR", 895*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 896*ff3d02b2SIan Rogers "MSRValue": "0x0100400200", 897*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 898*ff3d02b2SIan Rogers "UMask": "0x1" 899*ff3d02b2SIan Rogers }, 900*ff3d02b2SIan Rogers { 901*ff3d02b2SIan Rogers "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Local.", 902*ff3d02b2SIan Rogers "EventCode": "0xB7", 903*ff3d02b2SIan Rogers "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_NEAR", 904*ff3d02b2SIan Rogers "MSRIndex": "0x1a6,0x1a7", 905*ff3d02b2SIan Rogers "MSRValue": "0x0080200200", 906*ff3d02b2SIan Rogers "SampleAfterValue": "100007", 907*ff3d02b2SIan Rogers "UMask": "0x1" 90855d42d27SAndi Kleen } 90955d42d27SAndi Kleen] 910