1902ea4eeSAndi Kleen[ 2902ea4eeSAndi Kleen { 3*2782403cSIan Rogers "BriefDescription": "Unhalted core cycles when the thread is in ring 0.", 4902ea4eeSAndi Kleen "Counter": "0,1,2,3", 5*2782403cSIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 6902ea4eeSAndi Kleen "EventCode": "0x5C", 7902ea4eeSAndi Kleen "EventName": "CPL_CYCLES.RING0", 8902ea4eeSAndi Kleen "SampleAfterValue": "2000003", 9*2782403cSIan Rogers "UMask": "0x1" 10902ea4eeSAndi Kleen }, 11902ea4eeSAndi Kleen { 12*2782403cSIan Rogers "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", 13902ea4eeSAndi Kleen "Counter": "0,1,2,3", 14*2782403cSIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 15*2782403cSIan Rogers "CounterMask": "1", 16902ea4eeSAndi Kleen "EdgeDetect": "1", 17*2782403cSIan Rogers "EventCode": "0x5C", 18902ea4eeSAndi Kleen "EventName": "CPL_CYCLES.RING0_TRANS", 19902ea4eeSAndi Kleen "SampleAfterValue": "100007", 20*2782403cSIan Rogers "UMask": "0x1" 21902ea4eeSAndi Kleen }, 22902ea4eeSAndi Kleen { 23*2782403cSIan Rogers "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.", 24902ea4eeSAndi Kleen "Counter": "0,1,2,3", 25*2782403cSIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 26*2782403cSIan Rogers "EventCode": "0x5C", 27902ea4eeSAndi Kleen "EventName": "CPL_CYCLES.RING123", 28902ea4eeSAndi Kleen "SampleAfterValue": "2000003", 29*2782403cSIan Rogers "UMask": "0x2" 30902ea4eeSAndi Kleen }, 31902ea4eeSAndi Kleen { 32*2782403cSIan Rogers "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .", 33902ea4eeSAndi Kleen "Counter": "0,1,2,3", 34*2782403cSIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 35*2782403cSIan Rogers "EventCode": "0x4E", 36902ea4eeSAndi Kleen "EventName": "HW_PRE_REQ.DL1_MISS", 37902ea4eeSAndi Kleen "SampleAfterValue": "2000003", 38*2782403cSIan Rogers "UMask": "0x2" 39902ea4eeSAndi Kleen }, 40902ea4eeSAndi Kleen { 41*2782403cSIan Rogers "BriefDescription": "Valid instructions written to IQ per cycle.", 42902ea4eeSAndi Kleen "Counter": "0,1,2,3", 43*2782403cSIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 44*2782403cSIan Rogers "EventCode": "0x17", 45*2782403cSIan Rogers "EventName": "INSTS_WRITTEN_TO_IQ.INSTS", 46*2782403cSIan Rogers "SampleAfterValue": "2000003", 47*2782403cSIan Rogers "UMask": "0x1" 48*2782403cSIan Rogers }, 49*2782403cSIan Rogers { 50*2782403cSIan Rogers "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.", 51*2782403cSIan Rogers "Counter": "0,1,2,3", 52*2782403cSIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 53*2782403cSIan Rogers "EventCode": "0x63", 54902ea4eeSAndi Kleen "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", 55902ea4eeSAndi Kleen "SampleAfterValue": "2000003", 56*2782403cSIan Rogers "UMask": "0x1" 57902ea4eeSAndi Kleen } 58902ea4eeSAndi Kleen]