1902ea4eeSAndi Kleen[ 2902ea4eeSAndi Kleen { 3*2782403cSIan Rogers "BriefDescription": "Unhalted core cycles when the thread is in ring 0.", 4902ea4eeSAndi Kleen "EventCode": "0x5C", 5902ea4eeSAndi Kleen "EventName": "CPL_CYCLES.RING0", 6902ea4eeSAndi Kleen "SampleAfterValue": "2000003", 7*2782403cSIan Rogers "UMask": "0x1" 8902ea4eeSAndi Kleen }, 9902ea4eeSAndi Kleen { 10*2782403cSIan Rogers "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", 11*2782403cSIan Rogers "CounterMask": "1", 12902ea4eeSAndi Kleen "EdgeDetect": "1", 13*2782403cSIan Rogers "EventCode": "0x5C", 14902ea4eeSAndi Kleen "EventName": "CPL_CYCLES.RING0_TRANS", 15902ea4eeSAndi Kleen "SampleAfterValue": "100007", 16*2782403cSIan Rogers "UMask": "0x1" 17902ea4eeSAndi Kleen }, 18902ea4eeSAndi Kleen { 19*2782403cSIan Rogers "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.", 20*2782403cSIan Rogers "EventCode": "0x5C", 21902ea4eeSAndi Kleen "EventName": "CPL_CYCLES.RING123", 22902ea4eeSAndi Kleen "SampleAfterValue": "2000003", 23*2782403cSIan Rogers "UMask": "0x2" 24902ea4eeSAndi Kleen }, 25902ea4eeSAndi Kleen { 26*2782403cSIan Rogers "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .", 27*2782403cSIan Rogers "EventCode": "0x4E", 28902ea4eeSAndi Kleen "EventName": "HW_PRE_REQ.DL1_MISS", 29902ea4eeSAndi Kleen "SampleAfterValue": "2000003", 30*2782403cSIan Rogers "UMask": "0x2" 31902ea4eeSAndi Kleen }, 32902ea4eeSAndi Kleen { 33*2782403cSIan Rogers "BriefDescription": "Valid instructions written to IQ per cycle.", 34*2782403cSIan Rogers "EventCode": "0x17", 35*2782403cSIan Rogers "EventName": "INSTS_WRITTEN_TO_IQ.INSTS", 36*2782403cSIan Rogers "SampleAfterValue": "2000003", 37*2782403cSIan Rogers "UMask": "0x1" 38*2782403cSIan Rogers }, 39*2782403cSIan Rogers { 40*2782403cSIan Rogers "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.", 41*2782403cSIan Rogers "EventCode": "0x63", 42902ea4eeSAndi Kleen "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", 43902ea4eeSAndi Kleen "SampleAfterValue": "2000003", 44*2782403cSIan Rogers "UMask": "0x1" 45902ea4eeSAndi Kleen } 46902ea4eeSAndi Kleen] 47