1[
2    {
3        "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
4        "EventCode": "0xC3",
5        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
6        "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers.  Machine clears can have a significant performance impact if they are happening frequently.",
7        "SampleAfterValue": "100003",
8        "UMask": "0x2"
9    },
10    {
11        "BriefDescription": "Loads with latency value being above 128.",
12        "EventCode": "0xCD",
13        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
14        "MSRIndex": "0x3F6",
15        "MSRValue": "0x80",
16        "PEBS": "2",
17        "SampleAfterValue": "1009",
18        "UMask": "0x1"
19    },
20    {
21        "BriefDescription": "Loads with latency value being above 16.",
22        "EventCode": "0xCD",
23        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
24        "MSRIndex": "0x3F6",
25        "MSRValue": "0x10",
26        "PEBS": "2",
27        "SampleAfterValue": "20011",
28        "UMask": "0x1"
29    },
30    {
31        "BriefDescription": "Loads with latency value being above 256.",
32        "EventCode": "0xCD",
33        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
34        "MSRIndex": "0x3F6",
35        "MSRValue": "0x100",
36        "PEBS": "2",
37        "SampleAfterValue": "503",
38        "UMask": "0x1"
39    },
40    {
41        "BriefDescription": "Loads with latency value being above 32.",
42        "EventCode": "0xCD",
43        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
44        "MSRIndex": "0x3F6",
45        "MSRValue": "0x20",
46        "PEBS": "2",
47        "SampleAfterValue": "100007",
48        "UMask": "0x1"
49    },
50    {
51        "BriefDescription": "Loads with latency value being above 4 .",
52        "EventCode": "0xCD",
53        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
54        "MSRIndex": "0x3F6",
55        "MSRValue": "0x4",
56        "PEBS": "2",
57        "SampleAfterValue": "100003",
58        "UMask": "0x1"
59    },
60    {
61        "BriefDescription": "Loads with latency value being above 512.",
62        "EventCode": "0xCD",
63        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
64        "MSRIndex": "0x3F6",
65        "MSRValue": "0x200",
66        "PEBS": "2",
67        "SampleAfterValue": "101",
68        "UMask": "0x1"
69    },
70    {
71        "BriefDescription": "Loads with latency value being above 64.",
72        "EventCode": "0xCD",
73        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
74        "MSRIndex": "0x3F6",
75        "MSRValue": "0x40",
76        "PEBS": "2",
77        "SampleAfterValue": "2003",
78        "UMask": "0x1"
79    },
80    {
81        "BriefDescription": "Loads with latency value being above 8.",
82        "EventCode": "0xCD",
83        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
84        "MSRIndex": "0x3F6",
85        "MSRValue": "0x8",
86        "PEBS": "2",
87        "SampleAfterValue": "50021",
88        "UMask": "0x1"
89    },
90    {
91        "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).",
92        "EventCode": "0xCD",
93        "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
94        "PEBS": "2",
95        "SampleAfterValue": "2000003",
96        "UMask": "0x2"
97    },
98    {
99        "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.",
100        "EventCode": "0x05",
101        "EventName": "MISALIGN_MEM_REF.LOADS",
102        "SampleAfterValue": "2000003",
103        "UMask": "0x1"
104    },
105    {
106        "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.",
107        "EventCode": "0x05",
108        "EventName": "MISALIGN_MEM_REF.STORES",
109        "SampleAfterValue": "2000003",
110        "UMask": "0x2"
111    },
112    {
113        "BriefDescription": "This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded.",
114        "EventCode": "0xB7, 0xBB",
115        "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.ANY_RESPONSE",
116        "MSRIndex": "0x1a6,0x1a7",
117        "MSRValue": "0x3FFFC20077",
118        "SampleAfterValue": "100003",
119        "UMask": "0x1"
120    },
121    {
122        "BriefDescription": "Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded.",
123        "EventCode": "0xB7, 0xBB",
124        "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.LOCAL_DRAM",
125        "MSRIndex": "0x1a6,0x1a7",
126        "MSRValue": "0x600400077",
127        "SampleAfterValue": "100003",
128        "UMask": "0x1"
129    },
130    {
131        "BriefDescription": "This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded.",
132        "EventCode": "0xB7, 0xBB",
133        "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.REMOTE_HITM_HIT_FORWARD",
134        "MSRIndex": "0x1a6,0x1a7",
135        "MSRValue": "0x187FC20077",
136        "SampleAfterValue": "100003",
137        "UMask": "0x1"
138    },
139    {
140        "BriefDescription": "Counts all demand code reads that miss the LLC",
141        "EventCode": "0xB7, 0xBB",
142        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",
143        "MSRIndex": "0x1a6,0x1a7",
144        "MSRValue": "0x3fffc20004",
145        "SampleAfterValue": "100003",
146        "UMask": "0x1"
147    },
148    {
149        "BriefDescription": "Counts all demand code reads that miss the LLC  and the data returned from local dram",
150        "EventCode": "0xB7, 0xBB",
151        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",
152        "MSRIndex": "0x1a6,0x1a7",
153        "MSRValue": "0x600400004",
154        "SampleAfterValue": "100003",
155        "UMask": "0x1"
156    },
157    {
158        "BriefDescription": "Counts all demand code reads that miss the LLC  and the data returned from remote dram",
159        "EventCode": "0xB7, 0xBB",
160        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM",
161        "MSRIndex": "0x1a6,0x1a7",
162        "MSRValue": "0x67f800004",
163        "SampleAfterValue": "100003",
164        "UMask": "0x1"
165    },
166    {
167        "BriefDescription": "Counts all demand code reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",
168        "EventCode": "0xB7, 0xBB",
169        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM",
170        "MSRIndex": "0x1a6,0x1a7",
171        "MSRValue": "0x107fc00004",
172        "SampleAfterValue": "100003",
173        "UMask": "0x1"
174    },
175    {
176        "BriefDescription": "Counts all demand code reads that miss the LLC  and the data forwarded from remote cache",
177        "EventCode": "0xB7, 0xBB",
178        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD",
179        "MSRIndex": "0x1a6,0x1a7",
180        "MSRValue": "0x87f820004",
181        "SampleAfterValue": "100003",
182        "UMask": "0x1"
183    },
184    {
185        "BriefDescription": "Counts demand data reads that miss the LLC  and the data returned from remote & local dram",
186        "EventCode": "0xB7, 0xBB",
187        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM",
188        "MSRIndex": "0x1a6,0x1a7",
189        "MSRValue": "0x67fc00001",
190        "SampleAfterValue": "100003",
191        "UMask": "0x1"
192    },
193    {
194        "BriefDescription": "Counts demand data reads that miss in the LLC",
195        "EventCode": "0xB7, 0xBB",
196        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",
197        "MSRIndex": "0x1a6,0x1a7",
198        "MSRValue": "0x3fffc20001",
199        "SampleAfterValue": "100003",
200        "UMask": "0x1"
201    },
202    {
203        "BriefDescription": "Counts demand data reads that miss the LLC  and the data returned from local dram",
204        "EventCode": "0xB7, 0xBB",
205        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",
206        "MSRIndex": "0x1a6,0x1a7",
207        "MSRValue": "0x600400001",
208        "SampleAfterValue": "100003",
209        "UMask": "0x1"
210    },
211    {
212        "BriefDescription": "Counts demand data reads that miss the LLC  and the data returned from remote dram",
213        "EventCode": "0xB7, 0xBB",
214        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM",
215        "MSRIndex": "0x1a6,0x1a7",
216        "MSRValue": "0x67f800001",
217        "SampleAfterValue": "100003",
218        "UMask": "0x1"
219    },
220    {
221        "BriefDescription": "Counts demand data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",
222        "EventCode": "0xB7, 0xBB",
223        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM",
224        "MSRIndex": "0x1a6,0x1a7",
225        "MSRValue": "0x107fc00001",
226        "SampleAfterValue": "100003",
227        "UMask": "0x1"
228    },
229    {
230        "BriefDescription": "Counts demand data reads that miss the LLC  and the data forwarded from remote cache",
231        "EventCode": "0xB7, 0xBB",
232        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
233        "MSRIndex": "0x1a6,0x1a7",
234        "MSRValue": "0x87f820001",
235        "SampleAfterValue": "100003",
236        "UMask": "0x1"
237    },
238    {
239        "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from remote & local dram",
240        "EventCode": "0xB7, 0xBB",
241        "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",
242        "MSRIndex": "0x1a6,0x1a7",
243        "MSRValue": "0x3fffc20040",
244        "SampleAfterValue": "100003",
245        "UMask": "0x1"
246    },
247    {
248        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from remote & local dram",
249        "EventCode": "0xB7, 0xBB",
250        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM",
251        "MSRIndex": "0x1a6,0x1a7",
252        "MSRValue": "0x67fc00010",
253        "SampleAfterValue": "100003",
254        "UMask": "0x1"
255    },
256    {
257        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC",
258        "EventCode": "0xB7, 0xBB",
259        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",
260        "MSRIndex": "0x1a6,0x1a7",
261        "MSRValue": "0x3fffc20010",
262        "SampleAfterValue": "100003",
263        "UMask": "0x1"
264    },
265    {
266        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from local dram",
267        "EventCode": "0xB7, 0xBB",
268        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM",
269        "MSRIndex": "0x1a6,0x1a7",
270        "MSRValue": "0x600400010",
271        "SampleAfterValue": "100003",
272        "UMask": "0x1"
273    },
274    {
275        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  that miss the LLC  and the data returned from remote dram",
276        "EventCode": "0xB7, 0xBB",
277        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM",
278        "MSRIndex": "0x1a6,0x1a7",
279        "MSRValue": "0x67f800010",
280        "SampleAfterValue": "100003",
281        "UMask": "0x1"
282    },
283    {
284        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",
285        "EventCode": "0xB7, 0xBB",
286        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM",
287        "MSRIndex": "0x1a6,0x1a7",
288        "MSRValue": "0x107fc00010",
289        "SampleAfterValue": "100003",
290        "UMask": "0x1"
291    },
292    {
293        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data forwarded from remote cache",
294        "EventCode": "0xB7, 0xBB",
295        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
296        "MSRIndex": "0x1a6,0x1a7",
297        "MSRValue": "0x87f820010",
298        "SampleAfterValue": "100003",
299        "UMask": "0x1"
300    },
301    {
302        "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC",
303        "EventCode": "0xB7, 0xBB",
304        "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
305        "MSRIndex": "0x1a6,0x1a7",
306        "MSRValue": "0x3fffc20200",
307        "SampleAfterValue": "100003",
308        "UMask": "0x1"
309    },
310    {
311        "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
312        "EventCode": "0xB7, 0xBB",
313        "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",
314        "MSRIndex": "0x1a6,0x1a7",
315        "MSRValue": "0x3fffc20080",
316        "SampleAfterValue": "100003",
317        "UMask": "0x1"
318    }
319]
320