1902ea4eeSAndi Kleen[
2902ea4eeSAndi Kleen    {
3902ea4eeSAndi Kleen        "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
4*2782403cSIan Rogers        "EventCode": "0xC3",
5*2782403cSIan Rogers        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
6*2782403cSIan Rogers        "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers.  Machine clears can have a significant performance impact if they are happening frequently.",
7902ea4eeSAndi Kleen        "SampleAfterValue": "100003",
8*2782403cSIan Rogers        "UMask": "0x2"
9902ea4eeSAndi Kleen    },
10902ea4eeSAndi Kleen    {
11*2782403cSIan Rogers        "BriefDescription": "Loads with latency value being above 128.",
12902ea4eeSAndi Kleen        "EventCode": "0xCD",
13902ea4eeSAndi Kleen        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
14902ea4eeSAndi Kleen        "MSRIndex": "0x3F6",
15*2782403cSIan Rogers        "MSRValue": "0x80",
16*2782403cSIan Rogers        "PEBS": "2",
17902ea4eeSAndi Kleen        "SampleAfterValue": "1009",
18*2782403cSIan Rogers        "UMask": "0x1"
19902ea4eeSAndi Kleen    },
20902ea4eeSAndi Kleen    {
21*2782403cSIan Rogers        "BriefDescription": "Loads with latency value being above 16.",
22*2782403cSIan Rogers        "EventCode": "0xCD",
23*2782403cSIan Rogers        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
24*2782403cSIan Rogers        "MSRIndex": "0x3F6",
25*2782403cSIan Rogers        "MSRValue": "0x10",
26*2782403cSIan Rogers        "PEBS": "2",
27*2782403cSIan Rogers        "SampleAfterValue": "20011",
28*2782403cSIan Rogers        "UMask": "0x1"
29*2782403cSIan Rogers    },
30*2782403cSIan Rogers    {
31*2782403cSIan Rogers        "BriefDescription": "Loads with latency value being above 256.",
32*2782403cSIan Rogers        "EventCode": "0xCD",
33902ea4eeSAndi Kleen        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
34902ea4eeSAndi Kleen        "MSRIndex": "0x3F6",
35*2782403cSIan Rogers        "MSRValue": "0x100",
36*2782403cSIan Rogers        "PEBS": "2",
37902ea4eeSAndi Kleen        "SampleAfterValue": "503",
38*2782403cSIan Rogers        "UMask": "0x1"
39902ea4eeSAndi Kleen    },
40902ea4eeSAndi Kleen    {
41*2782403cSIan Rogers        "BriefDescription": "Loads with latency value being above 32.",
42*2782403cSIan Rogers        "EventCode": "0xCD",
43*2782403cSIan Rogers        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
44*2782403cSIan Rogers        "MSRIndex": "0x3F6",
45*2782403cSIan Rogers        "MSRValue": "0x20",
46*2782403cSIan Rogers        "PEBS": "2",
47*2782403cSIan Rogers        "SampleAfterValue": "100007",
48*2782403cSIan Rogers        "UMask": "0x1"
49*2782403cSIan Rogers    },
50*2782403cSIan Rogers    {
51*2782403cSIan Rogers        "BriefDescription": "Loads with latency value being above 4 .",
52*2782403cSIan Rogers        "EventCode": "0xCD",
53*2782403cSIan Rogers        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
54*2782403cSIan Rogers        "MSRIndex": "0x3F6",
55*2782403cSIan Rogers        "MSRValue": "0x4",
56*2782403cSIan Rogers        "PEBS": "2",
57*2782403cSIan Rogers        "SampleAfterValue": "100003",
58*2782403cSIan Rogers        "UMask": "0x1"
59*2782403cSIan Rogers    },
60*2782403cSIan Rogers    {
61*2782403cSIan Rogers        "BriefDescription": "Loads with latency value being above 512.",
62*2782403cSIan Rogers        "EventCode": "0xCD",
63902ea4eeSAndi Kleen        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
64902ea4eeSAndi Kleen        "MSRIndex": "0x3F6",
65*2782403cSIan Rogers        "MSRValue": "0x200",
66902ea4eeSAndi Kleen        "PEBS": "2",
67*2782403cSIan Rogers        "SampleAfterValue": "101",
68*2782403cSIan Rogers        "UMask": "0x1"
69902ea4eeSAndi Kleen    },
70902ea4eeSAndi Kleen    {
71*2782403cSIan Rogers        "BriefDescription": "Loads with latency value being above 64.",
72*2782403cSIan Rogers        "EventCode": "0xCD",
73*2782403cSIan Rogers        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
74*2782403cSIan Rogers        "MSRIndex": "0x3F6",
75*2782403cSIan Rogers        "MSRValue": "0x40",
76*2782403cSIan Rogers        "PEBS": "2",
77*2782403cSIan Rogers        "SampleAfterValue": "2003",
78*2782403cSIan Rogers        "UMask": "0x1"
79*2782403cSIan Rogers    },
80*2782403cSIan Rogers    {
81*2782403cSIan Rogers        "BriefDescription": "Loads with latency value being above 8.",
82*2782403cSIan Rogers        "EventCode": "0xCD",
83*2782403cSIan Rogers        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
84*2782403cSIan Rogers        "MSRIndex": "0x3F6",
85*2782403cSIan Rogers        "MSRValue": "0x8",
86*2782403cSIan Rogers        "PEBS": "2",
87*2782403cSIan Rogers        "SampleAfterValue": "50021",
88*2782403cSIan Rogers        "UMask": "0x1"
89*2782403cSIan Rogers    },
90*2782403cSIan Rogers    {
91*2782403cSIan Rogers        "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).",
92*2782403cSIan Rogers        "EventCode": "0xCD",
93*2782403cSIan Rogers        "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
94*2782403cSIan Rogers        "PEBS": "2",
95*2782403cSIan Rogers        "SampleAfterValue": "2000003",
96*2782403cSIan Rogers        "UMask": "0x2"
97*2782403cSIan Rogers    },
98*2782403cSIan Rogers    {
99*2782403cSIan Rogers        "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.",
100*2782403cSIan Rogers        "EventCode": "0x05",
101902ea4eeSAndi Kleen        "EventName": "MISALIGN_MEM_REF.LOADS",
102902ea4eeSAndi Kleen        "SampleAfterValue": "2000003",
103*2782403cSIan Rogers        "UMask": "0x1"
104902ea4eeSAndi Kleen    },
105902ea4eeSAndi Kleen    {
106*2782403cSIan Rogers        "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.",
107*2782403cSIan Rogers        "EventCode": "0x05",
108902ea4eeSAndi Kleen        "EventName": "MISALIGN_MEM_REF.STORES",
109902ea4eeSAndi Kleen        "SampleAfterValue": "2000003",
110*2782403cSIan Rogers        "UMask": "0x2"
111902ea4eeSAndi Kleen    },
112902ea4eeSAndi Kleen    {
113*2782403cSIan Rogers        "BriefDescription": "This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded.",
114902ea4eeSAndi Kleen        "EventCode": "0xB7, 0xBB",
115902ea4eeSAndi Kleen        "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.ANY_RESPONSE",
116902ea4eeSAndi Kleen        "MSRIndex": "0x1a6,0x1a7",
117*2782403cSIan Rogers        "MSRValue": "0x3FFFC20077",
118902ea4eeSAndi Kleen        "SampleAfterValue": "100003",
119*2782403cSIan Rogers        "UMask": "0x1"
120902ea4eeSAndi Kleen    },
121902ea4eeSAndi Kleen    {
122*2782403cSIan Rogers        "BriefDescription": "Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded.",
123*2782403cSIan Rogers        "EventCode": "0xB7, 0xBB",
124*2782403cSIan Rogers        "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.LOCAL_DRAM",
125*2782403cSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
126*2782403cSIan Rogers        "MSRValue": "0x600400077",
127*2782403cSIan Rogers        "SampleAfterValue": "100003",
128*2782403cSIan Rogers        "UMask": "0x1"
129*2782403cSIan Rogers    },
130*2782403cSIan Rogers    {
131*2782403cSIan Rogers        "BriefDescription": "This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded.",
132*2782403cSIan Rogers        "EventCode": "0xB7, 0xBB",
133902ea4eeSAndi Kleen        "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.REMOTE_HITM_HIT_FORWARD",
134902ea4eeSAndi Kleen        "MSRIndex": "0x1a6,0x1a7",
135*2782403cSIan Rogers        "MSRValue": "0x187FC20077",
136902ea4eeSAndi Kleen        "SampleAfterValue": "100003",
137*2782403cSIan Rogers        "UMask": "0x1"
138*2782403cSIan Rogers    },
139*2782403cSIan Rogers    {
140*2782403cSIan Rogers        "BriefDescription": "Counts all demand code reads that miss the LLC",
141*2782403cSIan Rogers        "EventCode": "0xB7, 0xBB",
142*2782403cSIan Rogers        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",
143*2782403cSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
144*2782403cSIan Rogers        "MSRValue": "0x3fffc20004",
145*2782403cSIan Rogers        "SampleAfterValue": "100003",
146*2782403cSIan Rogers        "UMask": "0x1"
147*2782403cSIan Rogers    },
148*2782403cSIan Rogers    {
149*2782403cSIan Rogers        "BriefDescription": "Counts all demand code reads that miss the LLC  and the data returned from local dram",
150*2782403cSIan Rogers        "EventCode": "0xB7, 0xBB",
151*2782403cSIan Rogers        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",
152*2782403cSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
153*2782403cSIan Rogers        "MSRValue": "0x600400004",
154*2782403cSIan Rogers        "SampleAfterValue": "100003",
155*2782403cSIan Rogers        "UMask": "0x1"
156*2782403cSIan Rogers    },
157*2782403cSIan Rogers    {
158*2782403cSIan Rogers        "BriefDescription": "Counts all demand code reads that miss the LLC  and the data returned from remote dram",
159*2782403cSIan Rogers        "EventCode": "0xB7, 0xBB",
160*2782403cSIan Rogers        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM",
161*2782403cSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
162*2782403cSIan Rogers        "MSRValue": "0x67f800004",
163*2782403cSIan Rogers        "SampleAfterValue": "100003",
164*2782403cSIan Rogers        "UMask": "0x1"
165*2782403cSIan Rogers    },
166*2782403cSIan Rogers    {
167*2782403cSIan Rogers        "BriefDescription": "Counts all demand code reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",
168*2782403cSIan Rogers        "EventCode": "0xB7, 0xBB",
169*2782403cSIan Rogers        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM",
170*2782403cSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
171*2782403cSIan Rogers        "MSRValue": "0x107fc00004",
172*2782403cSIan Rogers        "SampleAfterValue": "100003",
173*2782403cSIan Rogers        "UMask": "0x1"
174*2782403cSIan Rogers    },
175*2782403cSIan Rogers    {
176*2782403cSIan Rogers        "BriefDescription": "Counts all demand code reads that miss the LLC  and the data forwarded from remote cache",
177*2782403cSIan Rogers        "EventCode": "0xB7, 0xBB",
178*2782403cSIan Rogers        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD",
179*2782403cSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
180*2782403cSIan Rogers        "MSRValue": "0x87f820004",
181*2782403cSIan Rogers        "SampleAfterValue": "100003",
182*2782403cSIan Rogers        "UMask": "0x1"
183*2782403cSIan Rogers    },
184*2782403cSIan Rogers    {
185*2782403cSIan Rogers        "BriefDescription": "Counts demand data reads that miss the LLC  and the data returned from remote & local dram",
186*2782403cSIan Rogers        "EventCode": "0xB7, 0xBB",
187*2782403cSIan Rogers        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM",
188*2782403cSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
189*2782403cSIan Rogers        "MSRValue": "0x67fc00001",
190*2782403cSIan Rogers        "SampleAfterValue": "100003",
191*2782403cSIan Rogers        "UMask": "0x1"
192*2782403cSIan Rogers    },
193*2782403cSIan Rogers    {
194*2782403cSIan Rogers        "BriefDescription": "Counts demand data reads that miss in the LLC",
195*2782403cSIan Rogers        "EventCode": "0xB7, 0xBB",
196*2782403cSIan Rogers        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",
197*2782403cSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
198*2782403cSIan Rogers        "MSRValue": "0x3fffc20001",
199*2782403cSIan Rogers        "SampleAfterValue": "100003",
200*2782403cSIan Rogers        "UMask": "0x1"
201*2782403cSIan Rogers    },
202*2782403cSIan Rogers    {
203*2782403cSIan Rogers        "BriefDescription": "Counts demand data reads that miss the LLC  and the data returned from local dram",
204*2782403cSIan Rogers        "EventCode": "0xB7, 0xBB",
205*2782403cSIan Rogers        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",
206*2782403cSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
207*2782403cSIan Rogers        "MSRValue": "0x600400001",
208*2782403cSIan Rogers        "SampleAfterValue": "100003",
209*2782403cSIan Rogers        "UMask": "0x1"
210*2782403cSIan Rogers    },
211*2782403cSIan Rogers    {
212*2782403cSIan Rogers        "BriefDescription": "Counts demand data reads that miss the LLC  and the data returned from remote dram",
213*2782403cSIan Rogers        "EventCode": "0xB7, 0xBB",
214*2782403cSIan Rogers        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM",
215*2782403cSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
216*2782403cSIan Rogers        "MSRValue": "0x67f800001",
217*2782403cSIan Rogers        "SampleAfterValue": "100003",
218*2782403cSIan Rogers        "UMask": "0x1"
219*2782403cSIan Rogers    },
220*2782403cSIan Rogers    {
221*2782403cSIan Rogers        "BriefDescription": "Counts demand data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",
222*2782403cSIan Rogers        "EventCode": "0xB7, 0xBB",
223*2782403cSIan Rogers        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM",
224*2782403cSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
225*2782403cSIan Rogers        "MSRValue": "0x107fc00001",
226*2782403cSIan Rogers        "SampleAfterValue": "100003",
227*2782403cSIan Rogers        "UMask": "0x1"
228*2782403cSIan Rogers    },
229*2782403cSIan Rogers    {
230*2782403cSIan Rogers        "BriefDescription": "Counts demand data reads that miss the LLC  and the data forwarded from remote cache",
231*2782403cSIan Rogers        "EventCode": "0xB7, 0xBB",
232*2782403cSIan Rogers        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
233*2782403cSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
234*2782403cSIan Rogers        "MSRValue": "0x87f820001",
235*2782403cSIan Rogers        "SampleAfterValue": "100003",
236*2782403cSIan Rogers        "UMask": "0x1"
237*2782403cSIan Rogers    },
238*2782403cSIan Rogers    {
239*2782403cSIan Rogers        "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from remote & local dram",
240*2782403cSIan Rogers        "EventCode": "0xB7, 0xBB",
241*2782403cSIan Rogers        "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",
242*2782403cSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
243*2782403cSIan Rogers        "MSRValue": "0x3fffc20040",
244*2782403cSIan Rogers        "SampleAfterValue": "100003",
245*2782403cSIan Rogers        "UMask": "0x1"
246*2782403cSIan Rogers    },
247*2782403cSIan Rogers    {
248*2782403cSIan Rogers        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from remote & local dram",
249*2782403cSIan Rogers        "EventCode": "0xB7, 0xBB",
250*2782403cSIan Rogers        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM",
251*2782403cSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
252*2782403cSIan Rogers        "MSRValue": "0x67fc00010",
253*2782403cSIan Rogers        "SampleAfterValue": "100003",
254*2782403cSIan Rogers        "UMask": "0x1"
255*2782403cSIan Rogers    },
256*2782403cSIan Rogers    {
257*2782403cSIan Rogers        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC",
258*2782403cSIan Rogers        "EventCode": "0xB7, 0xBB",
259*2782403cSIan Rogers        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",
260*2782403cSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
261*2782403cSIan Rogers        "MSRValue": "0x3fffc20010",
262*2782403cSIan Rogers        "SampleAfterValue": "100003",
263*2782403cSIan Rogers        "UMask": "0x1"
264*2782403cSIan Rogers    },
265*2782403cSIan Rogers    {
266*2782403cSIan Rogers        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from local dram",
267*2782403cSIan Rogers        "EventCode": "0xB7, 0xBB",
268*2782403cSIan Rogers        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM",
269*2782403cSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
270*2782403cSIan Rogers        "MSRValue": "0x600400010",
271*2782403cSIan Rogers        "SampleAfterValue": "100003",
272*2782403cSIan Rogers        "UMask": "0x1"
273*2782403cSIan Rogers    },
274*2782403cSIan Rogers    {
275*2782403cSIan Rogers        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  that miss the LLC  and the data returned from remote dram",
276*2782403cSIan Rogers        "EventCode": "0xB7, 0xBB",
277*2782403cSIan Rogers        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM",
278*2782403cSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
279*2782403cSIan Rogers        "MSRValue": "0x67f800010",
280*2782403cSIan Rogers        "SampleAfterValue": "100003",
281*2782403cSIan Rogers        "UMask": "0x1"
282*2782403cSIan Rogers    },
283*2782403cSIan Rogers    {
284*2782403cSIan Rogers        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",
285*2782403cSIan Rogers        "EventCode": "0xB7, 0xBB",
286*2782403cSIan Rogers        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM",
287*2782403cSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
288*2782403cSIan Rogers        "MSRValue": "0x107fc00010",
289*2782403cSIan Rogers        "SampleAfterValue": "100003",
290*2782403cSIan Rogers        "UMask": "0x1"
291*2782403cSIan Rogers    },
292*2782403cSIan Rogers    {
293*2782403cSIan Rogers        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data forwarded from remote cache",
294*2782403cSIan Rogers        "EventCode": "0xB7, 0xBB",
295*2782403cSIan Rogers        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
296*2782403cSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
297*2782403cSIan Rogers        "MSRValue": "0x87f820010",
298*2782403cSIan Rogers        "SampleAfterValue": "100003",
299*2782403cSIan Rogers        "UMask": "0x1"
300*2782403cSIan Rogers    },
301*2782403cSIan Rogers    {
302*2782403cSIan Rogers        "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC",
303*2782403cSIan Rogers        "EventCode": "0xB7, 0xBB",
304*2782403cSIan Rogers        "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
305*2782403cSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
306*2782403cSIan Rogers        "MSRValue": "0x3fffc20200",
307*2782403cSIan Rogers        "SampleAfterValue": "100003",
308*2782403cSIan Rogers        "UMask": "0x1"
309*2782403cSIan Rogers    },
310*2782403cSIan Rogers    {
311*2782403cSIan Rogers        "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
312*2782403cSIan Rogers        "EventCode": "0xB7, 0xBB",
313*2782403cSIan Rogers        "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",
314*2782403cSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
315*2782403cSIan Rogers        "MSRValue": "0x3fffc20080",
316*2782403cSIan Rogers        "SampleAfterValue": "100003",
317*2782403cSIan Rogers        "UMask": "0x1"
318902ea4eeSAndi Kleen    }
319902ea4eeSAndi Kleen]
320