16b138c7bSAndi Kleen[ 26b138c7bSAndi Kleen { 3b90b3e9cSAndi Kleen "BriefDescription": "Memory page activates for reads and writes", 46b138c7bSAndi Kleen "Counter": "0,1,2,3", 56b138c7bSAndi Kleen "EventCode": "0x1", 66b138c7bSAndi Kleen "EventName": "UNC_M_ACT_COUNT.RD", 76b138c7bSAndi Kleen "PerPkg": "1", 8*afba2b08SIan Rogers "UMask": "0x3", 96b138c7bSAndi Kleen "Unit": "iMC" 106b138c7bSAndi Kleen }, 116b138c7bSAndi Kleen { 126b138c7bSAndi Kleen "BriefDescription": "Read requests to memory controller. Derived from unc_m_cas_count.rd", 136b138c7bSAndi Kleen "Counter": "0,1,2,3", 146b138c7bSAndi Kleen "EventCode": "0x4", 15b90b3e9cSAndi Kleen "EventName": "LLC_MISSES.MEM_READ", 166b138c7bSAndi Kleen "PerPkg": "1", 176b138c7bSAndi Kleen "ScaleUnit": "64Bytes", 186b138c7bSAndi Kleen "UMask": "0x3", 196b138c7bSAndi Kleen "Unit": "iMC" 206b138c7bSAndi Kleen }, 216b138c7bSAndi Kleen { 226b138c7bSAndi Kleen "BriefDescription": "Write requests to memory controller. Derived from unc_m_cas_count.wr", 236b138c7bSAndi Kleen "Counter": "0,1,2,3", 246b138c7bSAndi Kleen "EventCode": "0x4", 25b90b3e9cSAndi Kleen "EventName": "LLC_MISSES.MEM_WRITE", 266b138c7bSAndi Kleen "PerPkg": "1", 276b138c7bSAndi Kleen "ScaleUnit": "64Bytes", 286b138c7bSAndi Kleen "UMask": "0xC", 296b138c7bSAndi Kleen "Unit": "iMC" 306b138c7bSAndi Kleen }, 316b138c7bSAndi Kleen { 32b90b3e9cSAndi Kleen "BriefDescription": "Memory controller clock ticks. Use to generate percentages for memory controller CYCLES events", 336b138c7bSAndi Kleen "Counter": "0,1,2,3", 346b138c7bSAndi Kleen "EventName": "UNC_M_CLOCKTICKS", 356b138c7bSAndi Kleen "PerPkg": "1", 366b138c7bSAndi Kleen "Unit": "iMC" 376b138c7bSAndi Kleen }, 386b138c7bSAndi Kleen { 39b90b3e9cSAndi Kleen "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode", 406b138c7bSAndi Kleen "Counter": "0,1,2,3", 416b138c7bSAndi Kleen "EventCode": "0x85", 426b138c7bSAndi Kleen "EventName": "UNC_M_POWER_CHANNEL_PPD", 436b138c7bSAndi Kleen "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.", 44b90b3e9cSAndi Kleen "MetricName": "power_channel_ppd %", 456b138c7bSAndi Kleen "PerPkg": "1", 466b138c7bSAndi Kleen "Unit": "iMC" 476b138c7bSAndi Kleen }, 486b138c7bSAndi Kleen { 49b90b3e9cSAndi Kleen "BriefDescription": "Cycles all ranks are in critical thermal throttle", 506b138c7bSAndi Kleen "Counter": "0,1,2,3", 516b138c7bSAndi Kleen "EventCode": "0x86", 526b138c7bSAndi Kleen "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", 536b138c7bSAndi Kleen "MetricExpr": "(UNC_M_POWER_CRITICAL_THROTTLE_CYCLES / UNC_M_CLOCKTICKS) * 100.", 54b90b3e9cSAndi Kleen "MetricName": "power_critical_throttle_cycles %", 556b138c7bSAndi Kleen "PerPkg": "1", 566b138c7bSAndi Kleen "Unit": "iMC" 576b138c7bSAndi Kleen }, 586b138c7bSAndi Kleen { 59b90b3e9cSAndi Kleen "BriefDescription": "Cycles Memory is in self refresh power mode", 606b138c7bSAndi Kleen "Counter": "0,1,2,3", 616b138c7bSAndi Kleen "EventCode": "0x43", 626b138c7bSAndi Kleen "EventName": "UNC_M_POWER_SELF_REFRESH", 636b138c7bSAndi Kleen "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100.", 64b90b3e9cSAndi Kleen "MetricName": "power_self_refresh %", 656b138c7bSAndi Kleen "PerPkg": "1", 666b138c7bSAndi Kleen "Unit": "iMC" 676b138c7bSAndi Kleen }, 686b138c7bSAndi Kleen { 69b90b3e9cSAndi Kleen "BriefDescription": "Memory page conflicts", 706b138c7bSAndi Kleen "Counter": "0,1,2,3", 716b138c7bSAndi Kleen "EventCode": "0x2", 726b138c7bSAndi Kleen "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", 736b138c7bSAndi Kleen "PerPkg": "1", 746b138c7bSAndi Kleen "UMask": "0x1", 756b138c7bSAndi Kleen "Unit": "iMC" 766b138c7bSAndi Kleen } 776b138c7bSAndi Kleen] 78