1d910f0baSAndi Kleen[ 2d910f0baSAndi Kleen { 3d910f0baSAndi Kleen "PublicDescription": "Unhalted core cycles when the thread is in ring 0.", 4d910f0baSAndi Kleen "EventCode": "0x5C", 5d910f0baSAndi Kleen "Counter": "0,1,2,3", 6d910f0baSAndi Kleen "UMask": "0x1", 7d910f0baSAndi Kleen "EventName": "CPL_CYCLES.RING0", 8d910f0baSAndi Kleen "SampleAfterValue": "2000003", 9d910f0baSAndi Kleen "BriefDescription": "Unhalted core cycles when the thread is in ring 0", 10d910f0baSAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 11d910f0baSAndi Kleen }, 12d910f0baSAndi Kleen { 13d910f0baSAndi Kleen "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", 14d910f0baSAndi Kleen "EventCode": "0x5C", 15d910f0baSAndi Kleen "Counter": "0,1,2,3", 16d910f0baSAndi Kleen "UMask": "0x2", 17d910f0baSAndi Kleen "EventName": "CPL_CYCLES.RING123", 18d910f0baSAndi Kleen "SampleAfterValue": "2000003", 19d910f0baSAndi Kleen "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", 20d910f0baSAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 21d910f0baSAndi Kleen }, 22d910f0baSAndi Kleen { 23d910f0baSAndi Kleen "PublicDescription": "Number of intervals between processor halts while thread is in ring 0.", 24d910f0baSAndi Kleen "EventCode": "0x5C", 25d910f0baSAndi Kleen "Counter": "0,1,2,3", 26d910f0baSAndi Kleen "UMask": "0x1", 27d910f0baSAndi Kleen "EdgeDetect": "1", 28d910f0baSAndi Kleen "EventName": "CPL_CYCLES.RING0_TRANS", 29d910f0baSAndi Kleen "SampleAfterValue": "100007", 30d910f0baSAndi Kleen "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", 31d910f0baSAndi Kleen "CounterMask": "1", 32d910f0baSAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 33d910f0baSAndi Kleen }, 34d910f0baSAndi Kleen { 35d910f0baSAndi Kleen "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", 36d910f0baSAndi Kleen "EventCode": "0x63", 37d910f0baSAndi Kleen "Counter": "0,1,2,3", 38d910f0baSAndi Kleen "UMask": "0x1", 39d910f0baSAndi Kleen "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", 40d910f0baSAndi Kleen "SampleAfterValue": "2000003", 41d910f0baSAndi Kleen "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", 42d910f0baSAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 43d910f0baSAndi Kleen } 44d910f0baSAndi Kleen]