1d910f0baSAndi Kleen[ 2d910f0baSAndi Kleen { 3d910f0baSAndi Kleen "BriefDescription": "Unhalted core cycles when the thread is in ring 0", 4*70d90a6aSIan Rogers "Counter": "0,1,2,3", 5*70d90a6aSIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 6*70d90a6aSIan Rogers "EventCode": "0x5C", 7*70d90a6aSIan Rogers "EventName": "CPL_CYCLES.RING0", 8*70d90a6aSIan Rogers "PublicDescription": "Unhalted core cycles when the thread is in ring 0.", 9*70d90a6aSIan Rogers "SampleAfterValue": "2000003", 10*70d90a6aSIan Rogers "UMask": "0x1" 11d910f0baSAndi Kleen }, 12d910f0baSAndi Kleen { 13d910f0baSAndi Kleen "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", 14*70d90a6aSIan Rogers "Counter": "0,1,2,3", 15*70d90a6aSIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 16d910f0baSAndi Kleen "CounterMask": "1", 17*70d90a6aSIan Rogers "EdgeDetect": "1", 18194b6fa4SAndi Kleen "EventCode": "0x5C", 19*70d90a6aSIan Rogers "EventName": "CPL_CYCLES.RING0_TRANS", 20*70d90a6aSIan Rogers "PublicDescription": "Number of intervals between processor halts while thread is in ring 0.", 21*70d90a6aSIan Rogers "SampleAfterValue": "100007", 22*70d90a6aSIan Rogers "UMask": "0x1" 23194b6fa4SAndi Kleen }, 24194b6fa4SAndi Kleen { 25*70d90a6aSIan Rogers "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", 26d910f0baSAndi Kleen "Counter": "0,1,2,3", 27*70d90a6aSIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 28*70d90a6aSIan Rogers "EventCode": "0x5C", 29*70d90a6aSIan Rogers "EventName": "CPL_CYCLES.RING123", 30*70d90a6aSIan Rogers "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", 31d910f0baSAndi Kleen "SampleAfterValue": "2000003", 32*70d90a6aSIan Rogers "UMask": "0x2" 33*70d90a6aSIan Rogers }, 34*70d90a6aSIan Rogers { 35d910f0baSAndi Kleen "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", 36*70d90a6aSIan Rogers "Counter": "0,1,2,3", 37*70d90a6aSIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 38*70d90a6aSIan Rogers "EventCode": "0x63", 39*70d90a6aSIan Rogers "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", 40*70d90a6aSIan Rogers "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", 41*70d90a6aSIan Rogers "SampleAfterValue": "2000003", 42*70d90a6aSIan Rogers "UMask": "0x1" 43d910f0baSAndi Kleen } 44d910f0baSAndi Kleen]