1d910f0baSAndi Kleen[ 2d910f0baSAndi Kleen { 3d910f0baSAndi Kleen "BriefDescription": "Unhalted core cycles when the thread is in ring 0", 4*70d90a6aSIan Rogers "EventCode": "0x5C", 5*70d90a6aSIan Rogers "EventName": "CPL_CYCLES.RING0", 6*70d90a6aSIan Rogers "PublicDescription": "Unhalted core cycles when the thread is in ring 0.", 7*70d90a6aSIan Rogers "SampleAfterValue": "2000003", 8*70d90a6aSIan Rogers "UMask": "0x1" 9d910f0baSAndi Kleen }, 10d910f0baSAndi Kleen { 11d910f0baSAndi Kleen "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", 12d910f0baSAndi Kleen "CounterMask": "1", 13*70d90a6aSIan Rogers "EdgeDetect": "1", 14194b6fa4SAndi Kleen "EventCode": "0x5C", 15*70d90a6aSIan Rogers "EventName": "CPL_CYCLES.RING0_TRANS", 16*70d90a6aSIan Rogers "PublicDescription": "Number of intervals between processor halts while thread is in ring 0.", 17*70d90a6aSIan Rogers "SampleAfterValue": "100007", 18*70d90a6aSIan Rogers "UMask": "0x1" 19194b6fa4SAndi Kleen }, 20194b6fa4SAndi Kleen { 21*70d90a6aSIan Rogers "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", 22*70d90a6aSIan Rogers "EventCode": "0x5C", 23*70d90a6aSIan Rogers "EventName": "CPL_CYCLES.RING123", 24*70d90a6aSIan Rogers "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", 25d910f0baSAndi Kleen "SampleAfterValue": "2000003", 26*70d90a6aSIan Rogers "UMask": "0x2" 27*70d90a6aSIan Rogers }, 28*70d90a6aSIan Rogers { 29d910f0baSAndi Kleen "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", 30*70d90a6aSIan Rogers "EventCode": "0x63", 31*70d90a6aSIan Rogers "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", 32*70d90a6aSIan Rogers "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", 33*70d90a6aSIan Rogers "SampleAfterValue": "2000003", 34*70d90a6aSIan Rogers "UMask": "0x1" 35d910f0baSAndi Kleen } 36d910f0baSAndi Kleen] 37