1[
2    {
3        "BriefDescription": "L1D data line replacements",
4        "EventCode": "0x51",
5        "EventName": "L1D.REPLACEMENT",
6        "PublicDescription": "Counts the number of lines brought into the L1 data cache.",
7        "SampleAfterValue": "2000003",
8        "UMask": "0x1"
9    },
10    {
11        "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",
12        "CounterMask": "1",
13        "EventCode": "0x48",
14        "EventName": "L1D_PEND_MISS.FB_FULL",
15        "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
16        "SampleAfterValue": "2000003",
17        "UMask": "0x2"
18    },
19    {
20        "BriefDescription": "L1D miss outstanding duration in cycles",
21        "EventCode": "0x48",
22        "EventName": "L1D_PEND_MISS.PENDING",
23        "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
24        "SampleAfterValue": "2000003",
25        "UMask": "0x1"
26    },
27    {
28        "BriefDescription": "Cycles with L1D load Misses outstanding.",
29        "CounterMask": "1",
30        "EventCode": "0x48",
31        "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
32        "SampleAfterValue": "2000003",
33        "UMask": "0x1"
34    },
35    {
36        "AnyThread": "1",
37        "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",
38        "CounterMask": "1",
39        "EventCode": "0x48",
40        "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
41        "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
42        "SampleAfterValue": "2000003",
43        "UMask": "0x1"
44    },
45    {
46        "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
47        "EventCode": "0x28",
48        "EventName": "L2_L1D_WB_RQSTS.ALL",
49        "SampleAfterValue": "200003",
50        "UMask": "0xf"
51    },
52    {
53        "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
54        "EventCode": "0x28",
55        "EventName": "L2_L1D_WB_RQSTS.HIT_E",
56        "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
57        "SampleAfterValue": "200003",
58        "UMask": "0x4"
59    },
60    {
61        "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
62        "EventCode": "0x28",
63        "EventName": "L2_L1D_WB_RQSTS.HIT_M",
64        "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
65        "SampleAfterValue": "200003",
66        "UMask": "0x8"
67    },
68    {
69        "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)",
70        "EventCode": "0x28",
71        "EventName": "L2_L1D_WB_RQSTS.MISS",
72        "PublicDescription": "Not rejected writebacks that missed LLC.",
73        "SampleAfterValue": "200003",
74        "UMask": "0x1"
75    },
76    {
77        "BriefDescription": "L2 cache lines filling L2",
78        "EventCode": "0xF1",
79        "EventName": "L2_LINES_IN.ALL",
80        "PublicDescription": "L2 cache lines filling L2.",
81        "SampleAfterValue": "100003",
82        "UMask": "0x7"
83    },
84    {
85        "BriefDescription": "L2 cache lines in E state filling L2",
86        "EventCode": "0xF1",
87        "EventName": "L2_LINES_IN.E",
88        "PublicDescription": "L2 cache lines in E state filling L2.",
89        "SampleAfterValue": "100003",
90        "UMask": "0x4"
91    },
92    {
93        "BriefDescription": "L2 cache lines in I state filling L2",
94        "EventCode": "0xF1",
95        "EventName": "L2_LINES_IN.I",
96        "PublicDescription": "L2 cache lines in I state filling L2.",
97        "SampleAfterValue": "100003",
98        "UMask": "0x1"
99    },
100    {
101        "BriefDescription": "L2 cache lines in S state filling L2",
102        "EventCode": "0xF1",
103        "EventName": "L2_LINES_IN.S",
104        "PublicDescription": "L2 cache lines in S state filling L2.",
105        "SampleAfterValue": "100003",
106        "UMask": "0x2"
107    },
108    {
109        "BriefDescription": "Clean L2 cache lines evicted by demand",
110        "EventCode": "0xF2",
111        "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
112        "PublicDescription": "Clean L2 cache lines evicted by demand.",
113        "SampleAfterValue": "100003",
114        "UMask": "0x1"
115    },
116    {
117        "BriefDescription": "Dirty L2 cache lines evicted by demand",
118        "EventCode": "0xF2",
119        "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
120        "PublicDescription": "Dirty L2 cache lines evicted by demand.",
121        "SampleAfterValue": "100003",
122        "UMask": "0x2"
123    },
124    {
125        "BriefDescription": "Dirty L2 cache lines filling the L2",
126        "EventCode": "0xF2",
127        "EventName": "L2_LINES_OUT.DIRTY_ALL",
128        "PublicDescription": "Dirty L2 cache lines filling the L2.",
129        "SampleAfterValue": "100003",
130        "UMask": "0xa"
131    },
132    {
133        "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch",
134        "EventCode": "0xF2",
135        "EventName": "L2_LINES_OUT.PF_CLEAN",
136        "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.",
137        "SampleAfterValue": "100003",
138        "UMask": "0x4"
139    },
140    {
141        "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch",
142        "EventCode": "0xF2",
143        "EventName": "L2_LINES_OUT.PF_DIRTY",
144        "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.",
145        "SampleAfterValue": "100003",
146        "UMask": "0x8"
147    },
148    {
149        "BriefDescription": "L2 code requests",
150        "EventCode": "0x24",
151        "EventName": "L2_RQSTS.ALL_CODE_RD",
152        "PublicDescription": "Counts all L2 code requests.",
153        "SampleAfterValue": "200003",
154        "UMask": "0x30"
155    },
156    {
157        "BriefDescription": "Demand Data Read requests",
158        "EventCode": "0x24",
159        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
160        "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
161        "SampleAfterValue": "200003",
162        "UMask": "0x3"
163    },
164    {
165        "BriefDescription": "Requests from L2 hardware prefetchers",
166        "EventCode": "0x24",
167        "EventName": "L2_RQSTS.ALL_PF",
168        "PublicDescription": "Counts all L2 HW prefetcher requests.",
169        "SampleAfterValue": "200003",
170        "UMask": "0xc0"
171    },
172    {
173        "BriefDescription": "RFO requests to L2 cache",
174        "EventCode": "0x24",
175        "EventName": "L2_RQSTS.ALL_RFO",
176        "PublicDescription": "Counts all L2 store RFO requests.",
177        "SampleAfterValue": "200003",
178        "UMask": "0xc"
179    },
180    {
181        "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
182        "EventCode": "0x24",
183        "EventName": "L2_RQSTS.CODE_RD_HIT",
184        "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
185        "SampleAfterValue": "200003",
186        "UMask": "0x10"
187    },
188    {
189        "BriefDescription": "L2 cache misses when fetching instructions",
190        "EventCode": "0x24",
191        "EventName": "L2_RQSTS.CODE_RD_MISS",
192        "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
193        "SampleAfterValue": "200003",
194        "UMask": "0x20"
195    },
196    {
197        "BriefDescription": "Demand Data Read requests that hit L2 cache",
198        "EventCode": "0x24",
199        "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
200        "PublicDescription": "Demand Data Read requests that hit L2 cache.",
201        "SampleAfterValue": "200003",
202        "UMask": "0x1"
203    },
204    {
205        "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",
206        "EventCode": "0x24",
207        "EventName": "L2_RQSTS.PF_HIT",
208        "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
209        "SampleAfterValue": "200003",
210        "UMask": "0x40"
211    },
212    {
213        "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",
214        "EventCode": "0x24",
215        "EventName": "L2_RQSTS.PF_MISS",
216        "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
217        "SampleAfterValue": "200003",
218        "UMask": "0x80"
219    },
220    {
221        "BriefDescription": "RFO requests that hit L2 cache",
222        "EventCode": "0x24",
223        "EventName": "L2_RQSTS.RFO_HIT",
224        "PublicDescription": "RFO requests that hit L2 cache.",
225        "SampleAfterValue": "200003",
226        "UMask": "0x4"
227    },
228    {
229        "BriefDescription": "RFO requests that miss L2 cache",
230        "EventCode": "0x24",
231        "EventName": "L2_RQSTS.RFO_MISS",
232        "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
233        "SampleAfterValue": "200003",
234        "UMask": "0x8"
235    },
236    {
237        "BriefDescription": "RFOs that access cache lines in any state",
238        "EventCode": "0x27",
239        "EventName": "L2_STORE_LOCK_RQSTS.ALL",
240        "PublicDescription": "RFOs that access cache lines in any state.",
241        "SampleAfterValue": "200003",
242        "UMask": "0xf"
243    },
244    {
245        "BriefDescription": "RFOs that hit cache lines in M state",
246        "EventCode": "0x27",
247        "EventName": "L2_STORE_LOCK_RQSTS.HIT_M",
248        "PublicDescription": "RFOs that hit cache lines in M state.",
249        "SampleAfterValue": "200003",
250        "UMask": "0x8"
251    },
252    {
253        "BriefDescription": "RFOs that miss cache lines",
254        "EventCode": "0x27",
255        "EventName": "L2_STORE_LOCK_RQSTS.MISS",
256        "PublicDescription": "RFOs that miss cache lines.",
257        "SampleAfterValue": "200003",
258        "UMask": "0x1"
259    },
260    {
261        "BriefDescription": "L2 or LLC HW prefetches that access L2 cache",
262        "EventCode": "0xF0",
263        "EventName": "L2_TRANS.ALL_PF",
264        "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.",
265        "SampleAfterValue": "200003",
266        "UMask": "0x8"
267    },
268    {
269        "BriefDescription": "Transactions accessing L2 pipe",
270        "EventCode": "0xF0",
271        "EventName": "L2_TRANS.ALL_REQUESTS",
272        "PublicDescription": "Transactions accessing L2 pipe.",
273        "SampleAfterValue": "200003",
274        "UMask": "0x80"
275    },
276    {
277        "BriefDescription": "L2 cache accesses when fetching instructions",
278        "EventCode": "0xF0",
279        "EventName": "L2_TRANS.CODE_RD",
280        "PublicDescription": "L2 cache accesses when fetching instructions.",
281        "SampleAfterValue": "200003",
282        "UMask": "0x4"
283    },
284    {
285        "BriefDescription": "Demand Data Read requests that access L2 cache",
286        "EventCode": "0xF0",
287        "EventName": "L2_TRANS.DEMAND_DATA_RD",
288        "PublicDescription": "Demand Data Read requests that access L2 cache.",
289        "SampleAfterValue": "200003",
290        "UMask": "0x1"
291    },
292    {
293        "BriefDescription": "L1D writebacks that access L2 cache",
294        "EventCode": "0xF0",
295        "EventName": "L2_TRANS.L1D_WB",
296        "PublicDescription": "L1D writebacks that access L2 cache.",
297        "SampleAfterValue": "200003",
298        "UMask": "0x10"
299    },
300    {
301        "BriefDescription": "L2 fill requests that access L2 cache",
302        "EventCode": "0xF0",
303        "EventName": "L2_TRANS.L2_FILL",
304        "PublicDescription": "L2 fill requests that access L2 cache.",
305        "SampleAfterValue": "200003",
306        "UMask": "0x20"
307    },
308    {
309        "BriefDescription": "L2 writebacks that access L2 cache",
310        "EventCode": "0xF0",
311        "EventName": "L2_TRANS.L2_WB",
312        "PublicDescription": "L2 writebacks that access L2 cache.",
313        "SampleAfterValue": "200003",
314        "UMask": "0x40"
315    },
316    {
317        "BriefDescription": "RFO requests that access L2 cache",
318        "EventCode": "0xF0",
319        "EventName": "L2_TRANS.RFO",
320        "PublicDescription": "RFO requests that access L2 cache.",
321        "SampleAfterValue": "200003",
322        "UMask": "0x2"
323    },
324    {
325        "BriefDescription": "Cycles when L1D is locked",
326        "EventCode": "0x63",
327        "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
328        "PublicDescription": "Cycles in which the L1D is locked.",
329        "SampleAfterValue": "2000003",
330        "UMask": "0x2"
331    },
332    {
333        "BriefDescription": "Core-originated cacheable demand requests missed LLC",
334        "EventCode": "0x2E",
335        "EventName": "LONGEST_LAT_CACHE.MISS",
336        "PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
337        "SampleAfterValue": "100003",
338        "UMask": "0x41"
339    },
340    {
341        "BriefDescription": "Core-originated cacheable demand requests that refer to LLC",
342        "EventCode": "0x2E",
343        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
344        "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
345        "SampleAfterValue": "100003",
346        "UMask": "0x4f"
347    },
348    {
349        "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.",
350        "EventCode": "0xD2",
351        "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",
352        "PEBS": "1",
353        "SampleAfterValue": "20011",
354        "UMask": "0x2"
355    },
356    {
357        "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.",
358        "EventCode": "0xD2",
359        "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",
360        "PEBS": "1",
361        "SampleAfterValue": "20011",
362        "UMask": "0x4"
363    },
364    {
365        "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.",
366        "EventCode": "0xD2",
367        "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",
368        "PEBS": "1",
369        "SampleAfterValue": "20011",
370        "UMask": "0x1"
371    },
372    {
373        "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.",
374        "EventCode": "0xD2",
375        "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",
376        "PEBS": "1",
377        "SampleAfterValue": "100003",
378        "UMask": "0x8"
379    },
380    {
381        "BriefDescription": "Retired load uops whose data source was local DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).",
382        "EventCode": "0xD3",
383        "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",
384        "SampleAfterValue": "100007",
385        "UMask": "0x3"
386    },
387    {
388        "BriefDescription": "Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).",
389        "EventCode": "0xD3",
390        "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM",
391        "SampleAfterValue": "100007",
392        "UMask": "0xc"
393    },
394    {
395        "BriefDescription": "Data forwarded from remote cache.",
396        "EventCode": "0xD3",
397        "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD",
398        "SampleAfterValue": "100007",
399        "UMask": "0x20"
400    },
401    {
402        "BriefDescription": "Remote cache HITM.",
403        "EventCode": "0xD3",
404        "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM",
405        "SampleAfterValue": "100007",
406        "UMask": "0x10"
407    },
408    {
409        "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
410        "EventCode": "0xD1",
411        "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
412        "PEBS": "1",
413        "SampleAfterValue": "100003",
414        "UMask": "0x40"
415    },
416    {
417        "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
418        "EventCode": "0xD1",
419        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
420        "PEBS": "1",
421        "SampleAfterValue": "2000003",
422        "UMask": "0x1"
423    },
424    {
425        "BriefDescription": "Retired load uops which data sources following L1 data-cache miss.",
426        "EventCode": "0xD1",
427        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
428        "PEBS": "1",
429        "SampleAfterValue": "100003",
430        "UMask": "0x8"
431    },
432    {
433        "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
434        "EventCode": "0xD1",
435        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
436        "PEBS": "1",
437        "SampleAfterValue": "100003",
438        "UMask": "0x2"
439    },
440    {
441        "BriefDescription": "Retired load uops with L2 cache misses as data sources.",
442        "EventCode": "0xD1",
443        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
444        "PEBS": "1",
445        "SampleAfterValue": "50021",
446        "UMask": "0x10"
447    },
448    {
449        "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.",
450        "EventCode": "0xD1",
451        "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",
452        "PEBS": "1",
453        "SampleAfterValue": "50021",
454        "UMask": "0x4"
455    },
456    {
457        "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
458        "EventCode": "0xD1",
459        "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS",
460        "PEBS": "1",
461        "SampleAfterValue": "100007",
462        "UMask": "0x20"
463    },
464    {
465        "BriefDescription": "All retired load uops. (Precise Event)",
466        "EventCode": "0xD0",
467        "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
468        "PEBS": "1",
469        "SampleAfterValue": "2000003",
470        "UMask": "0x81"
471    },
472    {
473        "BriefDescription": "All retired store uops. (Precise Event)",
474        "EventCode": "0xD0",
475        "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
476        "PEBS": "1",
477        "SampleAfterValue": "2000003",
478        "UMask": "0x82"
479    },
480    {
481        "BriefDescription": "Retired load uops with locked access. (Precise Event)",
482        "EventCode": "0xD0",
483        "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
484        "PEBS": "1",
485        "SampleAfterValue": "100007",
486        "UMask": "0x21"
487    },
488    {
489        "BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event)",
490        "EventCode": "0xD0",
491        "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
492        "PEBS": "1",
493        "SampleAfterValue": "100003",
494        "UMask": "0x41"
495    },
496    {
497        "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event)",
498        "EventCode": "0xD0",
499        "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
500        "PEBS": "1",
501        "SampleAfterValue": "100003",
502        "UMask": "0x42"
503    },
504    {
505        "BriefDescription": "Retired load uops that miss the STLB. (Precise Event)",
506        "EventCode": "0xD0",
507        "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
508        "PEBS": "1",
509        "SampleAfterValue": "100003",
510        "UMask": "0x11"
511    },
512    {
513        "BriefDescription": "Retired store uops that miss the STLB. (Precise Event)",
514        "EventCode": "0xD0",
515        "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
516        "PEBS": "1",
517        "SampleAfterValue": "100003",
518        "UMask": "0x12"
519    },
520    {
521        "BriefDescription": "Demand and prefetch data reads",
522        "EventCode": "0xB0",
523        "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
524        "PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
525        "SampleAfterValue": "100003",
526        "UMask": "0x8"
527    },
528    {
529        "BriefDescription": "Cacheable and noncacheable code read requests",
530        "EventCode": "0xB0",
531        "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
532        "PublicDescription": "Demand code read requests sent to uncore.",
533        "SampleAfterValue": "100003",
534        "UMask": "0x2"
535    },
536    {
537        "BriefDescription": "Demand Data Read requests sent to uncore",
538        "EventCode": "0xB0",
539        "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
540        "PublicDescription": "Demand data read requests sent to uncore.",
541        "SampleAfterValue": "100003",
542        "UMask": "0x1"
543    },
544    {
545        "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
546        "EventCode": "0xB0",
547        "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
548        "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
549        "SampleAfterValue": "100003",
550        "UMask": "0x4"
551    },
552    {
553        "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core",
554        "EventCode": "0xB2",
555        "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
556        "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.",
557        "SampleAfterValue": "2000003",
558        "UMask": "0x1"
559    },
560    {
561        "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
562        "EventCode": "0x60",
563        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
564        "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
565        "SampleAfterValue": "2000003",
566        "UMask": "0x8"
567    },
568    {
569        "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
570        "CounterMask": "1",
571        "EventCode": "0x60",
572        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
573        "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
574        "SampleAfterValue": "2000003",
575        "UMask": "0x8"
576    },
577    {
578        "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
579        "CounterMask": "1",
580        "EventCode": "0x60",
581        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
582        "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
583        "SampleAfterValue": "2000003",
584        "UMask": "0x2"
585    },
586    {
587        "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
588        "CounterMask": "1",
589        "EventCode": "0x60",
590        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
591        "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
592        "SampleAfterValue": "2000003",
593        "UMask": "0x1"
594    },
595    {
596        "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
597        "CounterMask": "1",
598        "EventCode": "0x60",
599        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
600        "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
601        "SampleAfterValue": "2000003",
602        "UMask": "0x4"
603    },
604    {
605        "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
606        "EventCode": "0x60",
607        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
608        "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
609        "SampleAfterValue": "2000003",
610        "UMask": "0x2"
611    },
612    {
613        "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
614        "EventCode": "0x60",
615        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
616        "PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
617        "SampleAfterValue": "2000003",
618        "UMask": "0x1"
619    },
620    {
621        "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",
622        "CounterMask": "6",
623        "EventCode": "0x60",
624        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
625        "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
626        "SampleAfterValue": "2000003",
627        "UMask": "0x1"
628    },
629    {
630        "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
631        "EventCode": "0x60",
632        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
633        "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",
634        "SampleAfterValue": "2000003",
635        "UMask": "0x4"
636    },
637    {
638        "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
639        "EventCode": "0xB7, 0xBB",
640        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
641        "MSRIndex": "0x1a6,0x1a7",
642        "MSRValue": "0x10003c0091",
643        "SampleAfterValue": "100003",
644        "UMask": "0x1"
645    },
646    {
647        "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
648        "EventCode": "0xB7, 0xBB",
649        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
650        "MSRIndex": "0x1a6,0x1a7",
651        "MSRValue": "0x4003c0091",
652        "SampleAfterValue": "100003",
653        "UMask": "0x1"
654    },
655    {
656        "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
657        "EventCode": "0xB7, 0xBB",
658        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
659        "MSRIndex": "0x1a6,0x1a7",
660        "MSRValue": "0x1003c0091",
661        "SampleAfterValue": "100003",
662        "UMask": "0x1"
663    },
664    {
665        "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
666        "EventCode": "0xB7, 0xBB",
667        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS",
668        "MSRIndex": "0x1a6,0x1a7",
669        "MSRValue": "0x2003c0091",
670        "SampleAfterValue": "100003",
671        "UMask": "0x1"
672    },
673    {
674        "BriefDescription": "Counts all prefetch data reads that hit the LLC",
675        "EventCode": "0xB7, 0xBB",
676        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE",
677        "MSRIndex": "0x1a6,0x1a7",
678        "MSRValue": "0x3f803c0090",
679        "SampleAfterValue": "100003",
680        "UMask": "0x1"
681    },
682    {
683        "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
684        "EventCode": "0xB7, 0xBB",
685        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
686        "MSRIndex": "0x1a6,0x1a7",
687        "MSRValue": "0x10003c0090",
688        "SampleAfterValue": "100003",
689        "UMask": "0x1"
690    },
691    {
692        "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
693        "EventCode": "0xB7, 0xBB",
694        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
695        "MSRIndex": "0x1a6,0x1a7",
696        "MSRValue": "0x4003c0090",
697        "SampleAfterValue": "100003",
698        "UMask": "0x1"
699    },
700    {
701        "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
702        "EventCode": "0xB7, 0xBB",
703        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
704        "MSRIndex": "0x1a6,0x1a7",
705        "MSRValue": "0x1003c0090",
706        "SampleAfterValue": "100003",
707        "UMask": "0x1"
708    },
709    {
710        "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
711        "EventCode": "0xB7, 0xBB",
712        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS",
713        "MSRIndex": "0x1a6,0x1a7",
714        "MSRValue": "0x2003c0090",
715        "SampleAfterValue": "100003",
716        "UMask": "0x1"
717    },
718    {
719        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC",
720        "EventCode": "0xB7, 0xBB",
721        "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE",
722        "MSRIndex": "0x1a6,0x1a7",
723        "MSRValue": "0x3f803c03f7",
724        "SampleAfterValue": "100003",
725        "UMask": "0x1"
726    },
727    {
728        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
729        "EventCode": "0xB7, 0xBB",
730        "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
731        "MSRIndex": "0x1a6,0x1a7",
732        "MSRValue": "0x10003c03f7",
733        "SampleAfterValue": "100003",
734        "UMask": "0x1"
735    },
736    {
737        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
738        "EventCode": "0xB7, 0xBB",
739        "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
740        "MSRIndex": "0x1a6,0x1a7",
741        "MSRValue": "0x4003c03f7",
742        "SampleAfterValue": "100003",
743        "UMask": "0x1"
744    },
745    {
746        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
747        "EventCode": "0xB7, 0xBB",
748        "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED",
749        "MSRIndex": "0x1a6,0x1a7",
750        "MSRValue": "0x1003c03f7",
751        "SampleAfterValue": "100003",
752        "UMask": "0x1"
753    },
754    {
755        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response",
756        "EventCode": "0xB7, 0xBB",
757        "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS",
758        "MSRIndex": "0x1a6,0x1a7",
759        "MSRValue": "0x2003c03f7",
760        "SampleAfterValue": "100003",
761        "UMask": "0x1"
762    },
763    {
764        "BriefDescription": "Counts all writebacks from the core to the LLC",
765        "EventCode": "0xB7, 0xBB",
766        "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
767        "MSRIndex": "0x1a6,0x1a7",
768        "MSRValue": "0x10008",
769        "SampleAfterValue": "100003",
770        "UMask": "0x1"
771    },
772    {
773        "BriefDescription": "Counts all demand code reads that hit in the LLC",
774        "EventCode": "0xB7, 0xBB",
775        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
776        "MSRIndex": "0x1a6,0x1a7",
777        "MSRValue": "0x3f803c0004",
778        "SampleAfterValue": "100003",
779        "UMask": "0x1"
780    },
781    {
782        "BriefDescription": "Counts all demand data reads that hit in the LLC",
783        "EventCode": "0xB7, 0xBB",
784        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
785        "MSRIndex": "0x1a6,0x1a7",
786        "MSRValue": "0x3f803c0001",
787        "SampleAfterValue": "100003",
788        "UMask": "0x1"
789    },
790    {
791        "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
792        "EventCode": "0xB7, 0xBB",
793        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
794        "MSRIndex": "0x1a6,0x1a7",
795        "MSRValue": "0x10003c0001",
796        "SampleAfterValue": "100003",
797        "UMask": "0x1"
798    },
799    {
800        "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
801        "EventCode": "0xB7, 0xBB",
802        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
803        "MSRIndex": "0x1a6,0x1a7",
804        "MSRValue": "0x4003c0001",
805        "SampleAfterValue": "100003",
806        "UMask": "0x1"
807    },
808    {
809        "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
810        "EventCode": "0xB7, 0xBB",
811        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
812        "MSRIndex": "0x1a6,0x1a7",
813        "MSRValue": "0x1003c0001",
814        "SampleAfterValue": "100003",
815        "UMask": "0x1"
816    },
817    {
818        "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response",
819        "EventCode": "0xB7, 0xBB",
820        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS",
821        "MSRIndex": "0x1a6,0x1a7",
822        "MSRValue": "0x2003c0001",
823        "SampleAfterValue": "100003",
824        "UMask": "0x1"
825    },
826    {
827        "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
828        "EventCode": "0xB7, 0xBB",
829        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
830        "MSRIndex": "0x1a6,0x1a7",
831        "MSRValue": "0x10003c0002",
832        "SampleAfterValue": "100003",
833        "UMask": "0x1"
834    },
835    {
836        "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches",
837        "EventCode": "0xB7, 0xBB",
838        "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS",
839        "MSRIndex": "0x1a6,0x1a7",
840        "MSRValue": "0x803c8000",
841        "SampleAfterValue": "100003",
842        "UMask": "0x1"
843    },
844    {
845        "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses",
846        "EventCode": "0xB7, 0xBB",
847        "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC",
848        "MSRIndex": "0x1a6,0x1a7",
849        "MSRValue": "0x23ffc08000",
850        "SampleAfterValue": "100003",
851        "UMask": "0x1"
852    },
853    {
854        "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC",
855        "EventCode": "0xB7, 0xBB",
856        "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
857        "MSRIndex": "0x1a6,0x1a7",
858        "MSRValue": "0x3f803c0040",
859        "SampleAfterValue": "100003",
860        "UMask": "0x1"
861    },
862    {
863        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC",
864        "EventCode": "0xB7, 0xBB",
865        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
866        "MSRIndex": "0x1a6,0x1a7",
867        "MSRValue": "0x3f803c0010",
868        "SampleAfterValue": "100003",
869        "UMask": "0x1"
870    },
871    {
872        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
873        "EventCode": "0xB7, 0xBB",
874        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
875        "MSRIndex": "0x1a6,0x1a7",
876        "MSRValue": "0x10003c0010",
877        "SampleAfterValue": "100003",
878        "UMask": "0x1"
879    },
880    {
881        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
882        "EventCode": "0xB7, 0xBB",
883        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
884        "MSRIndex": "0x1a6,0x1a7",
885        "MSRValue": "0x4003c0010",
886        "SampleAfterValue": "100003",
887        "UMask": "0x1"
888    },
889    {
890        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
891        "EventCode": "0xB7, 0xBB",
892        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
893        "MSRIndex": "0x1a6,0x1a7",
894        "MSRValue": "0x1003c0010",
895        "SampleAfterValue": "100003",
896        "UMask": "0x1"
897    },
898    {
899        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
900        "EventCode": "0xB7, 0xBB",
901        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS",
902        "MSRIndex": "0x1a6,0x1a7",
903        "MSRValue": "0x2003c0010",
904        "SampleAfterValue": "100003",
905        "UMask": "0x1"
906    },
907    {
908        "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC",
909        "EventCode": "0xB7, 0xBB",
910        "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
911        "MSRIndex": "0x1a6,0x1a7",
912        "MSRValue": "0x3f803c0200",
913        "SampleAfterValue": "100003",
914        "UMask": "0x1"
915    },
916    {
917        "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC",
918        "EventCode": "0xB7, 0xBB",
919        "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
920        "MSRIndex": "0x1a6,0x1a7",
921        "MSRValue": "0x3f803c0080",
922        "SampleAfterValue": "100003",
923        "UMask": "0x1"
924    },
925    {
926        "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
927        "EventCode": "0xB7, 0xBB",
928        "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
929        "MSRIndex": "0x1a6,0x1a7",
930        "MSRValue": "0x10003c0080",
931        "SampleAfterValue": "100003",
932        "UMask": "0x1"
933    },
934    {
935        "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
936        "EventCode": "0xB7, 0xBB",
937        "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
938        "MSRIndex": "0x1a6,0x1a7",
939        "MSRValue": "0x4003c0080",
940        "SampleAfterValue": "100003",
941        "UMask": "0x1"
942    },
943    {
944        "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
945        "EventCode": "0xB7, 0xBB",
946        "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
947        "MSRIndex": "0x1a6,0x1a7",
948        "MSRValue": "0x1003c0080",
949        "SampleAfterValue": "100003",
950        "UMask": "0x1"
951    },
952    {
953        "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
954        "EventCode": "0xB7, 0xBB",
955        "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS",
956        "MSRIndex": "0x1a6,0x1a7",
957        "MSRValue": "0x2003c0080",
958        "SampleAfterValue": "100003",
959        "UMask": "0x1"
960    },
961    {
962        "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",
963        "EventCode": "0xB7, 0xBB",
964        "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
965        "MSRIndex": "0x1a6,0x1a7",
966        "MSRValue": "0x10400",
967        "SampleAfterValue": "100003",
968        "UMask": "0x1"
969    },
970    {
971        "BriefDescription": "Counts non-temporal stores",
972        "EventCode": "0xB7, 0xBB",
973        "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
974        "MSRIndex": "0x1a6,0x1a7",
975        "MSRValue": "0x10800",
976        "SampleAfterValue": "100003",
977        "UMask": "0x1"
978    },
979    {
980        "BriefDescription": "Split locks in SQ",
981        "EventCode": "0xF4",
982        "EventName": "SQ_MISC.SPLIT_LOCK",
983        "SampleAfterValue": "100003",
984        "UMask": "0x10"
985    }
986]
987