1*c2f38d3bSIan Rogers[ 2*c2f38d3bSIan Rogers { 3*c2f38d3bSIan Rogers "BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.", 4*c2f38d3bSIan Rogers "EventCode": "0x83", 5*c2f38d3bSIan Rogers "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL", 6*c2f38d3bSIan Rogers "PerPkg": "1", 7*c2f38d3bSIan Rogers "UMask": "0x1", 8*c2f38d3bSIan Rogers "Unit": "ARB" 9*c2f38d3bSIan Rogers }, 10*c2f38d3bSIan Rogers { 11*c2f38d3bSIan Rogers "BriefDescription": "Number of requests allocated in Coherency Tracker.", 12*c2f38d3bSIan Rogers "EventCode": "0x84", 13*c2f38d3bSIan Rogers "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", 14*c2f38d3bSIan Rogers "PerPkg": "1", 15*c2f38d3bSIan Rogers "UMask": "0x1", 16*c2f38d3bSIan Rogers "Unit": "ARB" 17*c2f38d3bSIan Rogers }, 18*c2f38d3bSIan Rogers { 19*c2f38d3bSIan Rogers "BriefDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.", 20*c2f38d3bSIan Rogers "EventCode": "0x80", 21*c2f38d3bSIan Rogers "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", 22*c2f38d3bSIan Rogers "PerPkg": "1", 23*c2f38d3bSIan Rogers "UMask": "0x1", 24*c2f38d3bSIan Rogers "Unit": "ARB" 25*c2f38d3bSIan Rogers }, 26*c2f38d3bSIan Rogers { 27*c2f38d3bSIan Rogers "BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", 28*c2f38d3bSIan Rogers "CounterMask": "10", 29*c2f38d3bSIan Rogers "EventCode": "0x80", 30*c2f38d3bSIan Rogers "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL", 31*c2f38d3bSIan Rogers "PerPkg": "1", 32*c2f38d3bSIan Rogers "UMask": "0x1", 33*c2f38d3bSIan Rogers "Unit": "ARB" 34*c2f38d3bSIan Rogers }, 35*c2f38d3bSIan Rogers { 36*c2f38d3bSIan Rogers "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", 37*c2f38d3bSIan Rogers "CounterMask": "1", 38*c2f38d3bSIan Rogers "EventCode": "0x80", 39*c2f38d3bSIan Rogers "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", 40*c2f38d3bSIan Rogers "PerPkg": "1", 41*c2f38d3bSIan Rogers "UMask": "0x1", 42*c2f38d3bSIan Rogers "Unit": "ARB" 43*c2f38d3bSIan Rogers }, 44*c2f38d3bSIan Rogers { 45*c2f38d3bSIan Rogers "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.", 46*c2f38d3bSIan Rogers "EventCode": "0x81", 47*c2f38d3bSIan Rogers "EventName": "UNC_ARB_TRK_REQUESTS.ALL", 48*c2f38d3bSIan Rogers "PerPkg": "1", 49*c2f38d3bSIan Rogers "UMask": "0x1", 50*c2f38d3bSIan Rogers "Unit": "ARB" 51*c2f38d3bSIan Rogers }, 52*c2f38d3bSIan Rogers { 53*c2f38d3bSIan Rogers "BriefDescription": "Counts the number of LLC evictions allocated.", 54*c2f38d3bSIan Rogers "EventCode": "0x81", 55*c2f38d3bSIan Rogers "EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS", 56*c2f38d3bSIan Rogers "PerPkg": "1", 57*c2f38d3bSIan Rogers "UMask": "0x80", 58*c2f38d3bSIan Rogers "Unit": "ARB" 59*c2f38d3bSIan Rogers }, 60*c2f38d3bSIan Rogers { 61*c2f38d3bSIan Rogers "BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.", 62*c2f38d3bSIan Rogers "EventCode": "0x81", 63*c2f38d3bSIan Rogers "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", 64*c2f38d3bSIan Rogers "PerPkg": "1", 65*c2f38d3bSIan Rogers "UMask": "0x20", 66*c2f38d3bSIan Rogers "Unit": "ARB" 67*c2f38d3bSIan Rogers }, 68*c2f38d3bSIan Rogers { 69*c2f38d3bSIan Rogers "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.", 70*c2f38d3bSIan Rogers "EventCode": "0xff", 71*c2f38d3bSIan Rogers "EventName": "UNC_CLOCK.SOCKET", 72*c2f38d3bSIan Rogers "PerPkg": "1", 73*c2f38d3bSIan Rogers "Unit": "ARB" 74*c2f38d3bSIan Rogers } 75*c2f38d3bSIan Rogers] 76