1[
2    {
3        "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.",
4        "EventCode": "0x05",
5        "Counter": "0,1,2,3",
6        "UMask": "0x1",
7        "EventName": "MISALIGN_MEM_REF.LOADS",
8        "SampleAfterValue": "2000003",
9        "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
10        "CounterHTOff": "0,1,2,3,4,5,6,7"
11    },
12    {
13        "PublicDescription": "Speculative cache-line split Store-address uops dispatched to L1D.",
14        "EventCode": "0x05",
15        "Counter": "0,1,2,3",
16        "UMask": "0x2",
17        "EventName": "MISALIGN_MEM_REF.STORES",
18        "SampleAfterValue": "2000003",
19        "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
20        "CounterHTOff": "0,1,2,3,4,5,6,7"
21    },
22    {
23        "EventCode": "0xBE",
24        "Counter": "0,1,2,3",
25        "UMask": "0x1",
26        "EventName": "PAGE_WALKS.LLC_MISS",
27        "SampleAfterValue": "100003",
28        "BriefDescription": "Number of any page walk that had a miss in LLC.",
29        "CounterHTOff": "0,1,2,3,4,5,6,7"
30    },
31    {
32        "EventCode": "0xC3",
33        "Counter": "0,1,2,3",
34        "UMask": "0x2",
35        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
36        "SampleAfterValue": "100003",
37        "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
38        "CounterHTOff": "0,1,2,3,4,5,6,7"
39    },
40    {
41        "PEBS": "2",
42        "EventCode": "0xCD",
43        "Counter": "3",
44        "UMask": "0x2",
45        "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
46        "SampleAfterValue": "2000003",
47        "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.",
48        "PRECISE_STORE": "1",
49        "TakenAlone": "1",
50        "CounterHTOff": "3"
51    },
52    {
53        "PEBS": "2",
54        "PublicDescription": "Loads with latency value being above 4.",
55        "EventCode": "0xCD",
56        "MSRValue": "0x4",
57        "Counter": "3",
58        "UMask": "0x1",
59        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
60        "MSRIndex": "0x3F6",
61        "SampleAfterValue": "100003",
62        "BriefDescription": "Loads with latency value being above 4",
63        "TakenAlone": "1",
64        "CounterHTOff": "3"
65    },
66    {
67        "PEBS": "2",
68        "PublicDescription": "Loads with latency value being above 8.",
69        "EventCode": "0xCD",
70        "MSRValue": "0x8",
71        "Counter": "3",
72        "UMask": "0x1",
73        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
74        "MSRIndex": "0x3F6",
75        "SampleAfterValue": "50021",
76        "BriefDescription": "Loads with latency value being above 8",
77        "TakenAlone": "1",
78        "CounterHTOff": "3"
79    },
80    {
81        "PEBS": "2",
82        "PublicDescription": "Loads with latency value being above 16.",
83        "EventCode": "0xCD",
84        "MSRValue": "0x10",
85        "Counter": "3",
86        "UMask": "0x1",
87        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
88        "MSRIndex": "0x3F6",
89        "SampleAfterValue": "20011",
90        "BriefDescription": "Loads with latency value being above 16",
91        "TakenAlone": "1",
92        "CounterHTOff": "3"
93    },
94    {
95        "PEBS": "2",
96        "PublicDescription": "Loads with latency value being above 32.",
97        "EventCode": "0xCD",
98        "MSRValue": "0x20",
99        "Counter": "3",
100        "UMask": "0x1",
101        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
102        "MSRIndex": "0x3F6",
103        "SampleAfterValue": "100007",
104        "BriefDescription": "Loads with latency value being above 32",
105        "TakenAlone": "1",
106        "CounterHTOff": "3"
107    },
108    {
109        "PEBS": "2",
110        "PublicDescription": "Loads with latency value being above 64.",
111        "EventCode": "0xCD",
112        "MSRValue": "0x40",
113        "Counter": "3",
114        "UMask": "0x1",
115        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
116        "MSRIndex": "0x3F6",
117        "SampleAfterValue": "2003",
118        "BriefDescription": "Loads with latency value being above 64",
119        "TakenAlone": "1",
120        "CounterHTOff": "3"
121    },
122    {
123        "PEBS": "2",
124        "PublicDescription": "Loads with latency value being above 128.",
125        "EventCode": "0xCD",
126        "MSRValue": "0x80",
127        "Counter": "3",
128        "UMask": "0x1",
129        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
130        "MSRIndex": "0x3F6",
131        "SampleAfterValue": "1009",
132        "BriefDescription": "Loads with latency value being above 128",
133        "TakenAlone": "1",
134        "CounterHTOff": "3"
135    },
136    {
137        "PEBS": "2",
138        "PublicDescription": "Loads with latency value being above 256.",
139        "EventCode": "0xCD",
140        "MSRValue": "0x100",
141        "Counter": "3",
142        "UMask": "0x1",
143        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
144        "MSRIndex": "0x3F6",
145        "SampleAfterValue": "503",
146        "BriefDescription": "Loads with latency value being above 256",
147        "TakenAlone": "1",
148        "CounterHTOff": "3"
149    },
150    {
151        "PEBS": "2",
152        "PublicDescription": "Loads with latency value being above 512.",
153        "EventCode": "0xCD",
154        "MSRValue": "0x200",
155        "Counter": "3",
156        "UMask": "0x1",
157        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
158        "MSRIndex": "0x3F6",
159        "SampleAfterValue": "101",
160        "BriefDescription": "Loads with latency value being above 512",
161        "TakenAlone": "1",
162        "CounterHTOff": "3"
163    },
164    {
165        "EventCode": "0xB7, 0xBB",
166        "MSRValue": "0x300400244",
167        "Counter": "0,1,2,3",
168        "UMask": "0x1",
169        "Offcore": "1",
170        "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",
171        "MSRIndex": "0x1a6,0x1a7",
172        "SampleAfterValue": "100003",
173        "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC  and the data returned from dram",
174        "CounterHTOff": "0,1,2,3"
175    },
176    {
177        "EventCode": "0xB7, 0xBB",
178        "MSRValue": "0x300400091",
179        "Counter": "0,1,2,3",
180        "UMask": "0x1",
181        "Offcore": "1",
182        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",
183        "MSRIndex": "0x1a6,0x1a7",
184        "SampleAfterValue": "100003",
185        "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC  and the data returned from dram",
186        "CounterHTOff": "0,1,2,3"
187    },
188    {
189        "EventCode": "0xB7, 0xBB",
190        "MSRValue": "0x3004003f7",
191        "Counter": "0,1,2,3",
192        "UMask": "0x1",
193        "Offcore": "1",
194        "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM",
195        "MSRIndex": "0x1a6,0x1a7",
196        "SampleAfterValue": "100003",
197        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from dram",
198        "CounterHTOff": "0,1,2,3"
199    },
200    {
201        "EventCode": "0xB7, 0xBB",
202        "MSRValue": "0x300400004",
203        "Counter": "0,1,2,3",
204        "UMask": "0x1",
205        "Offcore": "1",
206        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM",
207        "MSRIndex": "0x1a6,0x1a7",
208        "SampleAfterValue": "100003",
209        "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram",
210        "CounterHTOff": "0,1,2,3"
211    },
212    {
213        "EventCode": "0xB7, 0xBB",
214        "MSRValue": "0x300400001",
215        "Counter": "0,1,2,3",
216        "UMask": "0x1",
217        "Offcore": "1",
218        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM",
219        "MSRIndex": "0x1a6,0x1a7",
220        "SampleAfterValue": "100003",
221        "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram",
222        "CounterHTOff": "0,1,2,3"
223    },
224    {
225        "EventCode": "0xB7, 0xBB",
226        "MSRValue": "0x6004001b3",
227        "Counter": "0,1,2,3",
228        "UMask": "0x1",
229        "Offcore": "1",
230        "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM",
231        "MSRIndex": "0x1a6,0x1a7",
232        "SampleAfterValue": "100003",
233        "BriefDescription": "Counts LLC replacements",
234        "CounterHTOff": "0,1,2,3"
235    }
236]