18853d2deSAndi Kleen[ 28853d2deSAndi Kleen { 3fd550098SAndi Kleen "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)", 4fd550098SAndi Kleen "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", 5fd550098SAndi Kleen "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", 6fd550098SAndi Kleen "MetricGroup": "TopdownL1", 7fd550098SAndi Kleen "MetricName": "Frontend_Bound" 8fd550098SAndi Kleen }, 9fd550098SAndi Kleen { 10fd550098SAndi Kleen "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", 11fd550098SAndi Kleen "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU.", 12fd550098SAndi Kleen "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", 13fd550098SAndi Kleen "MetricGroup": "TopdownL1_SMT", 14fd550098SAndi Kleen "MetricName": "Frontend_Bound_SMT" 15fd550098SAndi Kleen }, 16fd550098SAndi Kleen { 17fd550098SAndi Kleen "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)", 18fd550098SAndi Kleen "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", 19fd550098SAndi Kleen "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", 20fd550098SAndi Kleen "MetricGroup": "TopdownL1", 21fd550098SAndi Kleen "MetricName": "Bad_Speculation" 22fd550098SAndi Kleen }, 23fd550098SAndi Kleen { 24fd550098SAndi Kleen "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", 25fd550098SAndi Kleen "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU.", 26fd550098SAndi Kleen "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.", 27fd550098SAndi Kleen "MetricGroup": "TopdownL1_SMT", 28fd550098SAndi Kleen "MetricName": "Bad_Speculation_SMT" 29fd550098SAndi Kleen }, 30fd550098SAndi Kleen { 31fd550098SAndi Kleen "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )", 32fd550098SAndi Kleen "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", 33fd550098SAndi Kleen "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", 34fd550098SAndi Kleen "MetricGroup": "TopdownL1", 35fd550098SAndi Kleen "MetricName": "Backend_Bound" 36fd550098SAndi Kleen }, 37fd550098SAndi Kleen { 38fd550098SAndi Kleen "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )", 39fd550098SAndi Kleen "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU.", 40fd550098SAndi Kleen "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", 41fd550098SAndi Kleen "MetricGroup": "TopdownL1_SMT", 42fd550098SAndi Kleen "MetricName": "Backend_Bound_SMT" 43fd550098SAndi Kleen }, 44fd550098SAndi Kleen { 45fd550098SAndi Kleen "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)", 46fd550098SAndi Kleen "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. ", 47fd550098SAndi Kleen "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", 48fd550098SAndi Kleen "MetricGroup": "TopdownL1", 49fd550098SAndi Kleen "MetricName": "Retiring" 50fd550098SAndi Kleen }, 51fd550098SAndi Kleen { 52fd550098SAndi Kleen "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", 53fd550098SAndi Kleen "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. SMT version; use when SMT is enabled and measuring per logical CPU.", 54fd550098SAndi Kleen "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.", 55fd550098SAndi Kleen "MetricGroup": "TopdownL1_SMT", 56fd550098SAndi Kleen "MetricName": "Retiring_SMT" 57fd550098SAndi Kleen }, 58fd550098SAndi Kleen { 598853d2deSAndi Kleen "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", 60fd550098SAndi Kleen "BriefDescription": "Instructions Per Cycle (per logical thread)", 618853d2deSAndi Kleen "MetricGroup": "TopDownL1", 628853d2deSAndi Kleen "MetricName": "IPC" 638853d2deSAndi Kleen }, 648853d2deSAndi Kleen { 658853d2deSAndi Kleen "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", 66fd550098SAndi Kleen "BriefDescription": "Uops Per Instruction", 67fd550098SAndi Kleen "MetricGroup": "Pipeline;Retiring", 688853d2deSAndi Kleen "MetricName": "UPI" 698853d2deSAndi Kleen }, 708853d2deSAndi Kleen { 71fd550098SAndi Kleen "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", 72fd550098SAndi Kleen "BriefDescription": "Instruction per taken branch", 73fd550098SAndi Kleen "MetricGroup": "Branches;PGO", 74fd550098SAndi Kleen "MetricName": "IpTB" 75fd550098SAndi Kleen }, 76fd550098SAndi Kleen { 77fd550098SAndi Kleen "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", 78fd550098SAndi Kleen "BriefDescription": "Branch instructions per taken branch. ", 79fd550098SAndi Kleen "MetricGroup": "Branches;PGO", 80fd550098SAndi Kleen "MetricName": "BpTB" 81fd550098SAndi Kleen }, 82fd550098SAndi Kleen { 831de31524SAndi Kleen "MetricExpr": "min( 1 , UOPS_ISSUED.ANY / ( (UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 32 * ( ICACHE.HIT + ICACHE.MISSES ) / 4 ) )", 84fd550098SAndi Kleen "BriefDescription": "Rough Estimation of fraction of fetched lines bytes that were likely (includes speculatively fetches) consumed by program instructions", 85fd550098SAndi Kleen "MetricGroup": "PGO", 868853d2deSAndi Kleen "MetricName": "IFetch_Line_Utilization" 878853d2deSAndi Kleen }, 888853d2deSAndi Kleen { 89fd550098SAndi Kleen "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", 90fd550098SAndi Kleen "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", 918853d2deSAndi Kleen "MetricGroup": "DSB;Frontend_Bandwidth", 928853d2deSAndi Kleen "MetricName": "DSB_Coverage" 938853d2deSAndi Kleen }, 948853d2deSAndi Kleen { 951de31524SAndi Kleen "MetricExpr": "1 / (INST_RETIRED.ANY / cycles)", 96fd550098SAndi Kleen "BriefDescription": "Cycles Per Instruction (threaded)", 978853d2deSAndi Kleen "MetricGroup": "Pipeline;Summary", 988853d2deSAndi Kleen "MetricName": "CPI" 998853d2deSAndi Kleen }, 1008853d2deSAndi Kleen { 1018853d2deSAndi Kleen "MetricExpr": "CPU_CLK_UNHALTED.THREAD", 102fd550098SAndi Kleen "BriefDescription": "Per-thread actual clocks when the logical processor is active.", 1038853d2deSAndi Kleen "MetricGroup": "Summary", 1048853d2deSAndi Kleen "MetricName": "CLKS" 1058853d2deSAndi Kleen }, 1068853d2deSAndi Kleen { 107fd550098SAndi Kleen "MetricExpr": "4 * cycles", 108fd550098SAndi Kleen "BriefDescription": "Total issue-pipeline slots (per core)", 1098853d2deSAndi Kleen "MetricGroup": "TopDownL1", 1108853d2deSAndi Kleen "MetricName": "SLOTS" 1118853d2deSAndi Kleen }, 1128853d2deSAndi Kleen { 113fd550098SAndi Kleen "MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", 114fd550098SAndi Kleen "BriefDescription": "Total issue-pipeline slots (per core)", 115fd550098SAndi Kleen "MetricGroup": "TopDownL1_SMT", 116fd550098SAndi Kleen "MetricName": "SLOTS_SMT" 117fd550098SAndi Kleen }, 118fd550098SAndi Kleen { 119fd550098SAndi Kleen "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", 120fd550098SAndi Kleen "BriefDescription": "Instructions per Load (lower number means loads are more frequent)", 121fd550098SAndi Kleen "MetricGroup": "Instruction_Type;L1_Bound", 122fd550098SAndi Kleen "MetricName": "IpL" 123fd550098SAndi Kleen }, 124fd550098SAndi Kleen { 125fd550098SAndi Kleen "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", 126fd550098SAndi Kleen "BriefDescription": "Instructions per Store", 127fd550098SAndi Kleen "MetricGroup": "Instruction_Type;Store_Bound", 128fd550098SAndi Kleen "MetricName": "IpS" 129fd550098SAndi Kleen }, 130fd550098SAndi Kleen { 131fd550098SAndi Kleen "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", 132fd550098SAndi Kleen "BriefDescription": "Instructions per Branch", 133fd550098SAndi Kleen "MetricGroup": "Branches;Instruction_Type;Port_5;Port_6", 134fd550098SAndi Kleen "MetricName": "IpB" 135fd550098SAndi Kleen }, 136fd550098SAndi Kleen { 137fd550098SAndi Kleen "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", 138fd550098SAndi Kleen "BriefDescription": "Instruction per (near) call", 139fd550098SAndi Kleen "MetricGroup": "Branches", 140fd550098SAndi Kleen "MetricName": "IpCall" 141fd550098SAndi Kleen }, 142fd550098SAndi Kleen { 1438853d2deSAndi Kleen "MetricExpr": "INST_RETIRED.ANY", 144fd550098SAndi Kleen "BriefDescription": "Total number of retired Instructions", 1458853d2deSAndi Kleen "MetricGroup": "Summary", 1468853d2deSAndi Kleen "MetricName": "Instructions" 1478853d2deSAndi Kleen }, 1488853d2deSAndi Kleen { 149fd550098SAndi Kleen "MetricExpr": "INST_RETIRED.ANY / cycles", 1508853d2deSAndi Kleen "BriefDescription": "Instructions Per Cycle (per physical core)", 1518853d2deSAndi Kleen "MetricGroup": "SMT", 1528853d2deSAndi Kleen "MetricName": "CoreIPC" 1538853d2deSAndi Kleen }, 1548853d2deSAndi Kleen { 155fd550098SAndi Kleen "MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", 156fd550098SAndi Kleen "BriefDescription": "Instructions Per Cycle (per physical core)", 157fd550098SAndi Kleen "MetricGroup": "SMT", 158fd550098SAndi Kleen "MetricName": "CoreIPC_SMT" 159fd550098SAndi Kleen }, 160fd550098SAndi Kleen { 161fd550098SAndi Kleen "MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / cycles", 162fd550098SAndi Kleen "BriefDescription": "Floating Point Operations Per Cycle", 163fd550098SAndi Kleen "MetricGroup": "FLOPS", 164fd550098SAndi Kleen "MetricName": "FLOPc" 165fd550098SAndi Kleen }, 166fd550098SAndi Kleen { 167fd550098SAndi Kleen "MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", 168fd550098SAndi Kleen "BriefDescription": "Floating Point Operations Per Cycle", 169fd550098SAndi Kleen "MetricGroup": "FLOPS_SMT", 170fd550098SAndi Kleen "MetricName": "FLOPc_SMT" 171fd550098SAndi Kleen }, 172fd550098SAndi Kleen { 1731de31524SAndi Kleen "MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", 174fd550098SAndi Kleen "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)", 1758853d2deSAndi Kleen "MetricGroup": "Pipeline;Ports_Utilization", 1768853d2deSAndi Kleen "MetricName": "ILP" 1778853d2deSAndi Kleen }, 1788853d2deSAndi Kleen { 179fd550098SAndi Kleen "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", 180fd550098SAndi Kleen "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", 181fd550098SAndi Kleen "MetricGroup": "Branch_Mispredicts", 182fd550098SAndi Kleen "MetricName": "IpMispredict" 1838853d2deSAndi Kleen }, 1848853d2deSAndi Kleen { 185fd550098SAndi Kleen "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", 1868853d2deSAndi Kleen "BriefDescription": "Core actual clocks when any thread is active on the physical core", 1878853d2deSAndi Kleen "MetricGroup": "SMT", 1888853d2deSAndi Kleen "MetricName": "CORE_CLKS" 1898853d2deSAndi Kleen }, 1908853d2deSAndi Kleen { 1918853d2deSAndi Kleen "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )", 192fd550098SAndi Kleen "BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)", 1938853d2deSAndi Kleen "MetricGroup": "Memory_Bound;Memory_Lat", 1948853d2deSAndi Kleen "MetricName": "Load_Miss_Real_Latency" 1958853d2deSAndi Kleen }, 1968853d2deSAndi Kleen { 197fd550098SAndi Kleen "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", 198fd550098SAndi Kleen "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-thread)", 1998853d2deSAndi Kleen "MetricGroup": "Memory_Bound;Memory_BW", 2008853d2deSAndi Kleen "MetricName": "MLP" 2018853d2deSAndi Kleen }, 2028853d2deSAndi Kleen { 203fd550098SAndi Kleen "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / cycles", 2048853d2deSAndi Kleen "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", 2058853d2deSAndi Kleen "MetricGroup": "TLB", 2068853d2deSAndi Kleen "MetricName": "Page_Walks_Utilization" 2078853d2deSAndi Kleen }, 2088853d2deSAndi Kleen { 209fd550098SAndi Kleen "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", 210fd550098SAndi Kleen "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", 211fd550098SAndi Kleen "MetricGroup": "TLB_SMT", 212fd550098SAndi Kleen "MetricName": "Page_Walks_Utilization_SMT" 213fd550098SAndi Kleen }, 214fd550098SAndi Kleen { 215fd550098SAndi Kleen "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", 216fd550098SAndi Kleen "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]", 217fd550098SAndi Kleen "MetricGroup": "Memory_BW", 218fd550098SAndi Kleen "MetricName": "L1D_Cache_Fill_BW" 219fd550098SAndi Kleen }, 220fd550098SAndi Kleen { 221fd550098SAndi Kleen "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", 222fd550098SAndi Kleen "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]", 223fd550098SAndi Kleen "MetricGroup": "Memory_BW", 224fd550098SAndi Kleen "MetricName": "L2_Cache_Fill_BW" 225fd550098SAndi Kleen }, 226fd550098SAndi Kleen { 227fd550098SAndi Kleen "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time", 228fd550098SAndi Kleen "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", 229fd550098SAndi Kleen "MetricGroup": "Memory_BW", 230fd550098SAndi Kleen "MetricName": "L3_Cache_Fill_BW" 231fd550098SAndi Kleen }, 232fd550098SAndi Kleen { 233fd550098SAndi Kleen "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", 234fd550098SAndi Kleen "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", 235fd550098SAndi Kleen "MetricGroup": "Cache_Misses;", 236fd550098SAndi Kleen "MetricName": "L1MPKI" 237fd550098SAndi Kleen }, 238fd550098SAndi Kleen { 239fd550098SAndi Kleen "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", 240fd550098SAndi Kleen "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", 241fd550098SAndi Kleen "MetricGroup": "Cache_Misses;", 242fd550098SAndi Kleen "MetricName": "L2MPKI" 243fd550098SAndi Kleen }, 244fd550098SAndi Kleen { 245fd550098SAndi Kleen "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", 246fd550098SAndi Kleen "BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)", 247fd550098SAndi Kleen "MetricGroup": "Cache_Misses;", 248fd550098SAndi Kleen "MetricName": "L2MPKI_All" 249fd550098SAndi Kleen }, 250fd550098SAndi Kleen { 251fd550098SAndi Kleen "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", 252fd550098SAndi Kleen "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", 253fd550098SAndi Kleen "MetricGroup": "Cache_Misses;", 254fd550098SAndi Kleen "MetricName": "L2HPKI_All" 255fd550098SAndi Kleen }, 256fd550098SAndi Kleen { 257fd550098SAndi Kleen "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRED.ANY", 258fd550098SAndi Kleen "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", 259fd550098SAndi Kleen "MetricGroup": "Cache_Misses;", 260fd550098SAndi Kleen "MetricName": "L3MPKI" 261fd550098SAndi Kleen }, 262fd550098SAndi Kleen { 2638853d2deSAndi Kleen "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", 264fd550098SAndi Kleen "BriefDescription": "Average CPU Utilization", 2658853d2deSAndi Kleen "MetricGroup": "Summary", 2668853d2deSAndi Kleen "MetricName": "CPU_Utilization" 2678853d2deSAndi Kleen }, 2688853d2deSAndi Kleen { 269fd550098SAndi Kleen "MetricExpr": "( (( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / 1000000000 ) / duration_time", 2708853d2deSAndi Kleen "BriefDescription": "Giga Floating Point Operations Per Second", 2718853d2deSAndi Kleen "MetricGroup": "FLOPS;Summary", 2728853d2deSAndi Kleen "MetricName": "GFLOPs" 2738853d2deSAndi Kleen }, 2748853d2deSAndi Kleen { 2758853d2deSAndi Kleen "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC", 276fd550098SAndi Kleen "BriefDescription": "Average Frequency Utilization relative nominal frequency", 2778853d2deSAndi Kleen "MetricGroup": "Power", 2788853d2deSAndi Kleen "MetricName": "Turbo_Utilization" 2798853d2deSAndi Kleen }, 2808853d2deSAndi Kleen { 2818853d2deSAndi Kleen "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", 282fd550098SAndi Kleen "BriefDescription": "Fraction of cycles where both hardware threads were active", 2838853d2deSAndi Kleen "MetricGroup": "SMT;Summary", 2848853d2deSAndi Kleen "MetricName": "SMT_2T_Utilization" 2858853d2deSAndi Kleen }, 2868853d2deSAndi Kleen { 2878853d2deSAndi Kleen "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC:u / CPU_CLK_UNHALTED.REF_TSC", 288fd550098SAndi Kleen "BriefDescription": "Fraction of cycles spent in Kernel mode", 2898853d2deSAndi Kleen "MetricGroup": "Summary", 2908853d2deSAndi Kleen "MetricName": "Kernel_Utilization" 2918853d2deSAndi Kleen }, 2928853d2deSAndi Kleen { 293fd550098SAndi Kleen "MetricExpr": "64 * ( arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@ ) / 1000000 / duration_time / 1000", 294fd550098SAndi Kleen "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", 295fd550098SAndi Kleen "MetricGroup": "Memory_BW", 296fd550098SAndi Kleen "MetricName": "DRAM_BW_Use" 297fd550098SAndi Kleen }, 298fd550098SAndi Kleen { 2998853d2deSAndi Kleen "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", 3008853d2deSAndi Kleen "MetricGroup": "Power", 301fd550098SAndi Kleen "BriefDescription": "C3 residency percent per core", 3028853d2deSAndi Kleen "MetricName": "C3_Core_Residency" 3038853d2deSAndi Kleen }, 3048853d2deSAndi Kleen { 3058853d2deSAndi Kleen "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100", 3068853d2deSAndi Kleen "MetricGroup": "Power", 307fd550098SAndi Kleen "BriefDescription": "C6 residency percent per core", 3088853d2deSAndi Kleen "MetricName": "C6_Core_Residency" 3098853d2deSAndi Kleen }, 3108853d2deSAndi Kleen { 3118853d2deSAndi Kleen "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100", 3128853d2deSAndi Kleen "MetricGroup": "Power", 313fd550098SAndi Kleen "BriefDescription": "C7 residency percent per core", 3148853d2deSAndi Kleen "MetricName": "C7_Core_Residency" 3158853d2deSAndi Kleen }, 3168853d2deSAndi Kleen { 3178853d2deSAndi Kleen "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100", 3188853d2deSAndi Kleen "MetricGroup": "Power", 319fd550098SAndi Kleen "BriefDescription": "C2 residency percent per package", 3208853d2deSAndi Kleen "MetricName": "C2_Pkg_Residency" 3218853d2deSAndi Kleen }, 3228853d2deSAndi Kleen { 3238853d2deSAndi Kleen "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100", 3248853d2deSAndi Kleen "MetricGroup": "Power", 325fd550098SAndi Kleen "BriefDescription": "C3 residency percent per package", 3268853d2deSAndi Kleen "MetricName": "C3_Pkg_Residency" 3278853d2deSAndi Kleen }, 3288853d2deSAndi Kleen { 3298853d2deSAndi Kleen "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", 3308853d2deSAndi Kleen "MetricGroup": "Power", 331fd550098SAndi Kleen "BriefDescription": "C6 residency percent per package", 3328853d2deSAndi Kleen "MetricName": "C6_Pkg_Residency" 3338853d2deSAndi Kleen }, 3348853d2deSAndi Kleen { 3358853d2deSAndi Kleen "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", 3368853d2deSAndi Kleen "MetricGroup": "Power", 337fd550098SAndi Kleen "BriefDescription": "C7 residency percent per package", 3388853d2deSAndi Kleen "MetricName": "C7_Pkg_Residency" 3398853d2deSAndi Kleen } 3408853d2deSAndi Kleen] 341