1[
2    {
3        "BriefDescription": "L1D data line replacements",
4        "EventCode": "0x51",
5        "EventName": "L1D.REPLACEMENT",
6        "PublicDescription": "Counts the number of lines brought into the L1 data cache.",
7        "SampleAfterValue": "2000003",
8        "UMask": "0x1"
9    },
10    {
11        "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",
12        "CounterMask": "1",
13        "EventCode": "0x48",
14        "EventName": "L1D_PEND_MISS.FB_FULL",
15        "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
16        "SampleAfterValue": "2000003",
17        "UMask": "0x2"
18    },
19    {
20        "BriefDescription": "L1D miss oustandings duration in cycles",
21        "EventCode": "0x48",
22        "EventName": "L1D_PEND_MISS.PENDING",
23        "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
24        "SampleAfterValue": "2000003",
25        "UMask": "0x1"
26    },
27    {
28        "BriefDescription": "Cycles with L1D load Misses outstanding.",
29        "CounterMask": "1",
30        "EventCode": "0x48",
31        "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
32        "SampleAfterValue": "2000003",
33        "UMask": "0x1"
34    },
35    {
36        "AnyThread": "1",
37        "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",
38        "CounterMask": "1",
39        "EventCode": "0x48",
40        "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
41        "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
42        "SampleAfterValue": "2000003",
43        "UMask": "0x1"
44    },
45    {
46        "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
47        "EventCode": "0x28",
48        "EventName": "L2_L1D_WB_RQSTS.ALL",
49        "SampleAfterValue": "200003",
50        "UMask": "0xf"
51    },
52    {
53        "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
54        "EventCode": "0x28",
55        "EventName": "L2_L1D_WB_RQSTS.HIT_E",
56        "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
57        "SampleAfterValue": "200003",
58        "UMask": "0x4"
59    },
60    {
61        "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
62        "EventCode": "0x28",
63        "EventName": "L2_L1D_WB_RQSTS.HIT_M",
64        "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
65        "SampleAfterValue": "200003",
66        "UMask": "0x8"
67    },
68    {
69        "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)",
70        "EventCode": "0x28",
71        "EventName": "L2_L1D_WB_RQSTS.MISS",
72        "PublicDescription": "Not rejected writebacks that missed LLC.",
73        "SampleAfterValue": "200003",
74        "UMask": "0x1"
75    },
76    {
77        "BriefDescription": "L2 cache lines filling L2",
78        "EventCode": "0xF1",
79        "EventName": "L2_LINES_IN.ALL",
80        "PublicDescription": "L2 cache lines filling L2.",
81        "SampleAfterValue": "100003",
82        "UMask": "0x7"
83    },
84    {
85        "BriefDescription": "L2 cache lines in E state filling L2",
86        "EventCode": "0xF1",
87        "EventName": "L2_LINES_IN.E",
88        "PublicDescription": "L2 cache lines in E state filling L2.",
89        "SampleAfterValue": "100003",
90        "UMask": "0x4"
91    },
92    {
93        "BriefDescription": "L2 cache lines in I state filling L2",
94        "EventCode": "0xF1",
95        "EventName": "L2_LINES_IN.I",
96        "PublicDescription": "L2 cache lines in I state filling L2.",
97        "SampleAfterValue": "100003",
98        "UMask": "0x1"
99    },
100    {
101        "BriefDescription": "L2 cache lines in S state filling L2",
102        "EventCode": "0xF1",
103        "EventName": "L2_LINES_IN.S",
104        "PublicDescription": "L2 cache lines in S state filling L2.",
105        "SampleAfterValue": "100003",
106        "UMask": "0x2"
107    },
108    {
109        "BriefDescription": "Clean L2 cache lines evicted by demand",
110        "EventCode": "0xF2",
111        "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
112        "PublicDescription": "Clean L2 cache lines evicted by demand.",
113        "SampleAfterValue": "100003",
114        "UMask": "0x1"
115    },
116    {
117        "BriefDescription": "Dirty L2 cache lines evicted by demand",
118        "EventCode": "0xF2",
119        "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
120        "PublicDescription": "Dirty L2 cache lines evicted by demand.",
121        "SampleAfterValue": "100003",
122        "UMask": "0x2"
123    },
124    {
125        "BriefDescription": "Dirty L2 cache lines filling the L2",
126        "EventCode": "0xF2",
127        "EventName": "L2_LINES_OUT.DIRTY_ALL",
128        "PublicDescription": "Dirty L2 cache lines filling the L2.",
129        "SampleAfterValue": "100003",
130        "UMask": "0xa"
131    },
132    {
133        "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch",
134        "EventCode": "0xF2",
135        "EventName": "L2_LINES_OUT.PF_CLEAN",
136        "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.",
137        "SampleAfterValue": "100003",
138        "UMask": "0x4"
139    },
140    {
141        "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch",
142        "EventCode": "0xF2",
143        "EventName": "L2_LINES_OUT.PF_DIRTY",
144        "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.",
145        "SampleAfterValue": "100003",
146        "UMask": "0x8"
147    },
148    {
149        "BriefDescription": "L2 code requests",
150        "EventCode": "0x24",
151        "EventName": "L2_RQSTS.ALL_CODE_RD",
152        "PublicDescription": "Counts all L2 code requests.",
153        "SampleAfterValue": "200003",
154        "UMask": "0x30"
155    },
156    {
157        "BriefDescription": "Demand Data Read requests",
158        "EventCode": "0x24",
159        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
160        "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
161        "SampleAfterValue": "200003",
162        "UMask": "0x3"
163    },
164    {
165        "BriefDescription": "Requests from L2 hardware prefetchers",
166        "EventCode": "0x24",
167        "EventName": "L2_RQSTS.ALL_PF",
168        "PublicDescription": "Counts all L2 HW prefetcher requests.",
169        "SampleAfterValue": "200003",
170        "UMask": "0xc0"
171    },
172    {
173        "BriefDescription": "RFO requests to L2 cache",
174        "EventCode": "0x24",
175        "EventName": "L2_RQSTS.ALL_RFO",
176        "PublicDescription": "Counts all L2 store RFO requests.",
177        "SampleAfterValue": "200003",
178        "UMask": "0xc"
179    },
180    {
181        "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
182        "EventCode": "0x24",
183        "EventName": "L2_RQSTS.CODE_RD_HIT",
184        "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
185        "SampleAfterValue": "200003",
186        "UMask": "0x10"
187    },
188    {
189        "BriefDescription": "L2 cache misses when fetching instructions",
190        "EventCode": "0x24",
191        "EventName": "L2_RQSTS.CODE_RD_MISS",
192        "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
193        "SampleAfterValue": "200003",
194        "UMask": "0x20"
195    },
196    {
197        "BriefDescription": "Demand Data Read requests that hit L2 cache",
198        "EventCode": "0x24",
199        "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
200        "PublicDescription": "Demand Data Read requests that hit L2 cache.",
201        "SampleAfterValue": "200003",
202        "UMask": "0x1"
203    },
204    {
205        "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",
206        "EventCode": "0x24",
207        "EventName": "L2_RQSTS.PF_HIT",
208        "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
209        "SampleAfterValue": "200003",
210        "UMask": "0x40"
211    },
212    {
213        "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",
214        "EventCode": "0x24",
215        "EventName": "L2_RQSTS.PF_MISS",
216        "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
217        "SampleAfterValue": "200003",
218        "UMask": "0x80"
219    },
220    {
221        "BriefDescription": "RFO requests that hit L2 cache",
222        "EventCode": "0x24",
223        "EventName": "L2_RQSTS.RFO_HIT",
224        "PublicDescription": "RFO requests that hit L2 cache.",
225        "SampleAfterValue": "200003",
226        "UMask": "0x4"
227    },
228    {
229        "BriefDescription": "RFO requests that miss L2 cache",
230        "EventCode": "0x24",
231        "EventName": "L2_RQSTS.RFO_MISS",
232        "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
233        "SampleAfterValue": "200003",
234        "UMask": "0x8"
235    },
236    {
237        "BriefDescription": "RFOs that access cache lines in any state",
238        "EventCode": "0x27",
239        "EventName": "L2_STORE_LOCK_RQSTS.ALL",
240        "PublicDescription": "RFOs that access cache lines in any state.",
241        "SampleAfterValue": "200003",
242        "UMask": "0xf"
243    },
244    {
245        "BriefDescription": "RFOs that hit cache lines in M state",
246        "EventCode": "0x27",
247        "EventName": "L2_STORE_LOCK_RQSTS.HIT_M",
248        "PublicDescription": "RFOs that hit cache lines in M state.",
249        "SampleAfterValue": "200003",
250        "UMask": "0x8"
251    },
252    {
253        "BriefDescription": "RFOs that miss cache lines",
254        "EventCode": "0x27",
255        "EventName": "L2_STORE_LOCK_RQSTS.MISS",
256        "PublicDescription": "RFOs that miss cache lines.",
257        "SampleAfterValue": "200003",
258        "UMask": "0x1"
259    },
260    {
261        "BriefDescription": "L2 or LLC HW prefetches that access L2 cache",
262        "EventCode": "0xF0",
263        "EventName": "L2_TRANS.ALL_PF",
264        "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.",
265        "SampleAfterValue": "200003",
266        "UMask": "0x8"
267    },
268    {
269        "BriefDescription": "Transactions accessing L2 pipe",
270        "EventCode": "0xF0",
271        "EventName": "L2_TRANS.ALL_REQUESTS",
272        "PublicDescription": "Transactions accessing L2 pipe.",
273        "SampleAfterValue": "200003",
274        "UMask": "0x80"
275    },
276    {
277        "BriefDescription": "L2 cache accesses when fetching instructions",
278        "EventCode": "0xF0",
279        "EventName": "L2_TRANS.CODE_RD",
280        "PublicDescription": "L2 cache accesses when fetching instructions.",
281        "SampleAfterValue": "200003",
282        "UMask": "0x4"
283    },
284    {
285        "BriefDescription": "Demand Data Read requests that access L2 cache",
286        "EventCode": "0xF0",
287        "EventName": "L2_TRANS.DEMAND_DATA_RD",
288        "PublicDescription": "Demand Data Read requests that access L2 cache.",
289        "SampleAfterValue": "200003",
290        "UMask": "0x1"
291    },
292    {
293        "BriefDescription": "L1D writebacks that access L2 cache",
294        "EventCode": "0xF0",
295        "EventName": "L2_TRANS.L1D_WB",
296        "PublicDescription": "L1D writebacks that access L2 cache.",
297        "SampleAfterValue": "200003",
298        "UMask": "0x10"
299    },
300    {
301        "BriefDescription": "L2 fill requests that access L2 cache",
302        "EventCode": "0xF0",
303        "EventName": "L2_TRANS.L2_FILL",
304        "PublicDescription": "L2 fill requests that access L2 cache.",
305        "SampleAfterValue": "200003",
306        "UMask": "0x20"
307    },
308    {
309        "BriefDescription": "L2 writebacks that access L2 cache",
310        "EventCode": "0xF0",
311        "EventName": "L2_TRANS.L2_WB",
312        "PublicDescription": "L2 writebacks that access L2 cache.",
313        "SampleAfterValue": "200003",
314        "UMask": "0x40"
315    },
316    {
317        "BriefDescription": "RFO requests that access L2 cache",
318        "EventCode": "0xF0",
319        "EventName": "L2_TRANS.RFO",
320        "PublicDescription": "RFO requests that access L2 cache.",
321        "SampleAfterValue": "200003",
322        "UMask": "0x2"
323    },
324    {
325        "BriefDescription": "Cycles when L1D is locked",
326        "EventCode": "0x63",
327        "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
328        "PublicDescription": "Cycles in which the L1D is locked.",
329        "SampleAfterValue": "2000003",
330        "UMask": "0x2"
331    },
332    {
333        "BriefDescription": "Core-originated cacheable demand requests missed LLC",
334        "EventCode": "0x2E",
335        "EventName": "LONGEST_LAT_CACHE.MISS",
336        "PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
337        "SampleAfterValue": "100003",
338        "UMask": "0x41"
339    },
340    {
341        "BriefDescription": "Core-originated cacheable demand requests that refer to LLC",
342        "EventCode": "0x2E",
343        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
344        "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
345        "SampleAfterValue": "100003",
346        "UMask": "0x4f"
347    },
348    {
349        "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.",
350        "EventCode": "0xD2",
351        "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",
352        "PEBS": "1",
353        "SampleAfterValue": "20011",
354        "UMask": "0x2"
355    },
356    {
357        "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.",
358        "EventCode": "0xD2",
359        "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",
360        "PEBS": "1",
361        "SampleAfterValue": "20011",
362        "UMask": "0x4"
363    },
364    {
365        "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.",
366        "EventCode": "0xD2",
367        "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",
368        "PEBS": "1",
369        "SampleAfterValue": "20011",
370        "UMask": "0x1"
371    },
372    {
373        "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.",
374        "EventCode": "0xD2",
375        "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",
376        "PEBS": "1",
377        "SampleAfterValue": "100003",
378        "UMask": "0x8"
379    },
380    {
381        "BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.",
382        "EventCode": "0xD3",
383        "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",
384        "PublicDescription": "Retired load uops whose data source was local memory (cross-socket snoop not needed or missed).",
385        "SampleAfterValue": "100007",
386        "UMask": "0x1"
387    },
388    {
389        "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
390        "EventCode": "0xD1",
391        "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
392        "PEBS": "1",
393        "SampleAfterValue": "100003",
394        "UMask": "0x40"
395    },
396    {
397        "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
398        "EventCode": "0xD1",
399        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
400        "PEBS": "1",
401        "SampleAfterValue": "2000003",
402        "UMask": "0x1"
403    },
404    {
405        "BriefDescription": "Retired load uops which data sources following L1 data-cache miss.",
406        "EventCode": "0xD1",
407        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
408        "PEBS": "1",
409        "SampleAfterValue": "100003",
410        "UMask": "0x8"
411    },
412    {
413        "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
414        "EventCode": "0xD1",
415        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
416        "PEBS": "1",
417        "SampleAfterValue": "100003",
418        "UMask": "0x2"
419    },
420    {
421        "BriefDescription": "Retired load uops with L2 cache misses as data sources.",
422        "EventCode": "0xD1",
423        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
424        "PEBS": "1",
425        "SampleAfterValue": "50021",
426        "UMask": "0x10"
427    },
428    {
429        "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.",
430        "EventCode": "0xD1",
431        "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",
432        "PEBS": "1",
433        "SampleAfterValue": "50021",
434        "UMask": "0x4"
435    },
436    {
437        "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
438        "EventCode": "0xD1",
439        "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS",
440        "PEBS": "1",
441        "SampleAfterValue": "100007",
442        "UMask": "0x20"
443    },
444    {
445        "BriefDescription": "All retired load uops. (Precise Event)",
446        "EventCode": "0xD0",
447        "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
448        "PEBS": "1",
449        "SampleAfterValue": "2000003",
450        "UMask": "0x81"
451    },
452    {
453        "BriefDescription": "All retired store uops. (Precise Event)",
454        "EventCode": "0xD0",
455        "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
456        "PEBS": "1",
457        "SampleAfterValue": "2000003",
458        "UMask": "0x82"
459    },
460    {
461        "BriefDescription": "Retired load uops with locked access. (Precise Event)",
462        "EventCode": "0xD0",
463        "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
464        "PEBS": "1",
465        "SampleAfterValue": "100007",
466        "UMask": "0x21"
467    },
468    {
469        "BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event)",
470        "EventCode": "0xD0",
471        "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
472        "PEBS": "1",
473        "SampleAfterValue": "100003",
474        "UMask": "0x41"
475    },
476    {
477        "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event)",
478        "EventCode": "0xD0",
479        "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
480        "PEBS": "1",
481        "SampleAfterValue": "100003",
482        "UMask": "0x42"
483    },
484    {
485        "BriefDescription": "Retired load uops that miss the STLB. (Precise Event)",
486        "EventCode": "0xD0",
487        "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
488        "PEBS": "1",
489        "SampleAfterValue": "100003",
490        "UMask": "0x11"
491    },
492    {
493        "BriefDescription": "Retired store uops that miss the STLB. (Precise Event)",
494        "EventCode": "0xD0",
495        "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
496        "PEBS": "1",
497        "SampleAfterValue": "100003",
498        "UMask": "0x12"
499    },
500    {
501        "BriefDescription": "Demand and prefetch data reads",
502        "EventCode": "0xB0",
503        "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
504        "PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
505        "SampleAfterValue": "100003",
506        "UMask": "0x8"
507    },
508    {
509        "BriefDescription": "Cacheable and noncachaeble code read requests",
510        "EventCode": "0xB0",
511        "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
512        "PublicDescription": "Demand code read requests sent to uncore.",
513        "SampleAfterValue": "100003",
514        "UMask": "0x2"
515    },
516    {
517        "BriefDescription": "Demand Data Read requests sent to uncore",
518        "EventCode": "0xB0",
519        "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
520        "PublicDescription": "Demand data read requests sent to uncore.",
521        "SampleAfterValue": "100003",
522        "UMask": "0x1"
523    },
524    {
525        "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
526        "EventCode": "0xB0",
527        "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
528        "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
529        "SampleAfterValue": "100003",
530        "UMask": "0x4"
531    },
532    {
533        "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core",
534        "EventCode": "0xB2",
535        "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
536        "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.",
537        "SampleAfterValue": "2000003",
538        "UMask": "0x1"
539    },
540    {
541        "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
542        "EventCode": "0x60",
543        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
544        "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
545        "SampleAfterValue": "2000003",
546        "UMask": "0x8"
547    },
548    {
549        "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
550        "CounterMask": "1",
551        "EventCode": "0x60",
552        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
553        "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
554        "SampleAfterValue": "2000003",
555        "UMask": "0x8"
556    },
557    {
558        "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
559        "CounterMask": "1",
560        "EventCode": "0x60",
561        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
562        "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
563        "SampleAfterValue": "2000003",
564        "UMask": "0x2"
565    },
566    {
567        "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
568        "CounterMask": "1",
569        "EventCode": "0x60",
570        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
571        "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
572        "SampleAfterValue": "2000003",
573        "UMask": "0x1"
574    },
575    {
576        "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
577        "CounterMask": "1",
578        "EventCode": "0x60",
579        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
580        "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
581        "SampleAfterValue": "2000003",
582        "UMask": "0x4"
583    },
584    {
585        "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
586        "EventCode": "0x60",
587        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
588        "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
589        "SampleAfterValue": "2000003",
590        "UMask": "0x2"
591    },
592    {
593        "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
594        "EventCode": "0x60",
595        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
596        "PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
597        "SampleAfterValue": "2000003",
598        "UMask": "0x1"
599    },
600    {
601        "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",
602        "CounterMask": "6",
603        "EventCode": "0x60",
604        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
605        "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
606        "SampleAfterValue": "2000003",
607        "UMask": "0x1"
608    },
609    {
610        "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
611        "EventCode": "0x60",
612        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
613        "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",
614        "SampleAfterValue": "2000003",
615        "UMask": "0x4"
616    },
617    {
618        "BriefDescription": "Counts all demand & prefetch code reads that hit in the LLC",
619        "EventCode": "0xB7, 0xBB",
620        "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE",
621        "MSRIndex": "0x1a6,0x1a7",
622        "MSRValue": "0x3f803c0244",
623        "SampleAfterValue": "100003",
624        "UMask": "0x1"
625    },
626    {
627        "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
628        "EventCode": "0xB7, 0xBB",
629        "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
630        "MSRIndex": "0x1a6,0x1a7",
631        "MSRValue": "0x1003c0244",
632        "SampleAfterValue": "100003",
633        "UMask": "0x1"
634    },
635    {
636        "BriefDescription": "Counts all demand & prefetch data reads",
637        "EventCode": "0xB7, 0xBB",
638        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",
639        "MSRIndex": "0x1a6,0x1a7",
640        "MSRValue": "0x000105B3",
641        "SampleAfterValue": "100003",
642        "UMask": "0x1"
643    },
644    {
645        "BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC",
646        "EventCode": "0xB7, 0xBB",
647        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE",
648        "MSRIndex": "0x1a6,0x1a7",
649        "MSRValue": "0x3f803c0091",
650        "SampleAfterValue": "100003",
651        "UMask": "0x1"
652    },
653    {
654        "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
655        "EventCode": "0xB7, 0xBB",
656        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
657        "MSRIndex": "0x1a6,0x1a7",
658        "MSRValue": "0x10003c0091",
659        "SampleAfterValue": "100003",
660        "UMask": "0x1"
661    },
662    {
663        "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
664        "EventCode": "0xB7, 0xBB",
665        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
666        "MSRIndex": "0x1a6,0x1a7",
667        "MSRValue": "0x4003c0091",
668        "SampleAfterValue": "100003",
669        "UMask": "0x1"
670    },
671    {
672        "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
673        "EventCode": "0xB7, 0xBB",
674        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
675        "MSRIndex": "0x1a6,0x1a7",
676        "MSRValue": "0x1003c0091",
677        "SampleAfterValue": "100003",
678        "UMask": "0x1"
679    },
680    {
681        "BriefDescription": "Counts all data/code/rfo references (demand & prefetch)",
682        "EventCode": "0xB7, 0xBB",
683        "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE",
684        "MSRIndex": "0x1a6,0x1a7",
685        "MSRValue": "0x000107F7",
686        "SampleAfterValue": "100003",
687        "UMask": "0x1"
688    },
689    {
690        "BriefDescription": "Counts all demand & prefetch prefetch RFOs",
691        "EventCode": "0xB7, 0xBB",
692        "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
693        "MSRIndex": "0x1a6,0x1a7",
694        "MSRValue": "0x00010122",
695        "SampleAfterValue": "100003",
696        "UMask": "0x1"
697    },
698    {
699        "BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC",
700        "EventCode": "0xB7, 0xBB",
701        "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE",
702        "MSRIndex": "0x1a6,0x1a7",
703        "MSRValue": "0x3f803c0122",
704        "SampleAfterValue": "100003",
705        "UMask": "0x1"
706    },
707    {
708        "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
709        "EventCode": "0xB7, 0xBB",
710        "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED",
711        "MSRIndex": "0x1a6,0x1a7",
712        "MSRValue": "0x1003c0122",
713        "SampleAfterValue": "100003",
714        "UMask": "0x1"
715    },
716    {
717        "BriefDescription": "Counts all writebacks from the core to the LLC",
718        "EventCode": "0xB7, 0xBB",
719        "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
720        "MSRIndex": "0x1a6,0x1a7",
721        "MSRValue": "0x10008",
722        "SampleAfterValue": "100003",
723        "UMask": "0x1"
724    },
725    {
726        "BriefDescription": "Counts all demand code reads",
727        "EventCode": "0xB7, 0xBB",
728        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
729        "MSRIndex": "0x1a6,0x1a7",
730        "MSRValue": "0x00010004",
731        "SampleAfterValue": "100003",
732        "UMask": "0x1"
733    },
734    {
735        "BriefDescription": "Counts all demand code reads that hit in the LLC",
736        "EventCode": "0xB7, 0xBB",
737        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
738        "MSRIndex": "0x1a6,0x1a7",
739        "MSRValue": "0x3f803c0004",
740        "SampleAfterValue": "100003",
741        "UMask": "0x1"
742    },
743    {
744        "BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
745        "EventCode": "0xB7, 0xBB",
746        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
747        "MSRIndex": "0x1a6,0x1a7",
748        "MSRValue": "0x1003c0004",
749        "SampleAfterValue": "100003",
750        "UMask": "0x1"
751    },
752    {
753        "BriefDescription": "Counts all demand data reads",
754        "EventCode": "0xB7, 0xBB",
755        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
756        "MSRIndex": "0x1a6,0x1a7",
757        "MSRValue": "0x00010001",
758        "SampleAfterValue": "100003",
759        "UMask": "0x1"
760    },
761    {
762        "BriefDescription": "Counts all demand data reads that hit in the LLC",
763        "EventCode": "0xB7, 0xBB",
764        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
765        "MSRIndex": "0x1a6,0x1a7",
766        "MSRValue": "0x3f803c0001",
767        "SampleAfterValue": "100003",
768        "UMask": "0x1"
769    },
770    {
771        "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
772        "EventCode": "0xB7, 0xBB",
773        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
774        "MSRIndex": "0x1a6,0x1a7",
775        "MSRValue": "0x10003c0001",
776        "SampleAfterValue": "100003",
777        "UMask": "0x1"
778    },
779    {
780        "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
781        "EventCode": "0xB7, 0xBB",
782        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
783        "MSRIndex": "0x1a6,0x1a7",
784        "MSRValue": "0x4003c0001",
785        "SampleAfterValue": "100003",
786        "UMask": "0x1"
787    },
788    {
789        "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
790        "EventCode": "0xB7, 0xBB",
791        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
792        "MSRIndex": "0x1a6,0x1a7",
793        "MSRValue": "0x1003c0001",
794        "SampleAfterValue": "100003",
795        "UMask": "0x1"
796    },
797    {
798        "BriefDescription": "Counts all demand rfo's",
799        "EventCode": "0xB7, 0xBB",
800        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
801        "MSRIndex": "0x1a6,0x1a7",
802        "MSRValue": "0x00010002",
803        "SampleAfterValue": "100003",
804        "UMask": "0x1"
805    },
806    {
807        "BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC",
808        "EventCode": "0xB7, 0xBB",
809        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE",
810        "MSRIndex": "0x1a6,0x1a7",
811        "MSRValue": "0x3f803c0002",
812        "SampleAfterValue": "100003",
813        "UMask": "0x1"
814    },
815    {
816        "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
817        "EventCode": "0xB7, 0xBB",
818        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
819        "MSRIndex": "0x1a6,0x1a7",
820        "MSRValue": "0x10003c0002",
821        "SampleAfterValue": "100003",
822        "UMask": "0x1"
823    },
824    {
825        "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
826        "EventCode": "0xB7, 0xBB",
827        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED",
828        "MSRIndex": "0x1a6,0x1a7",
829        "MSRValue": "0x1003c0002",
830        "SampleAfterValue": "100003",
831        "UMask": "0x1"
832    },
833    {
834        "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches",
835        "EventCode": "0xB7, 0xBB",
836        "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",
837        "MSRIndex": "0x1a6,0x1a7",
838        "MSRValue": "0x18000",
839        "SampleAfterValue": "100003",
840        "UMask": "0x1"
841    },
842    {
843        "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",
844        "EventCode": "0xB7, 0xBB",
845        "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
846        "MSRIndex": "0x1a6,0x1a7",
847        "MSRValue": "0x10400",
848        "SampleAfterValue": "100003",
849        "UMask": "0x1"
850    },
851    {
852        "BriefDescription": "Counts non-temporal stores",
853        "EventCode": "0xB7, 0xBB",
854        "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
855        "MSRIndex": "0x1a6,0x1a7",
856        "MSRValue": "0x10800",
857        "SampleAfterValue": "100003",
858        "UMask": "0x1"
859    },
860    {
861        "BriefDescription": "Split locks in SQ",
862        "EventCode": "0xF4",
863        "EventName": "SQ_MISC.SPLIT_LOCK",
864        "SampleAfterValue": "100003",
865        "UMask": "0x10"
866    }
867]
868