1[ 2 { 3 "PublicDescription": "Demand Data Read requests that hit L2 cache.", 4 "EventCode": "0x24", 5 "Counter": "0,1,2,3", 6 "UMask": "0x1", 7 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", 8 "SampleAfterValue": "200003", 9 "BriefDescription": "Demand Data Read requests that hit L2 cache", 10 "CounterHTOff": "0,1,2,3,4,5,6,7" 11 }, 12 { 13 "PublicDescription": "RFO requests that hit L2 cache.", 14 "EventCode": "0x24", 15 "Counter": "0,1,2,3", 16 "UMask": "0x4", 17 "EventName": "L2_RQSTS.RFO_HIT", 18 "SampleAfterValue": "200003", 19 "BriefDescription": "RFO requests that hit L2 cache", 20 "CounterHTOff": "0,1,2,3,4,5,6,7" 21 }, 22 { 23 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", 24 "EventCode": "0x24", 25 "Counter": "0,1,2,3", 26 "UMask": "0x8", 27 "EventName": "L2_RQSTS.RFO_MISS", 28 "SampleAfterValue": "200003", 29 "BriefDescription": "RFO requests that miss L2 cache", 30 "CounterHTOff": "0,1,2,3,4,5,6,7" 31 }, 32 { 33 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 34 "EventCode": "0x24", 35 "Counter": "0,1,2,3", 36 "UMask": "0x10", 37 "EventName": "L2_RQSTS.CODE_RD_HIT", 38 "SampleAfterValue": "200003", 39 "BriefDescription": "L2 cache hits when fetching instructions, code reads.", 40 "CounterHTOff": "0,1,2,3,4,5,6,7" 41 }, 42 { 43 "PublicDescription": "Number of instruction fetches that missed the L2 cache.", 44 "EventCode": "0x24", 45 "Counter": "0,1,2,3", 46 "UMask": "0x20", 47 "EventName": "L2_RQSTS.CODE_RD_MISS", 48 "SampleAfterValue": "200003", 49 "BriefDescription": "L2 cache misses when fetching instructions", 50 "CounterHTOff": "0,1,2,3,4,5,6,7" 51 }, 52 { 53 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 54 "EventCode": "0x24", 55 "Counter": "0,1,2,3", 56 "UMask": "0x40", 57 "EventName": "L2_RQSTS.PF_HIT", 58 "SampleAfterValue": "200003", 59 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache", 60 "CounterHTOff": "0,1,2,3,4,5,6,7" 61 }, 62 { 63 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", 64 "EventCode": "0x24", 65 "Counter": "0,1,2,3", 66 "UMask": "0x80", 67 "EventName": "L2_RQSTS.PF_MISS", 68 "SampleAfterValue": "200003", 69 "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache", 70 "CounterHTOff": "0,1,2,3,4,5,6,7" 71 }, 72 { 73 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", 74 "EventCode": "0x24", 75 "Counter": "0,1,2,3", 76 "UMask": "0x3", 77 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", 78 "SampleAfterValue": "200003", 79 "BriefDescription": "Demand Data Read requests", 80 "CounterHTOff": "0,1,2,3,4,5,6,7" 81 }, 82 { 83 "PublicDescription": "Counts all L2 store RFO requests.", 84 "EventCode": "0x24", 85 "Counter": "0,1,2,3", 86 "UMask": "0xc", 87 "EventName": "L2_RQSTS.ALL_RFO", 88 "SampleAfterValue": "200003", 89 "BriefDescription": "RFO requests to L2 cache", 90 "CounterHTOff": "0,1,2,3,4,5,6,7" 91 }, 92 { 93 "PublicDescription": "Counts all L2 code requests.", 94 "EventCode": "0x24", 95 "Counter": "0,1,2,3", 96 "UMask": "0x30", 97 "EventName": "L2_RQSTS.ALL_CODE_RD", 98 "SampleAfterValue": "200003", 99 "BriefDescription": "L2 code requests", 100 "CounterHTOff": "0,1,2,3,4,5,6,7" 101 }, 102 { 103 "PublicDescription": "Counts all L2 HW prefetcher requests.", 104 "EventCode": "0x24", 105 "Counter": "0,1,2,3", 106 "UMask": "0xc0", 107 "EventName": "L2_RQSTS.ALL_PF", 108 "SampleAfterValue": "200003", 109 "BriefDescription": "Requests from L2 hardware prefetchers", 110 "CounterHTOff": "0,1,2,3,4,5,6,7" 111 }, 112 { 113 "PublicDescription": "RFOs that miss cache lines.", 114 "EventCode": "0x27", 115 "Counter": "0,1,2,3", 116 "UMask": "0x1", 117 "EventName": "L2_STORE_LOCK_RQSTS.MISS", 118 "SampleAfterValue": "200003", 119 "BriefDescription": "RFOs that miss cache lines", 120 "CounterHTOff": "0,1,2,3,4,5,6,7" 121 }, 122 { 123 "PublicDescription": "RFOs that hit cache lines in M state.", 124 "EventCode": "0x27", 125 "Counter": "0,1,2,3", 126 "UMask": "0x8", 127 "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", 128 "SampleAfterValue": "200003", 129 "BriefDescription": "RFOs that hit cache lines in M state", 130 "CounterHTOff": "0,1,2,3,4,5,6,7" 131 }, 132 { 133 "PublicDescription": "RFOs that access cache lines in any state.", 134 "EventCode": "0x27", 135 "Counter": "0,1,2,3", 136 "UMask": "0xf", 137 "EventName": "L2_STORE_LOCK_RQSTS.ALL", 138 "SampleAfterValue": "200003", 139 "BriefDescription": "RFOs that access cache lines in any state", 140 "CounterHTOff": "0,1,2,3,4,5,6,7" 141 }, 142 { 143 "PublicDescription": "Not rejected writebacks that missed LLC.", 144 "EventCode": "0x28", 145 "Counter": "0,1,2,3", 146 "UMask": "0x1", 147 "EventName": "L2_L1D_WB_RQSTS.MISS", 148 "SampleAfterValue": "200003", 149 "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)", 150 "CounterHTOff": "0,1,2,3,4,5,6,7" 151 }, 152 { 153 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", 154 "EventCode": "0x28", 155 "Counter": "0,1,2,3", 156 "UMask": "0x4", 157 "EventName": "L2_L1D_WB_RQSTS.HIT_E", 158 "SampleAfterValue": "200003", 159 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state", 160 "CounterHTOff": "0,1,2,3,4,5,6,7" 161 }, 162 { 163 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", 164 "EventCode": "0x28", 165 "Counter": "0,1,2,3", 166 "UMask": "0x8", 167 "EventName": "L2_L1D_WB_RQSTS.HIT_M", 168 "SampleAfterValue": "200003", 169 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state", 170 "CounterHTOff": "0,1,2,3,4,5,6,7" 171 }, 172 { 173 "EventCode": "0x28", 174 "Counter": "0,1,2,3", 175 "UMask": "0xf", 176 "EventName": "L2_L1D_WB_RQSTS.ALL", 177 "SampleAfterValue": "200003", 178 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", 179 "CounterHTOff": "0,1,2,3,4,5,6,7" 180 }, 181 { 182 "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", 183 "EventCode": "0x2E", 184 "Counter": "0,1,2,3", 185 "UMask": "0x41", 186 "EventName": "LONGEST_LAT_CACHE.MISS", 187 "SampleAfterValue": "100003", 188 "BriefDescription": "Core-originated cacheable demand requests missed LLC", 189 "CounterHTOff": "0,1,2,3,4,5,6,7" 190 }, 191 { 192 "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", 193 "EventCode": "0x2E", 194 "Counter": "0,1,2,3", 195 "UMask": "0x4f", 196 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 197 "SampleAfterValue": "100003", 198 "BriefDescription": "Core-originated cacheable demand requests that refer to LLC", 199 "CounterHTOff": "0,1,2,3,4,5,6,7" 200 }, 201 { 202 "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", 203 "EventCode": "0x48", 204 "Counter": "2", 205 "UMask": "0x1", 206 "EventName": "L1D_PEND_MISS.PENDING", 207 "SampleAfterValue": "2000003", 208 "BriefDescription": "L1D miss oustandings duration in cycles", 209 "CounterHTOff": "2" 210 }, 211 { 212 "EventCode": "0x48", 213 "Counter": "2", 214 "UMask": "0x1", 215 "EventName": "L1D_PEND_MISS.PENDING_CYCLES", 216 "SampleAfterValue": "2000003", 217 "BriefDescription": "Cycles with L1D load Misses outstanding.", 218 "CounterMask": "1", 219 "CounterHTOff": "2" 220 }, 221 { 222 "PublicDescription": "Counts the number of lines brought into the L1 data cache.", 223 "EventCode": "0x51", 224 "Counter": "0,1,2,3", 225 "UMask": "0x1", 226 "EventName": "L1D.REPLACEMENT", 227 "SampleAfterValue": "2000003", 228 "BriefDescription": "L1D data line replacements", 229 "CounterHTOff": "0,1,2,3,4,5,6,7" 230 }, 231 { 232 "PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 233 "EventCode": "0x60", 234 "Counter": "0,1,2,3", 235 "UMask": "0x1", 236 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", 237 "SampleAfterValue": "2000003", 238 "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", 239 "CounterHTOff": "0,1,2,3,4,5,6,7" 240 }, 241 { 242 "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 243 "EventCode": "0x60", 244 "Counter": "0,1,2,3", 245 "UMask": "0x2", 246 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", 247 "SampleAfterValue": "2000003", 248 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 249 "CounterHTOff": "0,1,2,3,4,5,6,7" 250 }, 251 { 252 "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", 253 "EventCode": "0x60", 254 "Counter": "0,1,2,3", 255 "UMask": "0x4", 256 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", 257 "SampleAfterValue": "2000003", 258 "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", 259 "CounterHTOff": "0,1,2,3,4,5,6,7" 260 }, 261 { 262 "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 263 "EventCode": "0x60", 264 "Counter": "0,1,2,3", 265 "UMask": "0x8", 266 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 267 "SampleAfterValue": "2000003", 268 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", 269 "CounterHTOff": "0,1,2,3,4,5,6,7" 270 }, 271 { 272 "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 273 "EventCode": "0x60", 274 "Counter": "0,1,2,3", 275 "UMask": "0x1", 276 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", 277 "SampleAfterValue": "2000003", 278 "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", 279 "CounterMask": "1", 280 "CounterHTOff": "0,1,2,3,4,5,6,7" 281 }, 282 { 283 "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 284 "EventCode": "0x60", 285 "Counter": "0,1,2,3", 286 "UMask": "0x8", 287 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", 288 "SampleAfterValue": "2000003", 289 "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", 290 "CounterMask": "1", 291 "CounterHTOff": "0,1,2,3,4,5,6,7" 292 }, 293 { 294 "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", 295 "EventCode": "0x60", 296 "Counter": "0,1,2,3", 297 "UMask": "0x2", 298 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", 299 "SampleAfterValue": "2000003", 300 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 301 "CounterMask": "1", 302 "CounterHTOff": "0,1,2,3,4,5,6,7" 303 }, 304 { 305 "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", 306 "EventCode": "0x60", 307 "Counter": "0,1,2,3", 308 "UMask": "0x4", 309 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", 310 "SampleAfterValue": "2000003", 311 "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 312 "CounterMask": "1", 313 "CounterHTOff": "0,1,2,3,4,5,6,7" 314 }, 315 { 316 "PublicDescription": "Cycles in which the L1D is locked.", 317 "EventCode": "0x63", 318 "Counter": "0,1,2,3", 319 "UMask": "0x2", 320 "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", 321 "SampleAfterValue": "2000003", 322 "BriefDescription": "Cycles when L1D is locked", 323 "CounterHTOff": "0,1,2,3,4,5,6,7" 324 }, 325 { 326 "PublicDescription": "Demand data read requests sent to uncore.", 327 "EventCode": "0xB0", 328 "Counter": "0,1,2,3", 329 "UMask": "0x1", 330 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", 331 "SampleAfterValue": "100003", 332 "BriefDescription": "Demand Data Read requests sent to uncore", 333 "CounterHTOff": "0,1,2,3,4,5,6,7" 334 }, 335 { 336 "PublicDescription": "Demand code read requests sent to uncore.", 337 "EventCode": "0xB0", 338 "Counter": "0,1,2,3", 339 "UMask": "0x2", 340 "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", 341 "SampleAfterValue": "100003", 342 "BriefDescription": "Cacheable and noncachaeble code read requests", 343 "CounterHTOff": "0,1,2,3,4,5,6,7" 344 }, 345 { 346 "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", 347 "EventCode": "0xB0", 348 "Counter": "0,1,2,3", 349 "UMask": "0x4", 350 "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", 351 "SampleAfterValue": "100003", 352 "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", 353 "CounterHTOff": "0,1,2,3,4,5,6,7" 354 }, 355 { 356 "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", 357 "EventCode": "0xB0", 358 "Counter": "0,1,2,3", 359 "UMask": "0x8", 360 "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", 361 "SampleAfterValue": "100003", 362 "BriefDescription": "Demand and prefetch data reads", 363 "CounterHTOff": "0,1,2,3,4,5,6,7" 364 }, 365 { 366 "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.", 367 "EventCode": "0xB2", 368 "Counter": "0,1,2,3", 369 "UMask": "0x1", 370 "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", 371 "SampleAfterValue": "2000003", 372 "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core", 373 "CounterHTOff": "0,1,2,3,4,5,6,7" 374 }, 375 { 376 "PEBS": "1", 377 "EventCode": "0xD0", 378 "Counter": "0,1,2,3", 379 "UMask": "0x11", 380 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", 381 "SampleAfterValue": "100003", 382 "BriefDescription": "Retired load uops that miss the STLB.", 383 "CounterHTOff": "0,1,2,3" 384 }, 385 { 386 "PEBS": "1", 387 "EventCode": "0xD0", 388 "Counter": "0,1,2,3", 389 "UMask": "0x12", 390 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", 391 "SampleAfterValue": "100003", 392 "BriefDescription": "Retired store uops that miss the STLB.", 393 "CounterHTOff": "0,1,2,3" 394 }, 395 { 396 "PEBS": "1", 397 "EventCode": "0xD0", 398 "Counter": "0,1,2,3", 399 "UMask": "0x21", 400 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", 401 "SampleAfterValue": "100007", 402 "BriefDescription": "Retired load uops with locked access.", 403 "CounterHTOff": "0,1,2,3" 404 }, 405 { 406 "PEBS": "1", 407 "EventCode": "0xD0", 408 "Counter": "0,1,2,3", 409 "UMask": "0x41", 410 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", 411 "SampleAfterValue": "100003", 412 "BriefDescription": "Retired load uops that split across a cacheline boundary.", 413 "CounterHTOff": "0,1,2,3" 414 }, 415 { 416 "PEBS": "1", 417 "EventCode": "0xD0", 418 "Counter": "0,1,2,3", 419 "UMask": "0x42", 420 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", 421 "SampleAfterValue": "100003", 422 "BriefDescription": "Retired store uops that split across a cacheline boundary.", 423 "CounterHTOff": "0,1,2,3" 424 }, 425 { 426 "PEBS": "1", 427 "EventCode": "0xD0", 428 "Counter": "0,1,2,3", 429 "UMask": "0x81", 430 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", 431 "SampleAfterValue": "2000003", 432 "BriefDescription": "All retired load uops.", 433 "CounterHTOff": "0,1,2,3" 434 }, 435 { 436 "PEBS": "1", 437 "EventCode": "0xD0", 438 "Counter": "0,1,2,3", 439 "UMask": "0x82", 440 "EventName": "MEM_UOPS_RETIRED.ALL_STORES", 441 "SampleAfterValue": "2000003", 442 "BriefDescription": "All retired store uops.", 443 "CounterHTOff": "0,1,2,3" 444 }, 445 { 446 "PEBS": "1", 447 "PublicDescription": "Retired load uops with L1 cache hits as data sources.", 448 "EventCode": "0xD1", 449 "Counter": "0,1,2,3", 450 "UMask": "0x1", 451 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", 452 "SampleAfterValue": "2000003", 453 "BriefDescription": "Retired load uops with L1 cache hits as data sources. ", 454 "CounterHTOff": "0,1,2,3" 455 }, 456 { 457 "PEBS": "1", 458 "PublicDescription": "Retired load uops with L2 cache hits as data sources.", 459 "EventCode": "0xD1", 460 "Counter": "0,1,2,3", 461 "UMask": "0x2", 462 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", 463 "SampleAfterValue": "100003", 464 "BriefDescription": "Retired load uops with L2 cache hits as data sources. ", 465 "CounterHTOff": "0,1,2,3" 466 }, 467 { 468 "PEBS": "1", 469 "PublicDescription": "Retired load uops whose data source was LLC hit with no snoop required.", 470 "EventCode": "0xD1", 471 "Counter": "0,1,2,3", 472 "UMask": "0x4", 473 "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", 474 "SampleAfterValue": "50021", 475 "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required. ", 476 "CounterHTOff": "0,1,2,3" 477 }, 478 { 479 "PEBS": "1", 480 "PublicDescription": "Retired load uops whose data source followed an L1 miss.", 481 "EventCode": "0xD1", 482 "Counter": "0,1,2,3", 483 "UMask": "0x8", 484 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", 485 "SampleAfterValue": "100003", 486 "BriefDescription": "Retired load uops which data sources following L1 data-cache miss", 487 "CounterHTOff": "0,1,2,3" 488 }, 489 { 490 "PEBS": "1", 491 "PublicDescription": "Retired load uops that missed L2, excluding unknown sources.", 492 "EventCode": "0xD1", 493 "Counter": "0,1,2,3", 494 "UMask": "0x10", 495 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", 496 "SampleAfterValue": "50021", 497 "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", 498 "CounterHTOff": "0,1,2,3" 499 }, 500 { 501 "PEBS": "1", 502 "PublicDescription": "Retired load uops whose data source is LLC miss.", 503 "EventCode": "0xD1", 504 "Counter": "0,1,2,3", 505 "UMask": "0x20", 506 "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", 507 "SampleAfterValue": "100007", 508 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", 509 "CounterHTOff": "0,1,2,3" 510 }, 511 { 512 "PEBS": "1", 513 "PublicDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", 514 "EventCode": "0xD1", 515 "Counter": "0,1,2,3", 516 "UMask": "0x40", 517 "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", 518 "SampleAfterValue": "100003", 519 "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. ", 520 "CounterHTOff": "0,1,2,3" 521 }, 522 { 523 "PEBS": "1", 524 "PublicDescription": "Retired load uops whose data source was an on-package core cache LLC hit and cross-core snoop missed.", 525 "EventCode": "0xD2", 526 "Counter": "0,1,2,3", 527 "UMask": "0x1", 528 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", 529 "SampleAfterValue": "20011", 530 "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. ", 531 "CounterHTOff": "0,1,2,3" 532 }, 533 { 534 "PEBS": "1", 535 "PublicDescription": "Retired load uops whose data source was an on-package LLC hit and cross-core snoop hits.", 536 "EventCode": "0xD2", 537 "Counter": "0,1,2,3", 538 "UMask": "0x2", 539 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", 540 "SampleAfterValue": "20011", 541 "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. ", 542 "CounterHTOff": "0,1,2,3" 543 }, 544 { 545 "PEBS": "1", 546 "PublicDescription": "Retired load uops whose data source was an on-package core cache with HitM responses.", 547 "EventCode": "0xD2", 548 "Counter": "0,1,2,3", 549 "UMask": "0x4", 550 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", 551 "SampleAfterValue": "20011", 552 "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC. ", 553 "CounterHTOff": "0,1,2,3" 554 }, 555 { 556 "PEBS": "1", 557 "PublicDescription": "Retired load uops whose data source was LLC hit with no snoop required.", 558 "EventCode": "0xD2", 559 "Counter": "0,1,2,3", 560 "UMask": "0x8", 561 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", 562 "SampleAfterValue": "100003", 563 "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required. ", 564 "CounterHTOff": "0,1,2,3" 565 }, 566 { 567 "PublicDescription": "Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI)", 568 "EventCode": "0xD3", 569 "Counter": "0,1,2,3", 570 "UMask": "0x1", 571 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", 572 "SampleAfterValue": "100007", 573 "BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.", 574 "CounterHTOff": "0,1,2,3" 575 }, 576 { 577 "PublicDescription": "Demand Data Read requests that access L2 cache.", 578 "EventCode": "0xF0", 579 "Counter": "0,1,2,3", 580 "UMask": "0x1", 581 "EventName": "L2_TRANS.DEMAND_DATA_RD", 582 "SampleAfterValue": "200003", 583 "BriefDescription": "Demand Data Read requests that access L2 cache", 584 "CounterHTOff": "0,1,2,3,4,5,6,7" 585 }, 586 { 587 "PublicDescription": "RFO requests that access L2 cache.", 588 "EventCode": "0xF0", 589 "Counter": "0,1,2,3", 590 "UMask": "0x2", 591 "EventName": "L2_TRANS.RFO", 592 "SampleAfterValue": "200003", 593 "BriefDescription": "RFO requests that access L2 cache", 594 "CounterHTOff": "0,1,2,3,4,5,6,7" 595 }, 596 { 597 "PublicDescription": "L2 cache accesses when fetching instructions.", 598 "EventCode": "0xF0", 599 "Counter": "0,1,2,3", 600 "UMask": "0x4", 601 "EventName": "L2_TRANS.CODE_RD", 602 "SampleAfterValue": "200003", 603 "BriefDescription": "L2 cache accesses when fetching instructions", 604 "CounterHTOff": "0,1,2,3,4,5,6,7" 605 }, 606 { 607 "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.", 608 "EventCode": "0xF0", 609 "Counter": "0,1,2,3", 610 "UMask": "0x8", 611 "EventName": "L2_TRANS.ALL_PF", 612 "SampleAfterValue": "200003", 613 "BriefDescription": "L2 or LLC HW prefetches that access L2 cache", 614 "CounterHTOff": "0,1,2,3,4,5,6,7" 615 }, 616 { 617 "PublicDescription": "L1D writebacks that access L2 cache.", 618 "EventCode": "0xF0", 619 "Counter": "0,1,2,3", 620 "UMask": "0x10", 621 "EventName": "L2_TRANS.L1D_WB", 622 "SampleAfterValue": "200003", 623 "BriefDescription": "L1D writebacks that access L2 cache", 624 "CounterHTOff": "0,1,2,3,4,5,6,7" 625 }, 626 { 627 "PublicDescription": "L2 fill requests that access L2 cache.", 628 "EventCode": "0xF0", 629 "Counter": "0,1,2,3", 630 "UMask": "0x20", 631 "EventName": "L2_TRANS.L2_FILL", 632 "SampleAfterValue": "200003", 633 "BriefDescription": "L2 fill requests that access L2 cache", 634 "CounterHTOff": "0,1,2,3,4,5,6,7" 635 }, 636 { 637 "PublicDescription": "L2 writebacks that access L2 cache.", 638 "EventCode": "0xF0", 639 "Counter": "0,1,2,3", 640 "UMask": "0x40", 641 "EventName": "L2_TRANS.L2_WB", 642 "SampleAfterValue": "200003", 643 "BriefDescription": "L2 writebacks that access L2 cache", 644 "CounterHTOff": "0,1,2,3,4,5,6,7" 645 }, 646 { 647 "PublicDescription": "Transactions accessing L2 pipe.", 648 "EventCode": "0xF0", 649 "Counter": "0,1,2,3", 650 "UMask": "0x80", 651 "EventName": "L2_TRANS.ALL_REQUESTS", 652 "SampleAfterValue": "200003", 653 "BriefDescription": "Transactions accessing L2 pipe", 654 "CounterHTOff": "0,1,2,3,4,5,6,7" 655 }, 656 { 657 "PublicDescription": "L2 cache lines in I state filling L2.", 658 "EventCode": "0xF1", 659 "Counter": "0,1,2,3", 660 "UMask": "0x1", 661 "EventName": "L2_LINES_IN.I", 662 "SampleAfterValue": "100003", 663 "BriefDescription": "L2 cache lines in I state filling L2", 664 "CounterHTOff": "0,1,2,3,4,5,6,7" 665 }, 666 { 667 "PublicDescription": "L2 cache lines in S state filling L2.", 668 "EventCode": "0xF1", 669 "Counter": "0,1,2,3", 670 "UMask": "0x2", 671 "EventName": "L2_LINES_IN.S", 672 "SampleAfterValue": "100003", 673 "BriefDescription": "L2 cache lines in S state filling L2", 674 "CounterHTOff": "0,1,2,3,4,5,6,7" 675 }, 676 { 677 "PublicDescription": "L2 cache lines in E state filling L2.", 678 "EventCode": "0xF1", 679 "Counter": "0,1,2,3", 680 "UMask": "0x4", 681 "EventName": "L2_LINES_IN.E", 682 "SampleAfterValue": "100003", 683 "BriefDescription": "L2 cache lines in E state filling L2", 684 "CounterHTOff": "0,1,2,3,4,5,6,7" 685 }, 686 { 687 "PublicDescription": "L2 cache lines filling L2.", 688 "EventCode": "0xF1", 689 "Counter": "0,1,2,3", 690 "UMask": "0x7", 691 "EventName": "L2_LINES_IN.ALL", 692 "SampleAfterValue": "100003", 693 "BriefDescription": "L2 cache lines filling L2", 694 "CounterHTOff": "0,1,2,3,4,5,6,7" 695 }, 696 { 697 "PublicDescription": "Clean L2 cache lines evicted by demand.", 698 "EventCode": "0xF2", 699 "Counter": "0,1,2,3", 700 "UMask": "0x1", 701 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 702 "SampleAfterValue": "100003", 703 "BriefDescription": "Clean L2 cache lines evicted by demand", 704 "CounterHTOff": "0,1,2,3,4,5,6,7" 705 }, 706 { 707 "PublicDescription": "Dirty L2 cache lines evicted by demand.", 708 "EventCode": "0xF2", 709 "Counter": "0,1,2,3", 710 "UMask": "0x2", 711 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 712 "SampleAfterValue": "100003", 713 "BriefDescription": "Dirty L2 cache lines evicted by demand", 714 "CounterHTOff": "0,1,2,3,4,5,6,7" 715 }, 716 { 717 "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.", 718 "EventCode": "0xF2", 719 "Counter": "0,1,2,3", 720 "UMask": "0x4", 721 "EventName": "L2_LINES_OUT.PF_CLEAN", 722 "SampleAfterValue": "100003", 723 "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch", 724 "CounterHTOff": "0,1,2,3,4,5,6,7" 725 }, 726 { 727 "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.", 728 "EventCode": "0xF2", 729 "Counter": "0,1,2,3", 730 "UMask": "0x8", 731 "EventName": "L2_LINES_OUT.PF_DIRTY", 732 "SampleAfterValue": "100003", 733 "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch", 734 "CounterHTOff": "0,1,2,3,4,5,6,7" 735 }, 736 { 737 "PublicDescription": "Dirty L2 cache lines filling the L2.", 738 "EventCode": "0xF2", 739 "Counter": "0,1,2,3", 740 "UMask": "0xa", 741 "EventName": "L2_LINES_OUT.DIRTY_ALL", 742 "SampleAfterValue": "100003", 743 "BriefDescription": "Dirty L2 cache lines filling the L2", 744 "CounterHTOff": "0,1,2,3,4,5,6,7" 745 }, 746 { 747 "EventCode": "0xF4", 748 "Counter": "0,1,2,3", 749 "UMask": "0x10", 750 "EventName": "SQ_MISC.SPLIT_LOCK", 751 "SampleAfterValue": "100003", 752 "BriefDescription": "Split locks in SQ", 753 "CounterHTOff": "0,1,2,3,4,5,6,7" 754 }, 755 { 756 "PublicDescription": "Retired load uops whose data source was local memory (cross-socket snoop not needed or missed).", 757 "EventCode": "0xD3", 758 "Counter": "0,1,2,3", 759 "UMask": "0x1", 760 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", 761 "SampleAfterValue": "100007", 762 "BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.", 763 "CounterHTOff": "0,1,2,3" 764 }, 765 { 766 "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", 767 "EventCode": "0x60", 768 "Counter": "0,1,2,3", 769 "UMask": "0x1", 770 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", 771 "SampleAfterValue": "2000003", 772 "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue", 773 "CounterMask": "6", 774 "CounterHTOff": "0,1,2,3,4,5,6,7" 775 }, 776 { 777 "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", 778 "EventCode": "0x48", 779 "Counter": "2", 780 "UMask": "0x1", 781 "AnyThread": "1", 782 "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", 783 "SampleAfterValue": "2000003", 784 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core", 785 "CounterMask": "1", 786 "CounterHTOff": "2" 787 }, 788 { 789 "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", 790 "EventCode": "0x48", 791 "Counter": "0,1,2,3", 792 "UMask": "0x2", 793 "EventName": "L1D_PEND_MISS.FB_FULL", 794 "SampleAfterValue": "2000003", 795 "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability", 796 "CounterMask": "1", 797 "CounterHTOff": "0,1,2,3,4,5,6,7" 798 }, 799 { 800 "EventCode": "0xB7, 0xBB", 801 "MSRValue": "0x3f803c0244", 802 "Counter": "0,1,2,3", 803 "UMask": "0x1", 804 "Offcore": "1", 805 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE", 806 "MSRIndex": "0x1a6,0x1a7", 807 "SampleAfterValue": "100003", 808 "BriefDescription": "Counts all demand & prefetch code reads that hit in the LLC", 809 "CounterHTOff": "0,1,2,3" 810 }, 811 { 812 "EventCode": "0xB7, 0xBB", 813 "MSRValue": "0x1003c0244", 814 "Counter": "0,1,2,3", 815 "UMask": "0x1", 816 "Offcore": "1", 817 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", 818 "MSRIndex": "0x1a6,0x1a7", 819 "SampleAfterValue": "100003", 820 "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 821 "CounterHTOff": "0,1,2,3" 822 }, 823 { 824 "EventCode": "0xB7, 0xBB", 825 "MSRValue": "0x3f803c0091", 826 "Counter": "0,1,2,3", 827 "UMask": "0x1", 828 "Offcore": "1", 829 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE", 830 "MSRIndex": "0x1a6,0x1a7", 831 "SampleAfterValue": "100003", 832 "BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC", 833 "CounterHTOff": "0,1,2,3" 834 }, 835 { 836 "EventCode": "0xB7, 0xBB", 837 "MSRValue": "0x4003c0091", 838 "Counter": "0,1,2,3", 839 "UMask": "0x1", 840 "Offcore": "1", 841 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 842 "MSRIndex": "0x1a6,0x1a7", 843 "SampleAfterValue": "100003", 844 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 845 "CounterHTOff": "0,1,2,3" 846 }, 847 { 848 "EventCode": "0xB7, 0xBB", 849 "MSRValue": "0x10003c0091", 850 "Counter": "0,1,2,3", 851 "UMask": "0x1", 852 "Offcore": "1", 853 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 854 "MSRIndex": "0x1a6,0x1a7", 855 "SampleAfterValue": "100003", 856 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 857 "CounterHTOff": "0,1,2,3" 858 }, 859 { 860 "EventCode": "0xB7, 0xBB", 861 "MSRValue": "0x1003c0091", 862 "Counter": "0,1,2,3", 863 "UMask": "0x1", 864 "Offcore": "1", 865 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", 866 "MSRIndex": "0x1a6,0x1a7", 867 "SampleAfterValue": "100003", 868 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 869 "CounterHTOff": "0,1,2,3" 870 }, 871 { 872 "EventCode": "0xB7, 0xBB", 873 "MSRValue": "0x3f803c0122", 874 "Counter": "0,1,2,3", 875 "UMask": "0x1", 876 "Offcore": "1", 877 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE", 878 "MSRIndex": "0x1a6,0x1a7", 879 "SampleAfterValue": "100003", 880 "BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC", 881 "CounterHTOff": "0,1,2,3" 882 }, 883 { 884 "EventCode": "0xB7, 0xBB", 885 "MSRValue": "0x1003c0122", 886 "Counter": "0,1,2,3", 887 "UMask": "0x1", 888 "Offcore": "1", 889 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED", 890 "MSRIndex": "0x1a6,0x1a7", 891 "SampleAfterValue": "100003", 892 "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 893 "CounterHTOff": "0,1,2,3" 894 }, 895 { 896 "EventCode": "0xB7, 0xBB", 897 "MSRValue": "0x10008", 898 "Counter": "0,1,2,3", 899 "UMask": "0x1", 900 "Offcore": "1", 901 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", 902 "MSRIndex": "0x1a6,0x1a7", 903 "SampleAfterValue": "100003", 904 "BriefDescription": "Counts all writebacks from the core to the LLC", 905 "CounterHTOff": "0,1,2,3" 906 }, 907 { 908 "EventCode": "0xB7, 0xBB", 909 "MSRValue": "0x3f803c0004", 910 "Counter": "0,1,2,3", 911 "UMask": "0x1", 912 "Offcore": "1", 913 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE", 914 "MSRIndex": "0x1a6,0x1a7", 915 "SampleAfterValue": "100003", 916 "BriefDescription": "Counts all demand code reads that hit in the LLC", 917 "CounterHTOff": "0,1,2,3" 918 }, 919 { 920 "EventCode": "0xB7, 0xBB", 921 "MSRValue": "0x1003c0004", 922 "Counter": "0,1,2,3", 923 "UMask": "0x1", 924 "Offcore": "1", 925 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", 926 "MSRIndex": "0x1a6,0x1a7", 927 "SampleAfterValue": "100003", 928 "BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 929 "CounterHTOff": "0,1,2,3" 930 }, 931 { 932 "EventCode": "0xB7, 0xBB", 933 "MSRValue": "0x3f803c0001", 934 "Counter": "0,1,2,3", 935 "UMask": "0x1", 936 "Offcore": "1", 937 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE", 938 "MSRIndex": "0x1a6,0x1a7", 939 "SampleAfterValue": "100003", 940 "BriefDescription": "Counts all demand data reads that hit in the LLC", 941 "CounterHTOff": "0,1,2,3" 942 }, 943 { 944 "EventCode": "0xB7, 0xBB", 945 "MSRValue": "0x4003c0001", 946 "Counter": "0,1,2,3", 947 "UMask": "0x1", 948 "Offcore": "1", 949 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 950 "MSRIndex": "0x1a6,0x1a7", 951 "SampleAfterValue": "100003", 952 "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 953 "CounterHTOff": "0,1,2,3" 954 }, 955 { 956 "EventCode": "0xB7, 0xBB", 957 "MSRValue": "0x10003c0001", 958 "Counter": "0,1,2,3", 959 "UMask": "0x1", 960 "Offcore": "1", 961 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 962 "MSRIndex": "0x1a6,0x1a7", 963 "SampleAfterValue": "100003", 964 "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 965 "CounterHTOff": "0,1,2,3" 966 }, 967 { 968 "EventCode": "0xB7, 0xBB", 969 "MSRValue": "0x1003c0001", 970 "Counter": "0,1,2,3", 971 "UMask": "0x1", 972 "Offcore": "1", 973 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", 974 "MSRIndex": "0x1a6,0x1a7", 975 "SampleAfterValue": "100003", 976 "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 977 "CounterHTOff": "0,1,2,3" 978 }, 979 { 980 "EventCode": "0xB7, 0xBB", 981 "MSRValue": "0x3f803c0002", 982 "Counter": "0,1,2,3", 983 "UMask": "0x1", 984 "Offcore": "1", 985 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", 986 "MSRIndex": "0x1a6,0x1a7", 987 "SampleAfterValue": "100003", 988 "BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC", 989 "CounterHTOff": "0,1,2,3" 990 }, 991 { 992 "EventCode": "0xB7, 0xBB", 993 "MSRValue": "0x10003c0002", 994 "Counter": "0,1,2,3", 995 "UMask": "0x1", 996 "Offcore": "1", 997 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", 998 "MSRIndex": "0x1a6,0x1a7", 999 "SampleAfterValue": "100003", 1000 "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 1001 "CounterHTOff": "0,1,2,3" 1002 }, 1003 { 1004 "EventCode": "0xB7, 0xBB", 1005 "MSRValue": "0x1003c0002", 1006 "Counter": "0,1,2,3", 1007 "UMask": "0x1", 1008 "Offcore": "1", 1009 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED", 1010 "MSRIndex": "0x1a6,0x1a7", 1011 "SampleAfterValue": "100003", 1012 "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 1013 "CounterHTOff": "0,1,2,3" 1014 }, 1015 { 1016 "EventCode": "0xB7, 0xBB", 1017 "MSRValue": "0x18000", 1018 "Counter": "0,1,2,3", 1019 "UMask": "0x1", 1020 "Offcore": "1", 1021 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", 1022 "MSRIndex": "0x1a6,0x1a7", 1023 "SampleAfterValue": "100003", 1024 "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches", 1025 "CounterHTOff": "0,1,2,3" 1026 }, 1027 { 1028 "EventCode": "0xB7, 0xBB", 1029 "MSRValue": "0x10400", 1030 "Counter": "0,1,2,3", 1031 "UMask": "0x1", 1032 "Offcore": "1", 1033 "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", 1034 "MSRIndex": "0x1a6,0x1a7", 1035 "SampleAfterValue": "100003", 1036 "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address ", 1037 "CounterHTOff": "0,1,2,3" 1038 }, 1039 { 1040 "EventCode": "0xB7, 0xBB", 1041 "MSRValue": "0x10800", 1042 "Counter": "0,1,2,3", 1043 "UMask": "0x1", 1044 "Offcore": "1", 1045 "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", 1046 "MSRIndex": "0x1a6,0x1a7", 1047 "SampleAfterValue": "100003", 1048 "BriefDescription": "Counts non-temporal stores", 1049 "CounterHTOff": "0,1,2,3" 1050 }, 1051 { 1052 "EventCode": "0xB7, 0xBB", 1053 "MSRValue": "0x00010001", 1054 "Counter": "0,1,2,3", 1055 "UMask": "0x1", 1056 "Offcore": "1", 1057 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", 1058 "MSRIndex": "0x1a6,0x1a7", 1059 "SampleAfterValue": "100003", 1060 "BriefDescription": "Counts all demand data reads ", 1061 "CounterHTOff": "0,1,2,3" 1062 }, 1063 { 1064 "EventCode": "0xB7, 0xBB", 1065 "MSRValue": "0x00010002", 1066 "Counter": "0,1,2,3", 1067 "UMask": "0x1", 1068 "Offcore": "1", 1069 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", 1070 "MSRIndex": "0x1a6,0x1a7", 1071 "SampleAfterValue": "100003", 1072 "BriefDescription": "Counts all demand rfo's ", 1073 "CounterHTOff": "0,1,2,3" 1074 }, 1075 { 1076 "EventCode": "0xB7, 0xBB", 1077 "MSRValue": "0x00010004", 1078 "Counter": "0,1,2,3", 1079 "UMask": "0x1", 1080 "Offcore": "1", 1081 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", 1082 "MSRIndex": "0x1a6,0x1a7", 1083 "SampleAfterValue": "100003", 1084 "BriefDescription": "Counts all demand code reads", 1085 "CounterHTOff": "0,1,2,3" 1086 }, 1087 { 1088 "EventCode": "0xB7, 0xBB", 1089 "MSRValue": "0x000105B3", 1090 "Counter": "0,1,2,3", 1091 "UMask": "0x1", 1092 "Offcore": "1", 1093 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", 1094 "MSRIndex": "0x1a6,0x1a7", 1095 "SampleAfterValue": "100003", 1096 "BriefDescription": "Counts all demand & prefetch data reads", 1097 "CounterHTOff": "0,1,2,3" 1098 }, 1099 { 1100 "EventCode": "0xB7, 0xBB", 1101 "MSRValue": "0x00010122", 1102 "Counter": "0,1,2,3", 1103 "UMask": "0x1", 1104 "Offcore": "1", 1105 "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", 1106 "MSRIndex": "0x1a6,0x1a7", 1107 "SampleAfterValue": "100003", 1108 "BriefDescription": "Counts all demand & prefetch prefetch RFOs ", 1109 "CounterHTOff": "0,1,2,3" 1110 }, 1111 { 1112 "EventCode": "0xB7, 0xBB", 1113 "MSRValue": "0x000107F7", 1114 "Counter": "0,1,2,3", 1115 "UMask": "0x1", 1116 "Offcore": "1", 1117 "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", 1118 "MSRIndex": "0x1a6,0x1a7", 1119 "SampleAfterValue": "100003", 1120 "BriefDescription": "Counts all data/code/rfo references (demand & prefetch) ", 1121 "CounterHTOff": "0,1,2,3" 1122 } 1123]