1[ 2 { 3 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", 4 "CollectPEBSRecord": "2", 5 "Counter": "32", 6 "EventName": "INST_RETIRED.ANY", 7 "PEBS": "1", 8 "PEBScounters": "32", 9 "PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", 10 "SampleAfterValue": "2000003", 11 "UMask": "0x1" 12 }, 13 { 14 "BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution", 15 "CollectPEBSRecord": "2", 16 "Counter": "32", 17 "EventName": "INST_RETIRED.PREC_DIST", 18 "PEBS": "1", 19 "PEBScounters": "32", 20 "PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.", 21 "SampleAfterValue": "2000003", 22 "UMask": "0x1" 23 }, 24 { 25 "BriefDescription": "Core cycles when the thread is not in halt state", 26 "CollectPEBSRecord": "2", 27 "Counter": "33", 28 "EventName": "CPU_CLK_UNHALTED.THREAD", 29 "PEBScounters": "33", 30 "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.", 31 "SampleAfterValue": "2000003", 32 "Speculative": "1", 33 "UMask": "0x2" 34 }, 35 { 36 "BriefDescription": "Reference cycles when the core is not in halt state.", 37 "CollectPEBSRecord": "2", 38 "Counter": "34", 39 "EventName": "CPU_CLK_UNHALTED.REF_TSC", 40 "PEBScounters": "34", 41 "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", 42 "SampleAfterValue": "2000003", 43 "Speculative": "1", 44 "UMask": "0x3" 45 }, 46 { 47 "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", 48 "CollectPEBSRecord": "2", 49 "Counter": "0,1,2,3", 50 "EventCode": "0x03", 51 "EventName": "LD_BLOCKS.STORE_FORWARD", 52 "PEBScounters": "0,1,2,3", 53 "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", 54 "SampleAfterValue": "100003", 55 "Speculative": "1", 56 "UMask": "0x2" 57 }, 58 { 59 "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", 60 "CollectPEBSRecord": "2", 61 "Counter": "0,1,2,3", 62 "EventCode": "0x03", 63 "EventName": "LD_BLOCKS.NO_SR", 64 "PEBScounters": "0,1,2,3", 65 "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", 66 "SampleAfterValue": "100003", 67 "Speculative": "1", 68 "UMask": "0x8" 69 }, 70 { 71 "BriefDescription": "False dependencies due to partial compare on address.", 72 "CollectPEBSRecord": "2", 73 "Counter": "0,1,2,3", 74 "EventCode": "0x07", 75 "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", 76 "PEBScounters": "0,1,2,3", 77 "PublicDescription": "Counts the number of times a load got blocked due to false dependencies due to partial compare on address.", 78 "SampleAfterValue": "100003", 79 "Speculative": "1", 80 "UMask": "0x1" 81 }, 82 { 83 "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread", 84 "CollectPEBSRecord": "2", 85 "Counter": "0,1,2,3,4,5,6,7", 86 "EventCode": "0x0D", 87 "EventName": "INT_MISC.RECOVERY_CYCLES", 88 "PEBScounters": "0,1,2,3,4,5,6,7", 89 "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.", 90 "SampleAfterValue": "500009", 91 "Speculative": "1", 92 "UMask": "0x1" 93 }, 94 { 95 "BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", 96 "CollectPEBSRecord": "2", 97 "Counter": "0,1,2,3,4,5,6,7", 98 "CounterMask": "1", 99 "EventCode": "0x0D", 100 "EventName": "INT_MISC.ALL_RECOVERY_CYCLES", 101 "PEBScounters": "0,1,2,3,4,5,6,7", 102 "PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", 103 "SampleAfterValue": "2000003", 104 "Speculative": "1", 105 "UMask": "0x3" 106 }, 107 { 108 "BriefDescription": "TMA slots where uops got dropped", 109 "CollectPEBSRecord": "2", 110 "Counter": "0,1,2,3,4,5,6,7", 111 "EventCode": "0x0d", 112 "EventName": "INT_MISC.UOP_DROPPING", 113 "PEBScounters": "0,1,2,3,4,5,6,7", 114 "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons", 115 "SampleAfterValue": "1000003", 116 "Speculative": "1", 117 "UMask": "0x10" 118 }, 119 { 120 "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", 121 "CollectPEBSRecord": "2", 122 "Counter": "0,1,2,3,4,5,6,7", 123 "EventCode": "0x0d", 124 "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", 125 "PEBScounters": "0,1,2,3,4,5,6,7", 126 "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", 127 "SampleAfterValue": "500009", 128 "Speculative": "1", 129 "UMask": "0x80" 130 }, 131 { 132 "BriefDescription": "Uops that RAT issues to RS", 133 "CollectPEBSRecord": "2", 134 "Counter": "0,1,2,3,4,5,6,7", 135 "EventCode": "0x0e", 136 "EventName": "UOPS_ISSUED.ANY", 137 "PEBScounters": "0,1,2,3,4,5,6,7", 138 "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).", 139 "SampleAfterValue": "2000003", 140 "Speculative": "1", 141 "UMask": "0x1" 142 }, 143 { 144 "BriefDescription": "Cycles when RAT does not issue Uops to RS for the thread", 145 "CollectPEBSRecord": "2", 146 "Counter": "0,1,2,3,4,5,6,7", 147 "CounterMask": "1", 148 "EventCode": "0x0E", 149 "EventName": "UOPS_ISSUED.STALL_CYCLES", 150 "Invert": "1", 151 "PEBScounters": "0,1,2,3,4,5,6,7", 152 "PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", 153 "SampleAfterValue": "1000003", 154 "Speculative": "1", 155 "UMask": "0x1" 156 }, 157 { 158 "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.", 159 "CollectPEBSRecord": "2", 160 "Counter": "0,1,2,3,4,5,6,7", 161 "EventCode": "0x0e", 162 "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", 163 "PEBScounters": "0,1,2,3,4,5,6,7", 164 "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.", 165 "SampleAfterValue": "100003", 166 "Speculative": "1", 167 "UMask": "0x2" 168 }, 169 { 170 "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.", 171 "CollectPEBSRecord": "2", 172 "Counter": "0,1,2,3,4,5,6,7", 173 "CounterMask": "1", 174 "EventCode": "0x14", 175 "EventName": "ARITH.DIVIDER_ACTIVE", 176 "PEBScounters": "0,1,2,3,4,5,6,7", 177 "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.", 178 "SampleAfterValue": "1000003", 179 "Speculative": "1", 180 "UMask": "0x9" 181 }, 182 { 183 "BriefDescription": "Thread cycles when thread is not in halt state", 184 "CollectPEBSRecord": "2", 185 "Counter": "0,1,2,3,4,5,6,7", 186 "EventCode": "0x3C", 187 "EventName": "CPU_CLK_UNHALTED.THREAD_P", 188 "PEBScounters": "0,1,2,3,4,5,6,7", 189 "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", 190 "SampleAfterValue": "2000003", 191 "Speculative": "1" 192 }, 193 { 194 "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", 195 "CollectPEBSRecord": "2", 196 "Counter": "0,1,2,3,4,5,6,7", 197 "EventCode": "0x3C", 198 "EventName": "CPU_CLK_UNHALTED.REF_XCLK", 199 "PEBScounters": "0,1,2,3,4,5,6,7", 200 "PublicDescription": "Counts core crystal clock cycles when the thread is unhalted.", 201 "SampleAfterValue": "25003", 202 "Speculative": "1", 203 "UMask": "0x1" 204 }, 205 { 206 "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", 207 "CollectPEBSRecord": "2", 208 "Counter": "0,1,2,3,4,5,6,7", 209 "EventCode": "0x3C", 210 "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", 211 "PEBScounters": "0,1,2,3,4,5,6,7", 212 "PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.", 213 "SampleAfterValue": "25003", 214 "Speculative": "1", 215 "UMask": "0x2" 216 }, 217 { 218 "BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.", 219 "CollectPEBSRecord": "2", 220 "Counter": "0,1,2,3,4,5,6,7", 221 "EventCode": "0x3c", 222 "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", 223 "PEBScounters": "0,1,2,3,4,5,6,7", 224 "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", 225 "SampleAfterValue": "2000003", 226 "Speculative": "1", 227 "UMask": "0x8" 228 }, 229 { 230 "BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.", 231 "CollectPEBSRecord": "2", 232 "Counter": "0,1,2,3", 233 "EventCode": "0x4c", 234 "EventName": "LOAD_HIT_PREFETCH.SWPF", 235 "PEBScounters": "0,1,2,3", 236 "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.", 237 "SampleAfterValue": "100003", 238 "Speculative": "1", 239 "UMask": "0x1" 240 }, 241 { 242 "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", 243 "CollectPEBSRecord": "2", 244 "Counter": "0,1,2,3,4,5,6,7", 245 "EventCode": "0x5e", 246 "EventName": "RS_EVENTS.EMPTY_CYCLES", 247 "PEBScounters": "0,1,2,3,4,5,6,7", 248 "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)", 249 "SampleAfterValue": "1000003", 250 "Speculative": "1", 251 "UMask": "0x1" 252 }, 253 { 254 "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.", 255 "CollectPEBSRecord": "2", 256 "Counter": "0,1,2,3,4,5,6,7", 257 "CounterMask": "1", 258 "EdgeDetect": "1", 259 "EventCode": "0x5E", 260 "EventName": "RS_EVENTS.EMPTY_END", 261 "Invert": "1", 262 "PEBScounters": "0,1,2,3,4,5,6,7", 263 "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)", 264 "SampleAfterValue": "100003", 265 "Speculative": "1", 266 "UMask": "0x1" 267 }, 268 { 269 "BriefDescription": "Stalls caused by changing prefix length of the instruction.", 270 "CollectPEBSRecord": "2", 271 "Counter": "0,1,2,3", 272 "EventCode": "0x87", 273 "EventName": "ILD_STALL.LCP", 274 "PEBScounters": "0,1,2,3", 275 "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", 276 "SampleAfterValue": "500009", 277 "Speculative": "1", 278 "UMask": "0x1" 279 }, 280 { 281 "BriefDescription": "Number of uops executed on port 0", 282 "CollectPEBSRecord": "2", 283 "Counter": "0,1,2,3,4,5,6,7", 284 "EventCode": "0xa1", 285 "EventName": "UOPS_DISPATCHED.PORT_0", 286 "PEBScounters": "0,1,2,3,4,5,6,7", 287 "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.", 288 "SampleAfterValue": "2000003", 289 "Speculative": "1", 290 "UMask": "0x1" 291 }, 292 { 293 "BriefDescription": "Number of uops executed on port 1", 294 "CollectPEBSRecord": "2", 295 "Counter": "0,1,2,3,4,5,6,7", 296 "EventCode": "0xa1", 297 "EventName": "UOPS_DISPATCHED.PORT_1", 298 "PEBScounters": "0,1,2,3,4,5,6,7", 299 "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.", 300 "SampleAfterValue": "2000003", 301 "Speculative": "1", 302 "UMask": "0x2" 303 }, 304 { 305 "BriefDescription": "Number of uops executed on port 2 and 3", 306 "CollectPEBSRecord": "2", 307 "Counter": "0,1,2,3,4,5,6,7", 308 "EventCode": "0xa1", 309 "EventName": "UOPS_DISPATCHED.PORT_2_3", 310 "PEBScounters": "0,1,2,3,4,5,6,7", 311 "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3.", 312 "SampleAfterValue": "2000003", 313 "Speculative": "1", 314 "UMask": "0x4" 315 }, 316 { 317 "BriefDescription": "Number of uops executed on port 4 and 9", 318 "CollectPEBSRecord": "2", 319 "Counter": "0,1,2,3,4,5,6,7", 320 "EventCode": "0xa1", 321 "EventName": "UOPS_DISPATCHED.PORT_4_9", 322 "PEBScounters": "0,1,2,3,4,5,6,7", 323 "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9.", 324 "SampleAfterValue": "2000003", 325 "Speculative": "1", 326 "UMask": "0x10" 327 }, 328 { 329 "BriefDescription": "Number of uops executed on port 5", 330 "CollectPEBSRecord": "2", 331 "Counter": "0,1,2,3,4,5,6,7", 332 "EventCode": "0xa1", 333 "EventName": "UOPS_DISPATCHED.PORT_5", 334 "PEBScounters": "0,1,2,3,4,5,6,7", 335 "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.", 336 "SampleAfterValue": "2000003", 337 "Speculative": "1", 338 "UMask": "0x20" 339 }, 340 { 341 "BriefDescription": "Number of uops executed on port 6", 342 "CollectPEBSRecord": "2", 343 "Counter": "0,1,2,3,4,5,6,7", 344 "EventCode": "0xa1", 345 "EventName": "UOPS_DISPATCHED.PORT_6", 346 "PEBScounters": "0,1,2,3,4,5,6,7", 347 "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.", 348 "SampleAfterValue": "2000003", 349 "Speculative": "1", 350 "UMask": "0x40" 351 }, 352 { 353 "BriefDescription": "Number of uops executed on port 7 and 8", 354 "CollectPEBSRecord": "2", 355 "Counter": "0,1,2,3,4,5,6,7", 356 "EventCode": "0xa1", 357 "EventName": "UOPS_DISPATCHED.PORT_7_8", 358 "PEBScounters": "0,1,2,3,4,5,6,7", 359 "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8.", 360 "SampleAfterValue": "2000003", 361 "Speculative": "1", 362 "UMask": "0x80" 363 }, 364 { 365 "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", 366 "CollectPEBSRecord": "2", 367 "Counter": "0,1,2,3,4,5,6,7", 368 "EventCode": "0xa2", 369 "EventName": "RESOURCE_STALLS.SCOREBOARD", 370 "PEBScounters": "0,1,2,3,4,5,6,7", 371 "SampleAfterValue": "100003", 372 "Speculative": "1", 373 "UMask": "0x2" 374 }, 375 { 376 "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", 377 "CollectPEBSRecord": "2", 378 "Counter": "0,1,2,3,4,5,6,7", 379 "EventCode": "0xa2", 380 "EventName": "RESOURCE_STALLS.SB", 381 "PEBScounters": "0,1,2,3,4,5,6,7", 382 "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.", 383 "SampleAfterValue": "100003", 384 "Speculative": "1", 385 "UMask": "0x8" 386 }, 387 { 388 "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", 389 "CollectPEBSRecord": "2", 390 "Counter": "0,1,2,3", 391 "CounterMask": "1", 392 "EventCode": "0xA3", 393 "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", 394 "PEBScounters": "0,1,2,3", 395 "SampleAfterValue": "1000003", 396 "Speculative": "1", 397 "UMask": "0x1" 398 }, 399 { 400 "BriefDescription": "Total execution stalls.", 401 "CollectPEBSRecord": "2", 402 "Counter": "0,1,2,3,4,5,6,7", 403 "CounterMask": "4", 404 "EventCode": "0xa3", 405 "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", 406 "PEBScounters": "0,1,2,3,4,5,6,7", 407 "SampleAfterValue": "1000003", 408 "Speculative": "1", 409 "UMask": "0x4" 410 }, 411 { 412 "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", 413 "CollectPEBSRecord": "2", 414 "Counter": "0,1,2,3", 415 "CounterMask": "5", 416 "EventCode": "0xa3", 417 "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", 418 "PEBScounters": "0,1,2,3", 419 "SampleAfterValue": "1000003", 420 "Speculative": "1", 421 "UMask": "0x5" 422 }, 423 { 424 "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", 425 "CollectPEBSRecord": "2", 426 "Counter": "0,1,2,3", 427 "CounterMask": "8", 428 "EventCode": "0xA3", 429 "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", 430 "PEBScounters": "0,1,2,3", 431 "SampleAfterValue": "1000003", 432 "Speculative": "1", 433 "UMask": "0x8" 434 }, 435 { 436 "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", 437 "CollectPEBSRecord": "2", 438 "Counter": "0,1,2,3", 439 "CounterMask": "12", 440 "EventCode": "0xA3", 441 "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", 442 "PEBScounters": "0,1,2,3", 443 "SampleAfterValue": "1000003", 444 "Speculative": "1", 445 "UMask": "0xc" 446 }, 447 { 448 "BriefDescription": "Cycles while memory subsystem has an outstanding load.", 449 "CollectPEBSRecord": "2", 450 "Counter": "0,1,2,3,4,5,6,7", 451 "CounterMask": "16", 452 "EventCode": "0xA3", 453 "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", 454 "PEBScounters": "0,1,2,3,4,5,6,7", 455 "SampleAfterValue": "1000003", 456 "Speculative": "1", 457 "UMask": "0x10" 458 }, 459 { 460 "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", 461 "CollectPEBSRecord": "2", 462 "Counter": "0,1,2,3,4,5,6,7", 463 "CounterMask": "20", 464 "EventCode": "0xa3", 465 "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", 466 "PEBScounters": "0,1,2,3,4,5,6,7", 467 "SampleAfterValue": "1000003", 468 "Speculative": "1", 469 "UMask": "0x14" 470 }, 471 { 472 "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.", 473 "CollectPEBSRecord": "2", 474 "Counter": "0,1,2,3,4,5,6,7", 475 "EventCode": "0xa6", 476 "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", 477 "PEBScounters": "0,1,2,3,4,5,6,7", 478 "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.", 479 "SampleAfterValue": "2000003", 480 "Speculative": "1", 481 "UMask": "0x2" 482 }, 483 { 484 "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.", 485 "CollectPEBSRecord": "2", 486 "Counter": "0,1,2,3,4,5,6,7", 487 "EventCode": "0xa6", 488 "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", 489 "PEBScounters": "0,1,2,3,4,5,6,7", 490 "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.", 491 "SampleAfterValue": "2000003", 492 "Speculative": "1", 493 "UMask": "0x4" 494 }, 495 { 496 "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.", 497 "CollectPEBSRecord": "2", 498 "Counter": "0,1,2,3,4,5,6,7", 499 "EventCode": "0xa6", 500 "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", 501 "PEBScounters": "0,1,2,3,4,5,6,7", 502 "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.", 503 "SampleAfterValue": "2000003", 504 "Speculative": "1", 505 "UMask": "0x8" 506 }, 507 { 508 "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.", 509 "CollectPEBSRecord": "2", 510 "Counter": "0,1,2,3,4,5,6,7", 511 "EventCode": "0xa6", 512 "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", 513 "PEBScounters": "0,1,2,3,4,5,6,7", 514 "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.", 515 "SampleAfterValue": "2000003", 516 "Speculative": "1", 517 "UMask": "0x10" 518 }, 519 { 520 "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.", 521 "CollectPEBSRecord": "2", 522 "Counter": "0,1,2,3,4,5,6,7", 523 "CounterMask": "2", 524 "EventCode": "0xA6", 525 "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", 526 "PEBScounters": "0,1,2,3,4,5,6,7", 527 "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.", 528 "SampleAfterValue": "1000003", 529 "Speculative": "1", 530 "UMask": "0x40" 531 }, 532 { 533 "BriefDescription": "Number of Uops delivered by the LSD.", 534 "CollectPEBSRecord": "2", 535 "Counter": "0,1,2,3", 536 "EventCode": "0xa8", 537 "EventName": "LSD.UOPS", 538 "PEBScounters": "0,1,2,3", 539 "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).", 540 "SampleAfterValue": "2000003", 541 "Speculative": "1", 542 "UMask": "0x1" 543 }, 544 { 545 "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", 546 "CollectPEBSRecord": "2", 547 "Counter": "0,1,2,3", 548 "CounterMask": "1", 549 "EventCode": "0xA8", 550 "EventName": "LSD.CYCLES_ACTIVE", 551 "PEBScounters": "0,1,2,3", 552 "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).", 553 "SampleAfterValue": "2000003", 554 "Speculative": "1", 555 "UMask": "0x1" 556 }, 557 { 558 "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.", 559 "CollectPEBSRecord": "2", 560 "Counter": "0,1,2,3", 561 "CounterMask": "5", 562 "EventCode": "0xa8", 563 "EventName": "LSD.CYCLES_OK", 564 "PEBScounters": "0,1,2,3", 565 "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).", 566 "SampleAfterValue": "2000003", 567 "Speculative": "1", 568 "UMask": "0x1" 569 }, 570 { 571 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", 572 "CollectPEBSRecord": "2", 573 "Counter": "0,1,2,3,4,5,6,7", 574 "EventCode": "0xb1", 575 "EventName": "UOPS_EXECUTED.THREAD", 576 "PEBScounters": "0,1,2,3,4,5,6,7", 577 "SampleAfterValue": "2000003", 578 "Speculative": "1", 579 "UMask": "0x1" 580 }, 581 { 582 "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", 583 "CollectPEBSRecord": "2", 584 "Counter": "0,1,2,3,4,5,6,7", 585 "CounterMask": "1", 586 "EventCode": "0xB1", 587 "EventName": "UOPS_EXECUTED.STALL_CYCLES", 588 "Invert": "1", 589 "PEBScounters": "0,1,2,3,4,5,6,7", 590 "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", 591 "SampleAfterValue": "2000003", 592 "Speculative": "1", 593 "UMask": "0x1" 594 }, 595 { 596 "BriefDescription": "Cycles where at least 1 uop was executed per-thread", 597 "CollectPEBSRecord": "2", 598 "Counter": "0,1,2,3,4,5,6,7", 599 "CounterMask": "1", 600 "EventCode": "0xb1", 601 "EventName": "UOPS_EXECUTED.CYCLES_GE_1", 602 "PEBScounters": "0,1,2,3,4,5,6,7", 603 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", 604 "SampleAfterValue": "2000003", 605 "Speculative": "1", 606 "UMask": "0x1" 607 }, 608 { 609 "BriefDescription": "Cycles where at least 2 uops were executed per-thread", 610 "CollectPEBSRecord": "2", 611 "Counter": "0,1,2,3,4,5,6,7", 612 "CounterMask": "2", 613 "EventCode": "0xb1", 614 "EventName": "UOPS_EXECUTED.CYCLES_GE_2", 615 "PEBScounters": "0,1,2,3,4,5,6,7", 616 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", 617 "SampleAfterValue": "2000003", 618 "Speculative": "1", 619 "UMask": "0x1" 620 }, 621 { 622 "BriefDescription": "Cycles where at least 3 uops were executed per-thread", 623 "CollectPEBSRecord": "2", 624 "Counter": "0,1,2,3,4,5,6,7", 625 "CounterMask": "3", 626 "EventCode": "0xb1", 627 "EventName": "UOPS_EXECUTED.CYCLES_GE_3", 628 "PEBScounters": "0,1,2,3,4,5,6,7", 629 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", 630 "SampleAfterValue": "2000003", 631 "Speculative": "1", 632 "UMask": "0x1" 633 }, 634 { 635 "BriefDescription": "Cycles where at least 4 uops were executed per-thread", 636 "CollectPEBSRecord": "2", 637 "Counter": "0,1,2,3,4,5,6,7", 638 "CounterMask": "4", 639 "EventCode": "0xb1", 640 "EventName": "UOPS_EXECUTED.CYCLES_GE_4", 641 "PEBScounters": "0,1,2,3,4,5,6,7", 642 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.", 643 "SampleAfterValue": "2000003", 644 "Speculative": "1", 645 "UMask": "0x1" 646 }, 647 { 648 "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", 649 "CollectPEBSRecord": "2", 650 "Counter": "0,1,2,3,4,5,6,7", 651 "CounterMask": "1", 652 "EventCode": "0xB1", 653 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", 654 "PEBScounters": "0,1,2,3,4,5,6,7", 655 "PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.", 656 "SampleAfterValue": "2000003", 657 "Speculative": "1", 658 "UMask": "0x2" 659 }, 660 { 661 "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", 662 "CollectPEBSRecord": "2", 663 "Counter": "0,1,2,3,4,5,6,7", 664 "CounterMask": "2", 665 "EventCode": "0xB1", 666 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", 667 "PEBScounters": "0,1,2,3,4,5,6,7", 668 "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.", 669 "SampleAfterValue": "2000003", 670 "Speculative": "1", 671 "UMask": "0x2" 672 }, 673 { 674 "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", 675 "CollectPEBSRecord": "2", 676 "Counter": "0,1,2,3,4,5,6,7", 677 "CounterMask": "3", 678 "EventCode": "0xB1", 679 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", 680 "PEBScounters": "0,1,2,3,4,5,6,7", 681 "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.", 682 "SampleAfterValue": "2000003", 683 "Speculative": "1", 684 "UMask": "0x2" 685 }, 686 { 687 "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", 688 "CollectPEBSRecord": "2", 689 "Counter": "0,1,2,3,4,5,6,7", 690 "CounterMask": "4", 691 "EventCode": "0xB1", 692 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", 693 "PEBScounters": "0,1,2,3,4,5,6,7", 694 "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.", 695 "SampleAfterValue": "2000003", 696 "Speculative": "1", 697 "UMask": "0x2" 698 }, 699 { 700 "BriefDescription": "Counts the number of x87 uops dispatched.", 701 "CollectPEBSRecord": "2", 702 "Counter": "0,1,2,3,4,5,6,7", 703 "EventCode": "0xB1", 704 "EventName": "UOPS_EXECUTED.X87", 705 "PEBScounters": "0,1,2,3,4,5,6,7", 706 "PublicDescription": "Counts the number of x87 uops executed.", 707 "SampleAfterValue": "2000003", 708 "Speculative": "1", 709 "UMask": "0x10" 710 }, 711 { 712 "BriefDescription": "Number of instructions retired. General Counter - architectural event", 713 "CollectPEBSRecord": "2", 714 "Counter": "0,1,2,3,4,5,6,7", 715 "EventCode": "0xc0", 716 "EventName": "INST_RETIRED.ANY_P", 717 "PEBS": "1", 718 "PEBScounters": "0,1,2,3,4,5,6,7", 719 "PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", 720 "SampleAfterValue": "2000003" 721 }, 722 { 723 "BriefDescription": "Cycles with less than 10 actually retired uops.", 724 "CollectPEBSRecord": "2", 725 "Counter": "0,1,2,3,4,5,6,7", 726 "CounterMask": "10", 727 "EventCode": "0xc2", 728 "EventName": "UOPS_RETIRED.TOTAL_CYCLES", 729 "Invert": "1", 730 "PEBScounters": "0,1,2,3,4,5,6,7", 731 "PublicDescription": "Counts the number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.", 732 "SampleAfterValue": "1000003", 733 "UMask": "0x2" 734 }, 735 { 736 "BriefDescription": "Retirement slots used.", 737 "CollectPEBSRecord": "2", 738 "Counter": "0,1,2,3,4,5,6,7", 739 "EventCode": "0xc2", 740 "EventName": "UOPS_RETIRED.SLOTS", 741 "PEBScounters": "0,1,2,3,4,5,6,7", 742 "PublicDescription": "Counts the retirement slots used each cycle.", 743 "SampleAfterValue": "2000003", 744 "UMask": "0x2" 745 }, 746 { 747 "BriefDescription": "Number of machine clears (nukes) of any type.", 748 "CollectPEBSRecord": "2", 749 "Counter": "0,1,2,3,4,5,6,7", 750 "CounterMask": "1", 751 "EdgeDetect": "1", 752 "EventCode": "0xc3", 753 "EventName": "MACHINE_CLEARS.COUNT", 754 "PEBScounters": "0,1,2,3,4,5,6,7", 755 "PublicDescription": "Counts the number of machine clears (nukes) of any type.", 756 "SampleAfterValue": "100003", 757 "Speculative": "1", 758 "UMask": "0x1" 759 }, 760 { 761 "BriefDescription": "Self-modifying code (SMC) detected.", 762 "CollectPEBSRecord": "2", 763 "Counter": "0,1,2,3,4,5,6,7", 764 "EventCode": "0xc3", 765 "EventName": "MACHINE_CLEARS.SMC", 766 "PEBScounters": "0,1,2,3,4,5,6,7", 767 "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.", 768 "SampleAfterValue": "100003", 769 "Speculative": "1", 770 "UMask": "0x4" 771 }, 772 { 773 "BriefDescription": "All branch instructions retired.", 774 "CollectPEBSRecord": "2", 775 "Counter": "0,1,2,3,4,5,6,7", 776 "EventCode": "0xc4", 777 "EventName": "BR_INST_RETIRED.ALL_BRANCHES", 778 "PEBS": "1", 779 "PEBScounters": "0,1,2,3,4,5,6,7", 780 "PublicDescription": "Counts all branch instructions retired.", 781 "SampleAfterValue": "400009" 782 }, 783 { 784 "BriefDescription": "Taken conditional branch instructions retired.", 785 "CollectPEBSRecord": "2", 786 "Counter": "0,1,2,3,4,5,6,7", 787 "EventCode": "0xc4", 788 "EventName": "BR_INST_RETIRED.COND_TAKEN", 789 "PEBS": "1", 790 "PEBScounters": "0,1,2,3,4,5,6,7", 791 "PublicDescription": "Counts taken conditional branch instructions retired.", 792 "SampleAfterValue": "400009", 793 "UMask": "0x1" 794 }, 795 { 796 "BriefDescription": "Direct and indirect near call instructions retired.", 797 "CollectPEBSRecord": "2", 798 "Counter": "0,1,2,3,4,5,6,7", 799 "EventCode": "0xc4", 800 "EventName": "BR_INST_RETIRED.NEAR_CALL", 801 "PEBS": "1", 802 "PEBScounters": "0,1,2,3,4,5,6,7", 803 "PublicDescription": "Counts both direct and indirect near call instructions retired.", 804 "SampleAfterValue": "100007", 805 "UMask": "0x2" 806 }, 807 { 808 "BriefDescription": "Return instructions retired.", 809 "CollectPEBSRecord": "2", 810 "Counter": "0,1,2,3,4,5,6,7", 811 "EventCode": "0xc4", 812 "EventName": "BR_INST_RETIRED.NEAR_RETURN", 813 "PEBS": "1", 814 "PEBScounters": "0,1,2,3,4,5,6,7", 815 "PublicDescription": "Counts return instructions retired.", 816 "SampleAfterValue": "100007", 817 "UMask": "0x8" 818 }, 819 { 820 "BriefDescription": "Not taken branch instructions retired.", 821 "CollectPEBSRecord": "2", 822 "Counter": "0,1,2,3,4,5,6,7", 823 "EventCode": "0xc4", 824 "EventName": "BR_INST_RETIRED.COND_NTAKEN", 825 "PEBS": "1", 826 "PEBScounters": "0,1,2,3,4,5,6,7", 827 "PublicDescription": "Counts not taken branch instructions retired.", 828 "SampleAfterValue": "400009", 829 "UMask": "0x10" 830 }, 831 { 832 "BriefDescription": "Conditional branch instructions retired.", 833 "CollectPEBSRecord": "2", 834 "Counter": "0,1,2,3,4,5,6,7", 835 "EventCode": "0xc4", 836 "EventName": "BR_INST_RETIRED.COND", 837 "PEBS": "1", 838 "PEBScounters": "0,1,2,3,4,5,6,7", 839 "PublicDescription": "Counts conditional branch instructions retired.", 840 "SampleAfterValue": "400009", 841 "UMask": "0x11" 842 }, 843 { 844 "BriefDescription": "Taken branch instructions retired.", 845 "CollectPEBSRecord": "2", 846 "Counter": "0,1,2,3,4,5,6,7", 847 "EventCode": "0xc4", 848 "EventName": "BR_INST_RETIRED.NEAR_TAKEN", 849 "PEBS": "1", 850 "PEBScounters": "0,1,2,3,4,5,6,7", 851 "PublicDescription": "Counts taken branch instructions retired.", 852 "SampleAfterValue": "400009", 853 "UMask": "0x20" 854 }, 855 { 856 "BriefDescription": "Far branch instructions retired.", 857 "CollectPEBSRecord": "2", 858 "Counter": "0,1,2,3,4,5,6,7", 859 "EventCode": "0xc4", 860 "EventName": "BR_INST_RETIRED.FAR_BRANCH", 861 "PEBS": "1", 862 "PEBScounters": "0,1,2,3,4,5,6,7", 863 "PublicDescription": "Counts far branch instructions retired.", 864 "SampleAfterValue": "100007", 865 "UMask": "0x40" 866 }, 867 { 868 "BriefDescription": "All indirect branch instructions retired (excluding RETs. TSX aborts are considered indirect branch).", 869 "CollectPEBSRecord": "2", 870 "Counter": "0,1,2,3,4,5,6,7", 871 "EventCode": "0xc4", 872 "EventName": "BR_INST_RETIRED.INDIRECT", 873 "PEBS": "1", 874 "PEBScounters": "0,1,2,3,4,5,6,7", 875 "PublicDescription": "Counts all indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", 876 "SampleAfterValue": "100003", 877 "UMask": "0x80" 878 }, 879 { 880 "BriefDescription": "All mispredicted branch instructions retired.", 881 "CollectPEBSRecord": "2", 882 "Counter": "0,1,2,3,4,5,6,7", 883 "EventCode": "0xc5", 884 "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", 885 "PEBS": "1", 886 "PEBScounters": "0,1,2,3,4,5,6,7", 887 "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", 888 "SampleAfterValue": "50021" 889 }, 890 { 891 "BriefDescription": "number of branch instructions retired that were mispredicted and taken. Non PEBS", 892 "CollectPEBSRecord": "2", 893 "Counter": "0,1,2,3,4,5,6,7", 894 "EventCode": "0xc5", 895 "EventName": "BR_MISP_RETIRED.COND_TAKEN", 896 "PEBS": "1", 897 "PEBScounters": "0,1,2,3,4,5,6,7", 898 "PublicDescription": "Counts taken conditional mispredicted branch instructions retired.", 899 "SampleAfterValue": "50021", 900 "UMask": "0x1" 901 }, 902 { 903 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", 904 "CollectPEBSRecord": "2", 905 "Counter": "0,1,2,3,4,5,6,7", 906 "EventCode": "0xc5", 907 "EventName": "BR_MISP_RETIRED.COND_NTAKEN", 908 "PEBS": "1", 909 "PEBScounters": "0,1,2,3,4,5,6,7", 910 "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.", 911 "SampleAfterValue": "50021", 912 "UMask": "0x10" 913 }, 914 { 915 "BriefDescription": "Mispredicted conditional branch instructions retired.", 916 "CollectPEBSRecord": "2", 917 "Counter": "0,1,2,3,4,5,6,7", 918 "EventCode": "0xc5", 919 "EventName": "BR_MISP_RETIRED.COND", 920 "PEBS": "1", 921 "PEBScounters": "0,1,2,3,4,5,6,7", 922 "PublicDescription": "Counts mispredicted conditional branch instructions retired.", 923 "SampleAfterValue": "50021", 924 "UMask": "0x11" 925 }, 926 { 927 "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", 928 "CollectPEBSRecord": "2", 929 "Counter": "0,1,2,3,4,5,6,7", 930 "EventCode": "0xc5", 931 "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", 932 "PEBS": "1", 933 "PEBScounters": "0,1,2,3,4,5,6,7", 934 "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.", 935 "SampleAfterValue": "50021", 936 "UMask": "0x20" 937 }, 938 { 939 "BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", 940 "CollectPEBSRecord": "2", 941 "Counter": "0,1,2,3,4,5,6,7", 942 "EventCode": "0xc5", 943 "EventName": "BR_MISP_RETIRED.INDIRECT", 944 "PEBS": "1", 945 "PEBScounters": "0,1,2,3,4,5,6,7", 946 "PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", 947 "SampleAfterValue": "50021", 948 "UMask": "0x80" 949 }, 950 { 951 "BriefDescription": "Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.", 952 "CollectPEBSRecord": "2", 953 "Counter": "0,1,2,3,4,5,6,7", 954 "EventCode": "0xcc", 955 "EventName": "MISC_RETIRED.PAUSE_INST", 956 "PublicDescription": "Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.", 957 "SampleAfterValue": "100003", 958 "UMask": "0x40" 959 }, 960 { 961 "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.", 962 "CollectPEBSRecord": "2", 963 "Counter": "0,1,2,3,4,5,6,7", 964 "EventCode": "0xec", 965 "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", 966 "PEBScounters": "0,1,2,3,4,5,6,7", 967 "PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", 968 "SampleAfterValue": "2000003", 969 "Speculative": "1", 970 "UMask": "0x2" 971 } 972]