1[ 2 { 3 "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", 4 "CollectPEBSRecord": "2", 5 "Counter": "35", 6 "EventName": "TOPDOWN.SLOTS", 7 "PEBScounters": "35", 8 "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", 9 "SampleAfterValue": "10000003", 10 "Speculative": "1", 11 "UMask": "0x4" 12 }, 13 { 14 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", 15 "CollectPEBSRecord": "2", 16 "Counter": "0,1,2,3", 17 "EventCode": "0x28", 18 "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", 19 "PEBScounters": "0,1,2,3", 20 "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", 21 "SampleAfterValue": "200003", 22 "Speculative": "1", 23 "UMask": "0x7" 24 }, 25 { 26 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", 27 "CollectPEBSRecord": "2", 28 "Counter": "0,1,2,3", 29 "EventCode": "0x28", 30 "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", 31 "PEBScounters": "0,1,2,3", 32 "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", 33 "SampleAfterValue": "200003", 34 "Speculative": "1", 35 "UMask": "0x18" 36 }, 37 { 38 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", 39 "CollectPEBSRecord": "2", 40 "Counter": "0,1,2,3", 41 "EventCode": "0x28", 42 "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", 43 "PEBScounters": "0,1,2,3", 44 "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.", 45 "SampleAfterValue": "200003", 46 "Speculative": "1", 47 "UMask": "0x20" 48 }, 49 { 50 "BriefDescription": "Number of PREFETCHNTA instructions executed.", 51 "CollectPEBSRecord": "2", 52 "Counter": "0,1,2,3", 53 "EventCode": "0x32", 54 "EventName": "SW_PREFETCH_ACCESS.NTA", 55 "PEBScounters": "0,1,2,3", 56 "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", 57 "SampleAfterValue": "100003", 58 "Speculative": "1", 59 "UMask": "0x1" 60 }, 61 { 62 "BriefDescription": "Number of PREFETCHT0 instructions executed.", 63 "CollectPEBSRecord": "2", 64 "Counter": "0,1,2,3", 65 "EventCode": "0x32", 66 "EventName": "SW_PREFETCH_ACCESS.T0", 67 "PEBScounters": "0,1,2,3", 68 "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", 69 "SampleAfterValue": "100003", 70 "Speculative": "1", 71 "UMask": "0x2" 72 }, 73 { 74 "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", 75 "CollectPEBSRecord": "2", 76 "Counter": "0,1,2,3", 77 "EventCode": "0x32", 78 "EventName": "SW_PREFETCH_ACCESS.T1_T2", 79 "PEBScounters": "0,1,2,3", 80 "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", 81 "SampleAfterValue": "100003", 82 "Speculative": "1", 83 "UMask": "0x4" 84 }, 85 { 86 "BriefDescription": "Number of PREFETCHW instructions executed.", 87 "CollectPEBSRecord": "2", 88 "Counter": "0,1,2,3", 89 "EventCode": "0x32", 90 "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", 91 "PEBScounters": "0,1,2,3", 92 "PublicDescription": "Counts the number of PREFETCHW instructions executed.", 93 "SampleAfterValue": "100003", 94 "Speculative": "1", 95 "UMask": "0x8" 96 }, 97 { 98 "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", 99 "CollectPEBSRecord": "2", 100 "Counter": "0,1,2,3,4,5,6,7", 101 "EventCode": "0xa4", 102 "EventName": "TOPDOWN.SLOTS_P", 103 "PEBScounters": "0,1,2,3,4,5,6,7", 104 "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", 105 "SampleAfterValue": "10000003", 106 "Speculative": "1", 107 "UMask": "0x1" 108 }, 109 { 110 "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", 111 "CollectPEBSRecord": "2", 112 "Counter": "0,1,2,3,4,5,6,7", 113 "EventCode": "0xa4", 114 "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", 115 "PEBScounters": "0,1,2,3,4,5,6,7", 116 "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", 117 "SampleAfterValue": "10000003", 118 "Speculative": "1", 119 "UMask": "0x2" 120 }, 121 { 122 "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.", 123 "CollectPEBSRecord": "2", 124 "Counter": "0,1,2,3,4,5,6,7", 125 "EventCode": "0xc1", 126 "EventName": "ASSISTS.ANY", 127 "PEBScounters": "0,1,2,3,4,5,6,7", 128 "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.", 129 "SampleAfterValue": "100003", 130 "Speculative": "1", 131 "UMask": "0x7" 132 }, 133 { 134 "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", 135 "Counter": "0,1,2,3", 136 "EventCode": "0xB7, 0xBB", 137 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", 138 "MSRIndex": "0x1a6,0x1a7", 139 "MSRValue": "0x10003C0001", 140 "Offcore": "1", 141 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 142 "SampleAfterValue": "100003", 143 "UMask": "0x1" 144 }, 145 { 146 "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches which forwarded the unmodified data to the requesting core.", 147 "Counter": "0,1,2,3", 148 "EventCode": "0xB7, 0xBB", 149 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 150 "MSRIndex": "0x1a6,0x1a7", 151 "MSRValue": "0x8003C0001", 152 "Offcore": "1", 153 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 154 "SampleAfterValue": "100003", 155 "UMask": "0x1" 156 }, 157 { 158 "BriefDescription": "Counts writes that generate a demand reads for ownership (RFO) request and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", 159 "Counter": "0,1,2,3", 160 "EventCode": "0xB7, 0xBB", 161 "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", 162 "MSRIndex": "0x1a6,0x1a7", 163 "MSRValue": "0x10003C0002", 164 "Offcore": "1", 165 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 166 "SampleAfterValue": "100003", 167 "UMask": "0x1" 168 }, 169 { 170 "BriefDescription": "Counts streaming stores that have any type of response.", 171 "Counter": "0,1,2,3", 172 "EventCode": "0xB7, 0xBB", 173 "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", 174 "MSRIndex": "0x1a6,0x1a7", 175 "MSRValue": "0x10800", 176 "Offcore": "1", 177 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 178 "SampleAfterValue": "100003", 179 "UMask": "0x1" 180 } 181]