1[
2    {
3        "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
4        "CollectPEBSRecord": "2",
5        "Counter": "0,1,2,3",
6        "EventCode": "0x54",
7        "EventName": "TX_MEM.ABORT_CONFLICT",
8        "PEBScounters": "0,1,2,3",
9        "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
10        "SampleAfterValue": "100003",
11        "Speculative": "1",
12        "UMask": "0x1"
13    },
14    {
15        "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
16        "CollectPEBSRecord": "2",
17        "Counter": "0,1,2,3",
18        "EventCode": "0x54",
19        "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
20        "PEBScounters": "0,1,2,3",
21        "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
22        "SampleAfterValue": "100003",
23        "Speculative": "1",
24        "UMask": "0x2"
25    },
26    {
27        "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
28        "CollectPEBSRecord": "2",
29        "Counter": "0,1,2,3",
30        "EventCode": "0x54",
31        "EventName": "TX_MEM.ABORT_CAPACITY_READ",
32        "PEBScounters": "0,1,2,3",
33        "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
34        "SampleAfterValue": "100003",
35        "Speculative": "1",
36        "UMask": "0x80"
37    },
38    {
39        "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region",
40        "CollectPEBSRecord": "2",
41        "Counter": "0,1,2,3,4,5,6,7",
42        "EventCode": "0x5d",
43        "EventName": "TX_EXEC.MISC2",
44        "PEBScounters": "0,1,2,3,4,5,6,7",
45        "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",
46        "SampleAfterValue": "100003",
47        "Speculative": "1",
48        "UMask": "0x2"
49    },
50    {
51        "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded",
52        "CollectPEBSRecord": "2",
53        "Counter": "0,1,2,3,4,5,6,7",
54        "EventCode": "0x5d",
55        "EventName": "TX_EXEC.MISC3",
56        "PEBScounters": "0,1,2,3,4,5,6,7",
57        "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.",
58        "SampleAfterValue": "100003",
59        "Speculative": "1",
60        "UMask": "0x4"
61    },
62    {
63        "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
64        "CollectPEBSRecord": "2",
65        "Counter": "0,1,2,3",
66        "CounterMask": "6",
67        "EventCode": "0xa3",
68        "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
69        "PEBScounters": "0,1,2,3",
70        "SampleAfterValue": "1000003",
71        "Speculative": "1",
72        "UMask": "0x6"
73    },
74    {
75        "BriefDescription": "Number of machine clears due to memory ordering conflicts.",
76        "CollectPEBSRecord": "2",
77        "Counter": "0,1,2,3,4,5,6,7",
78        "EventCode": "0xc3",
79        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
80        "PEBScounters": "0,1,2,3,4,5,6,7",
81        "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
82        "SampleAfterValue": "100003",
83        "Speculative": "1",
84        "UMask": "0x2"
85    },
86    {
87        "BriefDescription": "Number of times an RTM execution started.",
88        "CollectPEBSRecord": "2",
89        "Counter": "0,1,2,3,4,5,6,7",
90        "EventCode": "0xc9",
91        "EventName": "RTM_RETIRED.START",
92        "PEBScounters": "0,1,2,3,4,5,6,7",
93        "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
94        "SampleAfterValue": "100003",
95        "UMask": "0x1"
96    },
97    {
98        "BriefDescription": "Number of times an RTM execution successfully committed",
99        "CollectPEBSRecord": "2",
100        "Counter": "0,1,2,3,4,5,6,7",
101        "EventCode": "0xc9",
102        "EventName": "RTM_RETIRED.COMMIT",
103        "PEBScounters": "0,1,2,3,4,5,6,7",
104        "PublicDescription": "Counts the number of times RTM commit succeeded.",
105        "SampleAfterValue": "100003",
106        "UMask": "0x2"
107    },
108    {
109        "BriefDescription": "Number of times an RTM execution aborted.",
110        "CollectPEBSRecord": "2",
111        "Counter": "0,1,2,3,4,5,6,7",
112        "EventCode": "0xc9",
113        "EventName": "RTM_RETIRED.ABORTED",
114        "PEBScounters": "0,1,2,3,4,5,6,7",
115        "PublicDescription": "Counts the number of times RTM abort was triggered.",
116        "SampleAfterValue": "100003",
117        "UMask": "0x4"
118    },
119    {
120        "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
121        "CollectPEBSRecord": "2",
122        "Counter": "0,1,2,3,4,5,6,7",
123        "EventCode": "0xc9",
124        "EventName": "RTM_RETIRED.ABORTED_MEM",
125        "PEBScounters": "0,1,2,3,4,5,6,7",
126        "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
127        "SampleAfterValue": "100003",
128        "UMask": "0x8"
129    },
130    {
131        "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
132        "CollectPEBSRecord": "2",
133        "Counter": "0,1,2,3,4,5,6,7",
134        "EventCode": "0xc9",
135        "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
136        "PEBScounters": "0,1,2,3,4,5,6,7",
137        "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
138        "SampleAfterValue": "100003",
139        "UMask": "0x20"
140    },
141    {
142        "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
143        "CollectPEBSRecord": "2",
144        "Counter": "0,1,2,3,4,5,6,7",
145        "EventCode": "0xc9",
146        "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
147        "PEBScounters": "0,1,2,3,4,5,6,7",
148        "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
149        "SampleAfterValue": "100003",
150        "UMask": "0x40"
151    },
152    {
153        "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
154        "CollectPEBSRecord": "2",
155        "Counter": "0,1,2,3,4,5,6,7",
156        "EventCode": "0xc9",
157        "EventName": "RTM_RETIRED.ABORTED_EVENTS",
158        "PEBScounters": "0,1,2,3,4,5,6,7",
159        "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
160        "SampleAfterValue": "100003",
161        "UMask": "0x80"
162    },
163    {
164        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
165        "CollectPEBSRecord": "2",
166        "Counter": "0,1,2,3,4,5,6,7",
167        "Data_LA": "1",
168        "EventCode": "0xcd",
169        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
170        "MSRIndex": "0x3F6",
171        "MSRValue": "0x4",
172        "PEBS": "2",
173        "PEBScounters": "0,1,2,3,4,5,6,7",
174        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
175        "SampleAfterValue": "100003",
176        "TakenAlone": "1",
177        "UMask": "0x1"
178    },
179    {
180        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
181        "CollectPEBSRecord": "2",
182        "Counter": "0,1,2,3,4,5,6,7",
183        "Data_LA": "1",
184        "EventCode": "0xcd",
185        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
186        "MSRIndex": "0x3F6",
187        "MSRValue": "0x8",
188        "PEBS": "2",
189        "PEBScounters": "0,1,2,3,4,5,6,7",
190        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
191        "SampleAfterValue": "50021",
192        "TakenAlone": "1",
193        "UMask": "0x1"
194    },
195    {
196        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
197        "CollectPEBSRecord": "2",
198        "Counter": "0,1,2,3,4,5,6,7",
199        "Data_LA": "1",
200        "EventCode": "0xcd",
201        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
202        "MSRIndex": "0x3F6",
203        "MSRValue": "0x10",
204        "PEBS": "2",
205        "PEBScounters": "0,1,2,3,4,5,6,7",
206        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
207        "SampleAfterValue": "20011",
208        "TakenAlone": "1",
209        "UMask": "0x1"
210    },
211    {
212        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
213        "CollectPEBSRecord": "2",
214        "Counter": "0,1,2,3,4,5,6,7",
215        "Data_LA": "1",
216        "EventCode": "0xcd",
217        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
218        "MSRIndex": "0x3F6",
219        "MSRValue": "0x20",
220        "PEBS": "2",
221        "PEBScounters": "0,1,2,3,4,5,6,7",
222        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
223        "SampleAfterValue": "100007",
224        "TakenAlone": "1",
225        "UMask": "0x1"
226    },
227    {
228        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
229        "CollectPEBSRecord": "2",
230        "Counter": "0,1,2,3,4,5,6,7",
231        "Data_LA": "1",
232        "EventCode": "0xcd",
233        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
234        "MSRIndex": "0x3F6",
235        "MSRValue": "0x40",
236        "PEBS": "2",
237        "PEBScounters": "0,1,2,3,4,5,6,7",
238        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
239        "SampleAfterValue": "2003",
240        "TakenAlone": "1",
241        "UMask": "0x1"
242    },
243    {
244        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
245        "CollectPEBSRecord": "2",
246        "Counter": "0,1,2,3,4,5,6,7",
247        "Data_LA": "1",
248        "EventCode": "0xcd",
249        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
250        "MSRIndex": "0x3F6",
251        "MSRValue": "0x80",
252        "PEBS": "2",
253        "PEBScounters": "0,1,2,3,4,5,6,7",
254        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
255        "SampleAfterValue": "1009",
256        "TakenAlone": "1",
257        "UMask": "0x1"
258    },
259    {
260        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
261        "CollectPEBSRecord": "2",
262        "Counter": "0,1,2,3,4,5,6,7",
263        "Data_LA": "1",
264        "EventCode": "0xcd",
265        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
266        "MSRIndex": "0x3F6",
267        "MSRValue": "0x100",
268        "PEBS": "2",
269        "PEBScounters": "0,1,2,3,4,5,6,7",
270        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
271        "SampleAfterValue": "503",
272        "TakenAlone": "1",
273        "UMask": "0x1"
274    },
275    {
276        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
277        "CollectPEBSRecord": "2",
278        "Counter": "0,1,2,3,4,5,6,7",
279        "Data_LA": "1",
280        "EventCode": "0xcd",
281        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
282        "MSRIndex": "0x3F6",
283        "MSRValue": "0x200",
284        "PEBS": "2",
285        "PEBScounters": "0,1,2,3,4,5,6,7",
286        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
287        "SampleAfterValue": "101",
288        "TakenAlone": "1",
289        "UMask": "0x1"
290    }
291]