1cdb29a8fSJin Yao[ 2cdb29a8fSJin Yao { 309625cffSIan Rogers "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 4cdb29a8fSJin Yao "CollectPEBSRecord": "2", 5cdb29a8fSJin Yao "Counter": "0,1,2,3", 609625cffSIan Rogers "CounterMask": "6", 709625cffSIan Rogers "EventCode": "0xa3", 809625cffSIan Rogers "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 9cdb29a8fSJin Yao "PEBScounters": "0,1,2,3", 1009625cffSIan Rogers "SampleAfterValue": "1000003", 11cdb29a8fSJin Yao "Speculative": "1", 1209625cffSIan Rogers "UMask": "0x6" 13cdb29a8fSJin Yao }, 14cdb29a8fSJin Yao { 1509625cffSIan Rogers "BriefDescription": "Number of machine clears due to memory ordering conflicts.", 16cdb29a8fSJin Yao "CollectPEBSRecord": "2", 1709625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 1809625cffSIan Rogers "EventCode": "0xc3", 1909625cffSIan Rogers "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 2009625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 2109625cffSIan Rogers "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture", 22cdb29a8fSJin Yao "SampleAfterValue": "100003", 23cdb29a8fSJin Yao "Speculative": "1", 24cdb29a8fSJin Yao "UMask": "0x2" 25cdb29a8fSJin Yao }, 26cdb29a8fSJin Yao { 2709625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 2809625cffSIan Rogers "CollectPEBSRecord": "2", 2909625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 3009625cffSIan Rogers "Data_LA": "1", 3109625cffSIan Rogers "EventCode": "0xcd", 3209625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 3309625cffSIan Rogers "MSRIndex": "0x3F6", 3409625cffSIan Rogers "MSRValue": "0x80", 3509625cffSIan Rogers "PEBS": "2", 3609625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 3709625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 3809625cffSIan Rogers "SampleAfterValue": "1009", 3909625cffSIan Rogers "TakenAlone": "1", 4009625cffSIan Rogers "UMask": "0x1" 4109625cffSIan Rogers }, 4209625cffSIan Rogers { 4309625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 4409625cffSIan Rogers "CollectPEBSRecord": "2", 4509625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 4609625cffSIan Rogers "Data_LA": "1", 4709625cffSIan Rogers "EventCode": "0xcd", 4809625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 4909625cffSIan Rogers "MSRIndex": "0x3F6", 5009625cffSIan Rogers "MSRValue": "0x10", 5109625cffSIan Rogers "PEBS": "2", 5209625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 5309625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 5409625cffSIan Rogers "SampleAfterValue": "20011", 5509625cffSIan Rogers "TakenAlone": "1", 5609625cffSIan Rogers "UMask": "0x1" 5709625cffSIan Rogers }, 5809625cffSIan Rogers { 5909625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 6009625cffSIan Rogers "CollectPEBSRecord": "2", 6109625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 6209625cffSIan Rogers "Data_LA": "1", 6309625cffSIan Rogers "EventCode": "0xcd", 6409625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 6509625cffSIan Rogers "MSRIndex": "0x3F6", 6609625cffSIan Rogers "MSRValue": "0x100", 6709625cffSIan Rogers "PEBS": "2", 6809625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 6909625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 7009625cffSIan Rogers "SampleAfterValue": "503", 7109625cffSIan Rogers "TakenAlone": "1", 7209625cffSIan Rogers "UMask": "0x1" 7309625cffSIan Rogers }, 7409625cffSIan Rogers { 7509625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 7609625cffSIan Rogers "CollectPEBSRecord": "2", 7709625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 7809625cffSIan Rogers "Data_LA": "1", 7909625cffSIan Rogers "EventCode": "0xcd", 8009625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 8109625cffSIan Rogers "MSRIndex": "0x3F6", 8209625cffSIan Rogers "MSRValue": "0x20", 8309625cffSIan Rogers "PEBS": "2", 8409625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 8509625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 8609625cffSIan Rogers "SampleAfterValue": "100007", 8709625cffSIan Rogers "TakenAlone": "1", 8809625cffSIan Rogers "UMask": "0x1" 8909625cffSIan Rogers }, 9009625cffSIan Rogers { 9109625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 9209625cffSIan Rogers "CollectPEBSRecord": "2", 9309625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 9409625cffSIan Rogers "Data_LA": "1", 9509625cffSIan Rogers "EventCode": "0xcd", 9609625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 9709625cffSIan Rogers "MSRIndex": "0x3F6", 9809625cffSIan Rogers "MSRValue": "0x4", 9909625cffSIan Rogers "PEBS": "2", 10009625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 10109625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 10209625cffSIan Rogers "SampleAfterValue": "100003", 10309625cffSIan Rogers "TakenAlone": "1", 10409625cffSIan Rogers "UMask": "0x1" 10509625cffSIan Rogers }, 10609625cffSIan Rogers { 10709625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 10809625cffSIan Rogers "CollectPEBSRecord": "2", 10909625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 11009625cffSIan Rogers "Data_LA": "1", 11109625cffSIan Rogers "EventCode": "0xcd", 11209625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 11309625cffSIan Rogers "MSRIndex": "0x3F6", 11409625cffSIan Rogers "MSRValue": "0x200", 11509625cffSIan Rogers "PEBS": "2", 11609625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 11709625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 11809625cffSIan Rogers "SampleAfterValue": "101", 11909625cffSIan Rogers "TakenAlone": "1", 12009625cffSIan Rogers "UMask": "0x1" 12109625cffSIan Rogers }, 12209625cffSIan Rogers { 12309625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 12409625cffSIan Rogers "CollectPEBSRecord": "2", 12509625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 12609625cffSIan Rogers "Data_LA": "1", 12709625cffSIan Rogers "EventCode": "0xcd", 12809625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 12909625cffSIan Rogers "MSRIndex": "0x3F6", 13009625cffSIan Rogers "MSRValue": "0x40", 13109625cffSIan Rogers "PEBS": "2", 13209625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 13309625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 13409625cffSIan Rogers "SampleAfterValue": "2003", 13509625cffSIan Rogers "TakenAlone": "1", 13609625cffSIan Rogers "UMask": "0x1" 13709625cffSIan Rogers }, 13809625cffSIan Rogers { 13909625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 14009625cffSIan Rogers "CollectPEBSRecord": "2", 14109625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 14209625cffSIan Rogers "Data_LA": "1", 14309625cffSIan Rogers "EventCode": "0xcd", 14409625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 14509625cffSIan Rogers "MSRIndex": "0x3F6", 14609625cffSIan Rogers "MSRValue": "0x8", 14709625cffSIan Rogers "PEBS": "2", 14809625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 14909625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 15009625cffSIan Rogers "SampleAfterValue": "50021", 15109625cffSIan Rogers "TakenAlone": "1", 15209625cffSIan Rogers "UMask": "0x1" 15309625cffSIan Rogers }, 15409625cffSIan Rogers { 15509625cffSIan Rogers "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", 15609625cffSIan Rogers "Counter": "0,1,2,3", 15709625cffSIan Rogers "EventCode": "0xB7, 0xBB", 15809625cffSIan Rogers "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", 15909625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 16009625cffSIan Rogers "MSRValue": "0x3FBFC00004", 16109625cffSIan Rogers "Offcore": "1", 16209625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 16309625cffSIan Rogers "SampleAfterValue": "100003", 16409625cffSIan Rogers "UMask": "0x1" 16509625cffSIan Rogers }, 16609625cffSIan Rogers { 16709625cffSIan Rogers "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 16809625cffSIan Rogers "Counter": "0,1,2,3", 16909625cffSIan Rogers "EventCode": "0xB7, 0xBB", 17009625cffSIan Rogers "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL", 17109625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 172*f25db21bSIan Rogers "MSRValue": "0x3F84400004", 17309625cffSIan Rogers "Offcore": "1", 17409625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 17509625cffSIan Rogers "SampleAfterValue": "100003", 17609625cffSIan Rogers "UMask": "0x1" 17709625cffSIan Rogers }, 17809625cffSIan Rogers { 17909625cffSIan Rogers "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", 18009625cffSIan Rogers "Counter": "0,1,2,3", 18109625cffSIan Rogers "EventCode": "0xB7, 0xBB", 18209625cffSIan Rogers "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", 18309625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 18409625cffSIan Rogers "MSRValue": "0x3FBFC00001", 18509625cffSIan Rogers "Offcore": "1", 18609625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 18709625cffSIan Rogers "SampleAfterValue": "100003", 18809625cffSIan Rogers "UMask": "0x1" 18909625cffSIan Rogers }, 19009625cffSIan Rogers { 19109625cffSIan Rogers "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 19209625cffSIan Rogers "Counter": "0,1,2,3", 19309625cffSIan Rogers "EventCode": "0xB7, 0xBB", 19409625cffSIan Rogers "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", 19509625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 196*f25db21bSIan Rogers "MSRValue": "0x3F84400001", 19709625cffSIan Rogers "Offcore": "1", 19809625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 19909625cffSIan Rogers "SampleAfterValue": "100003", 20009625cffSIan Rogers "UMask": "0x1" 20109625cffSIan Rogers }, 20209625cffSIan Rogers { 20309625cffSIan Rogers "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 20409625cffSIan Rogers "Counter": "0,1,2,3", 20509625cffSIan Rogers "EventCode": "0xB7, 0xBB", 20609625cffSIan Rogers "EventName": "OCR.DEMAND_RFO.L3_MISS", 20709625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 20809625cffSIan Rogers "MSRValue": "0x3F3FC00002", 20909625cffSIan Rogers "Offcore": "1", 21009625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 21109625cffSIan Rogers "SampleAfterValue": "100003", 21209625cffSIan Rogers "UMask": "0x1" 21309625cffSIan Rogers }, 21409625cffSIan Rogers { 21509625cffSIan Rogers "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.", 21609625cffSIan Rogers "Counter": "0,1,2,3", 21709625cffSIan Rogers "EventCode": "0xB7, 0xBB", 21809625cffSIan Rogers "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", 21909625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 220*f25db21bSIan Rogers "MSRValue": "0x3F04400002", 22109625cffSIan Rogers "Offcore": "1", 22209625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 22309625cffSIan Rogers "SampleAfterValue": "100003", 22409625cffSIan Rogers "UMask": "0x1" 22509625cffSIan Rogers }, 22609625cffSIan Rogers { 22709625cffSIan Rogers "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 22809625cffSIan Rogers "Counter": "0,1,2,3", 22909625cffSIan Rogers "EventCode": "0xB7, 0xBB", 23009625cffSIan Rogers "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS", 23109625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 23209625cffSIan Rogers "MSRValue": "0x3FBFC00400", 23309625cffSIan Rogers "Offcore": "1", 23409625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 23509625cffSIan Rogers "SampleAfterValue": "100003", 23609625cffSIan Rogers "UMask": "0x1" 23709625cffSIan Rogers }, 23809625cffSIan Rogers { 23909625cffSIan Rogers "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 24009625cffSIan Rogers "Counter": "0,1,2,3", 24109625cffSIan Rogers "EventCode": "0xB7, 0xBB", 24209625cffSIan Rogers "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS_LOCAL", 24309625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 244*f25db21bSIan Rogers "MSRValue": "0x3F84400400", 24509625cffSIan Rogers "Offcore": "1", 24609625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 24709625cffSIan Rogers "SampleAfterValue": "100003", 24809625cffSIan Rogers "UMask": "0x1" 24909625cffSIan Rogers }, 25009625cffSIan Rogers { 25109625cffSIan Rogers "BriefDescription": "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.", 25209625cffSIan Rogers "Counter": "0,1,2,3", 25309625cffSIan Rogers "EventCode": "0xB7, 0xBB", 25409625cffSIan Rogers "EventName": "OCR.HWPF_L3.L3_MISS", 25509625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 25609625cffSIan Rogers "MSRValue": "0x94002380", 25709625cffSIan Rogers "Offcore": "1", 25809625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 25909625cffSIan Rogers "SampleAfterValue": "100003", 26009625cffSIan Rogers "UMask": "0x1" 26109625cffSIan Rogers }, 26209625cffSIan Rogers { 26309625cffSIan Rogers "BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 26409625cffSIan Rogers "Counter": "0,1,2,3", 26509625cffSIan Rogers "EventCode": "0xB7, 0xBB", 26609625cffSIan Rogers "EventName": "OCR.HWPF_L3.L3_MISS_LOCAL", 26709625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 26809625cffSIan Rogers "MSRValue": "0x84002380", 26909625cffSIan Rogers "Offcore": "1", 27009625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 27109625cffSIan Rogers "SampleAfterValue": "100003", 27209625cffSIan Rogers "UMask": "0x1" 27309625cffSIan Rogers }, 27409625cffSIan Rogers { 27509625cffSIan Rogers "BriefDescription": "Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 27609625cffSIan Rogers "Counter": "0,1,2,3", 27709625cffSIan Rogers "EventCode": "0xB7, 0xBB", 27809625cffSIan Rogers "EventName": "OCR.ITOM.L3_MISS_LOCAL", 27909625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 28009625cffSIan Rogers "MSRValue": "0x84000002", 28109625cffSIan Rogers "Offcore": "1", 28209625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 28309625cffSIan Rogers "SampleAfterValue": "100003", 28409625cffSIan Rogers "UMask": "0x1" 28509625cffSIan Rogers }, 28609625cffSIan Rogers { 28709625cffSIan Rogers "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches.", 28809625cffSIan Rogers "Counter": "0,1,2,3", 28909625cffSIan Rogers "EventCode": "0xB7, 0xBB", 29009625cffSIan Rogers "EventName": "OCR.OTHER.L3_MISS", 29109625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 29209625cffSIan Rogers "MSRValue": "0x3FBFC08000", 29309625cffSIan Rogers "Offcore": "1", 29409625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 29509625cffSIan Rogers "SampleAfterValue": "100003", 29609625cffSIan Rogers "UMask": "0x1" 29709625cffSIan Rogers }, 29809625cffSIan Rogers { 29909625cffSIan Rogers "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 30009625cffSIan Rogers "Counter": "0,1,2,3", 30109625cffSIan Rogers "EventCode": "0xB7, 0xBB", 30209625cffSIan Rogers "EventName": "OCR.OTHER.L3_MISS_LOCAL", 30309625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 304*f25db21bSIan Rogers "MSRValue": "0x3F84408000", 30509625cffSIan Rogers "Offcore": "1", 30609625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 30709625cffSIan Rogers "SampleAfterValue": "100003", 30809625cffSIan Rogers "UMask": "0x1" 30909625cffSIan Rogers }, 31009625cffSIan Rogers { 31109625cffSIan Rogers "BriefDescription": "Counts hardware and software prefetches to all cache levels that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 31209625cffSIan Rogers "Counter": "0,1,2,3", 31309625cffSIan Rogers "EventCode": "0xB7, 0xBB", 31409625cffSIan Rogers "EventName": "OCR.PREFETCHES.L3_MISS_LOCAL", 31509625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 316*f25db21bSIan Rogers "MSRValue": "0x3F844027F0", 31709625cffSIan Rogers "Offcore": "1", 31809625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 31909625cffSIan Rogers "SampleAfterValue": "100003", 32009625cffSIan Rogers "UMask": "0x1" 32109625cffSIan Rogers }, 32209625cffSIan Rogers { 32309625cffSIan Rogers "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.", 32409625cffSIan Rogers "Counter": "0,1,2,3", 32509625cffSIan Rogers "EventCode": "0xB7, 0xBB", 32609625cffSIan Rogers "EventName": "OCR.READS_TO_CORE.L3_MISS", 32709625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 32809625cffSIan Rogers "MSRValue": "0x3F3FC00477", 32909625cffSIan Rogers "Offcore": "1", 33009625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 33109625cffSIan Rogers "SampleAfterValue": "100003", 33209625cffSIan Rogers "UMask": "0x1" 33309625cffSIan Rogers }, 33409625cffSIan Rogers { 33509625cffSIan Rogers "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.", 33609625cffSIan Rogers "Counter": "0,1,2,3", 33709625cffSIan Rogers "EventCode": "0xB7, 0xBB", 33809625cffSIan Rogers "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", 33909625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 340*f25db21bSIan Rogers "MSRValue": "0x3F04400477", 341*f25db21bSIan Rogers "Offcore": "1", 342*f25db21bSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 343*f25db21bSIan Rogers "SampleAfterValue": "100003", 344*f25db21bSIan Rogers "UMask": "0x1" 345*f25db21bSIan Rogers }, 346*f25db21bSIan Rogers { 347*f25db21bSIan Rogers "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.", 348*f25db21bSIan Rogers "Counter": "0,1,2,3", 349*f25db21bSIan Rogers "EventCode": "0xB7, 0xBB", 350*f25db21bSIan Rogers "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET", 351*f25db21bSIan Rogers "MSRIndex": "0x1a6,0x1a7", 352*f25db21bSIan Rogers "MSRValue": "0x70CC00477", 35309625cffSIan Rogers "Offcore": "1", 35409625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 35509625cffSIan Rogers "SampleAfterValue": "100003", 35609625cffSIan Rogers "UMask": "0x1" 35709625cffSIan Rogers }, 35809625cffSIan Rogers { 35909625cffSIan Rogers "BriefDescription": "Counts streaming stores that missed the local socket's L1, L2, and L3 caches.", 36009625cffSIan Rogers "Counter": "0,1,2,3", 36109625cffSIan Rogers "EventCode": "0xB7, 0xBB", 36209625cffSIan Rogers "EventName": "OCR.STREAMING_WR.L3_MISS", 36309625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 36409625cffSIan Rogers "MSRValue": "0x94000800", 36509625cffSIan Rogers "Offcore": "1", 36609625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 36709625cffSIan Rogers "SampleAfterValue": "100003", 36809625cffSIan Rogers "UMask": "0x1" 36909625cffSIan Rogers }, 37009625cffSIan Rogers { 37109625cffSIan Rogers "BriefDescription": "Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 37209625cffSIan Rogers "Counter": "0,1,2,3", 37309625cffSIan Rogers "EventCode": "0xB7, 0xBB", 37409625cffSIan Rogers "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL", 37509625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 37609625cffSIan Rogers "MSRValue": "0x84000800", 37709625cffSIan Rogers "Offcore": "1", 37809625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 37909625cffSIan Rogers "SampleAfterValue": "100003", 38009625cffSIan Rogers "UMask": "0x1" 38109625cffSIan Rogers }, 38209625cffSIan Rogers { 38309625cffSIan Rogers "BriefDescription": "Counts demand data read requests that miss the L3 cache.", 384cdb29a8fSJin Yao "CollectPEBSRecord": "2", 385cdb29a8fSJin Yao "Counter": "0,1,2,3", 38609625cffSIan Rogers "EventCode": "0xb0", 38709625cffSIan Rogers "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 388cdb29a8fSJin Yao "PEBScounters": "0,1,2,3", 389cdb29a8fSJin Yao "SampleAfterValue": "100003", 390cdb29a8fSJin Yao "Speculative": "1", 39109625cffSIan Rogers "UMask": "0x10" 39209625cffSIan Rogers }, 39309625cffSIan Rogers { 39409625cffSIan Rogers "BriefDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending.", 39509625cffSIan Rogers "CollectPEBSRecord": "2", 39609625cffSIan Rogers "Counter": "0,1,2,3", 39709625cffSIan Rogers "CounterMask": "1", 39809625cffSIan Rogers "EventCode": "0x60", 39909625cffSIan Rogers "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", 40009625cffSIan Rogers "PEBScounters": "0,1,2,3", 40109625cffSIan Rogers "PublicDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.", 40209625cffSIan Rogers "SampleAfterValue": "1000003", 40309625cffSIan Rogers "Speculative": "1", 40409625cffSIan Rogers "UMask": "0x10" 40509625cffSIan Rogers }, 40609625cffSIan Rogers { 40709625cffSIan Rogers "BriefDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.", 40809625cffSIan Rogers "CollectPEBSRecord": "2", 40909625cffSIan Rogers "Counter": "0,1,2,3", 41009625cffSIan Rogers "EventCode": "0x60", 41109625cffSIan Rogers "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", 41209625cffSIan Rogers "PEBScounters": "0,1,2,3", 41309625cffSIan Rogers "PublicDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.", 41409625cffSIan Rogers "SampleAfterValue": "2000003", 41509625cffSIan Rogers "Speculative": "1", 41609625cffSIan Rogers "UMask": "0x10" 41709625cffSIan Rogers }, 41809625cffSIan Rogers { 41909625cffSIan Rogers "BriefDescription": "Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache.", 42009625cffSIan Rogers "CollectPEBSRecord": "2", 42109625cffSIan Rogers "Counter": "0,1,2,3", 42209625cffSIan Rogers "CounterMask": "6", 42309625cffSIan Rogers "EventCode": "0x60", 42409625cffSIan Rogers "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", 42509625cffSIan Rogers "PEBScounters": "0,1,2,3", 42609625cffSIan Rogers "PublicDescription": "Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache. Note that this event does not capture all elapsed cycles while the requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.", 42709625cffSIan Rogers "SampleAfterValue": "2000003", 42809625cffSIan Rogers "Speculative": "1", 42909625cffSIan Rogers "UMask": "0x10" 43009625cffSIan Rogers }, 43109625cffSIan Rogers { 43209625cffSIan Rogers "BriefDescription": "Number of times an RTM execution aborted.", 43309625cffSIan Rogers "CollectPEBSRecord": "2", 43409625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 43509625cffSIan Rogers "EventCode": "0xc9", 43609625cffSIan Rogers "EventName": "RTM_RETIRED.ABORTED", 43709625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 43809625cffSIan Rogers "PublicDescription": "Counts the number of times RTM abort was triggered.", 43909625cffSIan Rogers "SampleAfterValue": "100003", 44009625cffSIan Rogers "UMask": "0x4" 44109625cffSIan Rogers }, 44209625cffSIan Rogers { 44309625cffSIan Rogers "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 44409625cffSIan Rogers "CollectPEBSRecord": "2", 44509625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 44609625cffSIan Rogers "EventCode": "0xc9", 44709625cffSIan Rogers "EventName": "RTM_RETIRED.ABORTED_EVENTS", 44809625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 44909625cffSIan Rogers "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 45009625cffSIan Rogers "SampleAfterValue": "100003", 451cdb29a8fSJin Yao "UMask": "0x80" 452cdb29a8fSJin Yao }, 453cdb29a8fSJin Yao { 45409625cffSIan Rogers "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 45509625cffSIan Rogers "CollectPEBSRecord": "2", 45609625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 45709625cffSIan Rogers "EventCode": "0xc9", 45809625cffSIan Rogers "EventName": "RTM_RETIRED.ABORTED_MEM", 45909625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 46009625cffSIan Rogers "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 46109625cffSIan Rogers "SampleAfterValue": "100003", 46209625cffSIan Rogers "UMask": "0x8" 46309625cffSIan Rogers }, 46409625cffSIan Rogers { 46509625cffSIan Rogers "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 46609625cffSIan Rogers "CollectPEBSRecord": "2", 46709625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 46809625cffSIan Rogers "EventCode": "0xc9", 46909625cffSIan Rogers "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 47009625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 47109625cffSIan Rogers "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.", 47209625cffSIan Rogers "SampleAfterValue": "100003", 47309625cffSIan Rogers "UMask": "0x40" 47409625cffSIan Rogers }, 47509625cffSIan Rogers { 47609625cffSIan Rogers "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 47709625cffSIan Rogers "CollectPEBSRecord": "2", 47809625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 47909625cffSIan Rogers "EventCode": "0xc9", 48009625cffSIan Rogers "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 48109625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 48209625cffSIan Rogers "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.", 48309625cffSIan Rogers "SampleAfterValue": "100003", 48409625cffSIan Rogers "UMask": "0x20" 48509625cffSIan Rogers }, 48609625cffSIan Rogers { 48709625cffSIan Rogers "BriefDescription": "Number of times an RTM execution successfully committed", 48809625cffSIan Rogers "CollectPEBSRecord": "2", 48909625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 49009625cffSIan Rogers "EventCode": "0xc9", 49109625cffSIan Rogers "EventName": "RTM_RETIRED.COMMIT", 49209625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 49309625cffSIan Rogers "PublicDescription": "Counts the number of times RTM commit succeeded.", 49409625cffSIan Rogers "SampleAfterValue": "100003", 49509625cffSIan Rogers "UMask": "0x2" 49609625cffSIan Rogers }, 49709625cffSIan Rogers { 49809625cffSIan Rogers "BriefDescription": "Number of times an RTM execution started.", 49909625cffSIan Rogers "CollectPEBSRecord": "2", 50009625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 50109625cffSIan Rogers "EventCode": "0xc9", 50209625cffSIan Rogers "EventName": "RTM_RETIRED.START", 50309625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 50409625cffSIan Rogers "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.", 50509625cffSIan Rogers "SampleAfterValue": "100003", 50609625cffSIan Rogers "UMask": "0x1" 50709625cffSIan Rogers }, 50809625cffSIan Rogers { 509cdb29a8fSJin Yao "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region", 510cdb29a8fSJin Yao "CollectPEBSRecord": "2", 511cdb29a8fSJin Yao "Counter": "0,1,2,3,4,5,6,7", 512cdb29a8fSJin Yao "EventCode": "0x5d", 513cdb29a8fSJin Yao "EventName": "TX_EXEC.MISC2", 514cdb29a8fSJin Yao "PEBScounters": "0,1,2,3,4,5,6,7", 515cdb29a8fSJin Yao "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.", 516cdb29a8fSJin Yao "SampleAfterValue": "100003", 517cdb29a8fSJin Yao "Speculative": "1", 518cdb29a8fSJin Yao "UMask": "0x2" 519cdb29a8fSJin Yao }, 520cdb29a8fSJin Yao { 521cdb29a8fSJin Yao "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded", 522cdb29a8fSJin Yao "CollectPEBSRecord": "2", 523cdb29a8fSJin Yao "Counter": "0,1,2,3,4,5,6,7", 524cdb29a8fSJin Yao "EventCode": "0x5d", 525cdb29a8fSJin Yao "EventName": "TX_EXEC.MISC3", 526cdb29a8fSJin Yao "PEBScounters": "0,1,2,3,4,5,6,7", 527cdb29a8fSJin Yao "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.", 528cdb29a8fSJin Yao "SampleAfterValue": "100003", 529cdb29a8fSJin Yao "Speculative": "1", 530cdb29a8fSJin Yao "UMask": "0x4" 531cdb29a8fSJin Yao }, 532cdb29a8fSJin Yao { 53309625cffSIan Rogers "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads", 534cdb29a8fSJin Yao "CollectPEBSRecord": "2", 535cdb29a8fSJin Yao "Counter": "0,1,2,3", 53609625cffSIan Rogers "EventCode": "0x54", 53709625cffSIan Rogers "EventName": "TX_MEM.ABORT_CAPACITY_READ", 538cdb29a8fSJin Yao "PEBScounters": "0,1,2,3", 53909625cffSIan Rogers "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads", 540cdb29a8fSJin Yao "SampleAfterValue": "100003", 541cdb29a8fSJin Yao "Speculative": "1", 542cdb29a8fSJin Yao "UMask": "0x80" 543cdb29a8fSJin Yao }, 544cdb29a8fSJin Yao { 54509625cffSIan Rogers "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.", 546cdb29a8fSJin Yao "CollectPEBSRecord": "2", 54709625cffSIan Rogers "Counter": "0,1,2,3", 54809625cffSIan Rogers "EventCode": "0x54", 54909625cffSIan Rogers "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", 55009625cffSIan Rogers "PEBScounters": "0,1,2,3", 55109625cffSIan Rogers "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.", 552cdb29a8fSJin Yao "SampleAfterValue": "100003", 55309625cffSIan Rogers "Speculative": "1", 55409625cffSIan Rogers "UMask": "0x2" 555cdb29a8fSJin Yao }, 556cdb29a8fSJin Yao { 55709625cffSIan Rogers "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", 558cdb29a8fSJin Yao "CollectPEBSRecord": "2", 55909625cffSIan Rogers "Counter": "0,1,2,3", 56009625cffSIan Rogers "EventCode": "0x54", 56109625cffSIan Rogers "EventName": "TX_MEM.ABORT_CONFLICT", 56209625cffSIan Rogers "PEBScounters": "0,1,2,3", 56309625cffSIan Rogers "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", 56409625cffSIan Rogers "SampleAfterValue": "100003", 56509625cffSIan Rogers "Speculative": "1", 566cdb29a8fSJin Yao "UMask": "0x1" 567cdb29a8fSJin Yao } 568cdb29a8fSJin Yao]