1cdb29a8fSJin Yao[ 2cdb29a8fSJin Yao { 309625cffSIan Rogers "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 4cdb29a8fSJin Yao "CollectPEBSRecord": "2", 5cdb29a8fSJin Yao "Counter": "0,1,2,3", 609625cffSIan Rogers "CounterMask": "6", 709625cffSIan Rogers "EventCode": "0xa3", 809625cffSIan Rogers "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 9cdb29a8fSJin Yao "PEBScounters": "0,1,2,3", 1009625cffSIan Rogers "SampleAfterValue": "1000003", 11cdb29a8fSJin Yao "Speculative": "1", 1209625cffSIan Rogers "UMask": "0x6" 13cdb29a8fSJin Yao }, 14cdb29a8fSJin Yao { 1509625cffSIan Rogers "BriefDescription": "Number of machine clears due to memory ordering conflicts.", 16cdb29a8fSJin Yao "CollectPEBSRecord": "2", 1709625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 1809625cffSIan Rogers "EventCode": "0xc3", 1909625cffSIan Rogers "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 2009625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 2109625cffSIan Rogers "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture", 22cdb29a8fSJin Yao "SampleAfterValue": "100003", 23cdb29a8fSJin Yao "Speculative": "1", 24cdb29a8fSJin Yao "UMask": "0x2" 25cdb29a8fSJin Yao }, 26cdb29a8fSJin Yao { 2709625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 2809625cffSIan Rogers "CollectPEBSRecord": "2", 2909625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 3009625cffSIan Rogers "Data_LA": "1", 3109625cffSIan Rogers "EventCode": "0xcd", 3209625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 3309625cffSIan Rogers "MSRIndex": "0x3F6", 3409625cffSIan Rogers "MSRValue": "0x80", 3509625cffSIan Rogers "PEBS": "2", 3609625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 3709625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 3809625cffSIan Rogers "SampleAfterValue": "1009", 3909625cffSIan Rogers "TakenAlone": "1", 4009625cffSIan Rogers "UMask": "0x1" 4109625cffSIan Rogers }, 4209625cffSIan Rogers { 4309625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 4409625cffSIan Rogers "CollectPEBSRecord": "2", 4509625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 4609625cffSIan Rogers "Data_LA": "1", 4709625cffSIan Rogers "EventCode": "0xcd", 4809625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 4909625cffSIan Rogers "MSRIndex": "0x3F6", 5009625cffSIan Rogers "MSRValue": "0x10", 5109625cffSIan Rogers "PEBS": "2", 5209625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 5309625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 5409625cffSIan Rogers "SampleAfterValue": "20011", 5509625cffSIan Rogers "TakenAlone": "1", 5609625cffSIan Rogers "UMask": "0x1" 5709625cffSIan Rogers }, 5809625cffSIan Rogers { 5909625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 6009625cffSIan Rogers "CollectPEBSRecord": "2", 6109625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 6209625cffSIan Rogers "Data_LA": "1", 6309625cffSIan Rogers "EventCode": "0xcd", 6409625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 6509625cffSIan Rogers "MSRIndex": "0x3F6", 6609625cffSIan Rogers "MSRValue": "0x100", 6709625cffSIan Rogers "PEBS": "2", 6809625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 6909625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 7009625cffSIan Rogers "SampleAfterValue": "503", 7109625cffSIan Rogers "TakenAlone": "1", 7209625cffSIan Rogers "UMask": "0x1" 7309625cffSIan Rogers }, 7409625cffSIan Rogers { 7509625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 7609625cffSIan Rogers "CollectPEBSRecord": "2", 7709625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 7809625cffSIan Rogers "Data_LA": "1", 7909625cffSIan Rogers "EventCode": "0xcd", 8009625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 8109625cffSIan Rogers "MSRIndex": "0x3F6", 8209625cffSIan Rogers "MSRValue": "0x20", 8309625cffSIan Rogers "PEBS": "2", 8409625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 8509625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 8609625cffSIan Rogers "SampleAfterValue": "100007", 8709625cffSIan Rogers "TakenAlone": "1", 8809625cffSIan Rogers "UMask": "0x1" 8909625cffSIan Rogers }, 9009625cffSIan Rogers { 9109625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 9209625cffSIan Rogers "CollectPEBSRecord": "2", 9309625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 9409625cffSIan Rogers "Data_LA": "1", 9509625cffSIan Rogers "EventCode": "0xcd", 9609625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 9709625cffSIan Rogers "MSRIndex": "0x3F6", 9809625cffSIan Rogers "MSRValue": "0x4", 9909625cffSIan Rogers "PEBS": "2", 10009625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 10109625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 10209625cffSIan Rogers "SampleAfterValue": "100003", 10309625cffSIan Rogers "TakenAlone": "1", 10409625cffSIan Rogers "UMask": "0x1" 10509625cffSIan Rogers }, 10609625cffSIan Rogers { 10709625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 10809625cffSIan Rogers "CollectPEBSRecord": "2", 10909625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 11009625cffSIan Rogers "Data_LA": "1", 11109625cffSIan Rogers "EventCode": "0xcd", 11209625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 11309625cffSIan Rogers "MSRIndex": "0x3F6", 11409625cffSIan Rogers "MSRValue": "0x200", 11509625cffSIan Rogers "PEBS": "2", 11609625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 11709625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 11809625cffSIan Rogers "SampleAfterValue": "101", 11909625cffSIan Rogers "TakenAlone": "1", 12009625cffSIan Rogers "UMask": "0x1" 12109625cffSIan Rogers }, 12209625cffSIan Rogers { 12309625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 12409625cffSIan Rogers "CollectPEBSRecord": "2", 12509625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 12609625cffSIan Rogers "Data_LA": "1", 12709625cffSIan Rogers "EventCode": "0xcd", 12809625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 12909625cffSIan Rogers "MSRIndex": "0x3F6", 13009625cffSIan Rogers "MSRValue": "0x40", 13109625cffSIan Rogers "PEBS": "2", 13209625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 13309625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 13409625cffSIan Rogers "SampleAfterValue": "2003", 13509625cffSIan Rogers "TakenAlone": "1", 13609625cffSIan Rogers "UMask": "0x1" 13709625cffSIan Rogers }, 13809625cffSIan Rogers { 13909625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 14009625cffSIan Rogers "CollectPEBSRecord": "2", 14109625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 14209625cffSIan Rogers "Data_LA": "1", 14309625cffSIan Rogers "EventCode": "0xcd", 14409625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 14509625cffSIan Rogers "MSRIndex": "0x3F6", 14609625cffSIan Rogers "MSRValue": "0x8", 14709625cffSIan Rogers "PEBS": "2", 14809625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 14909625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 15009625cffSIan Rogers "SampleAfterValue": "50021", 15109625cffSIan Rogers "TakenAlone": "1", 15209625cffSIan Rogers "UMask": "0x1" 15309625cffSIan Rogers }, 15409625cffSIan Rogers { 15509625cffSIan Rogers "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", 15609625cffSIan Rogers "Counter": "0,1,2,3", 15709625cffSIan Rogers "EventCode": "0xB7, 0xBB", 15809625cffSIan Rogers "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", 15909625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 16009625cffSIan Rogers "MSRValue": "0x3FBFC00004", 16109625cffSIan Rogers "Offcore": "1", 16209625cffSIan Rogers "SampleAfterValue": "100003", 16309625cffSIan Rogers "UMask": "0x1" 16409625cffSIan Rogers }, 16509625cffSIan Rogers { 16609625cffSIan Rogers "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 16709625cffSIan Rogers "Counter": "0,1,2,3", 16809625cffSIan Rogers "EventCode": "0xB7, 0xBB", 16909625cffSIan Rogers "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL", 17009625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 171f25db21bSIan Rogers "MSRValue": "0x3F84400004", 17209625cffSIan Rogers "Offcore": "1", 17309625cffSIan Rogers "SampleAfterValue": "100003", 17409625cffSIan Rogers "UMask": "0x1" 17509625cffSIan Rogers }, 17609625cffSIan Rogers { 17709625cffSIan Rogers "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", 17809625cffSIan Rogers "Counter": "0,1,2,3", 17909625cffSIan Rogers "EventCode": "0xB7, 0xBB", 18009625cffSIan Rogers "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", 18109625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 18209625cffSIan Rogers "MSRValue": "0x3FBFC00001", 18309625cffSIan Rogers "Offcore": "1", 18409625cffSIan Rogers "SampleAfterValue": "100003", 18509625cffSIan Rogers "UMask": "0x1" 18609625cffSIan Rogers }, 18709625cffSIan Rogers { 18809625cffSIan Rogers "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 18909625cffSIan Rogers "Counter": "0,1,2,3", 19009625cffSIan Rogers "EventCode": "0xB7, 0xBB", 19109625cffSIan Rogers "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", 19209625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 193f25db21bSIan Rogers "MSRValue": "0x3F84400001", 19409625cffSIan Rogers "Offcore": "1", 19509625cffSIan Rogers "SampleAfterValue": "100003", 19609625cffSIan Rogers "UMask": "0x1" 19709625cffSIan Rogers }, 19809625cffSIan Rogers { 19909625cffSIan Rogers "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 20009625cffSIan Rogers "Counter": "0,1,2,3", 20109625cffSIan Rogers "EventCode": "0xB7, 0xBB", 20209625cffSIan Rogers "EventName": "OCR.DEMAND_RFO.L3_MISS", 20309625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 20409625cffSIan Rogers "MSRValue": "0x3F3FC00002", 20509625cffSIan Rogers "Offcore": "1", 20609625cffSIan Rogers "SampleAfterValue": "100003", 20709625cffSIan Rogers "UMask": "0x1" 20809625cffSIan Rogers }, 20909625cffSIan Rogers { 21009625cffSIan Rogers "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.", 21109625cffSIan Rogers "Counter": "0,1,2,3", 21209625cffSIan Rogers "EventCode": "0xB7, 0xBB", 21309625cffSIan Rogers "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", 21409625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 215f25db21bSIan Rogers "MSRValue": "0x3F04400002", 21609625cffSIan Rogers "Offcore": "1", 21709625cffSIan Rogers "SampleAfterValue": "100003", 21809625cffSIan Rogers "UMask": "0x1" 21909625cffSIan Rogers }, 22009625cffSIan Rogers { 22109625cffSIan Rogers "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 22209625cffSIan Rogers "Counter": "0,1,2,3", 22309625cffSIan Rogers "EventCode": "0xB7, 0xBB", 22409625cffSIan Rogers "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS", 22509625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 22609625cffSIan Rogers "MSRValue": "0x3FBFC00400", 22709625cffSIan Rogers "Offcore": "1", 22809625cffSIan Rogers "SampleAfterValue": "100003", 22909625cffSIan Rogers "UMask": "0x1" 23009625cffSIan Rogers }, 23109625cffSIan Rogers { 23209625cffSIan Rogers "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 23309625cffSIan Rogers "Counter": "0,1,2,3", 23409625cffSIan Rogers "EventCode": "0xB7, 0xBB", 23509625cffSIan Rogers "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS_LOCAL", 23609625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 237f25db21bSIan Rogers "MSRValue": "0x3F84400400", 23809625cffSIan Rogers "Offcore": "1", 23909625cffSIan Rogers "SampleAfterValue": "100003", 24009625cffSIan Rogers "UMask": "0x1" 24109625cffSIan Rogers }, 24209625cffSIan Rogers { 24309625cffSIan Rogers "BriefDescription": "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.", 24409625cffSIan Rogers "Counter": "0,1,2,3", 24509625cffSIan Rogers "EventCode": "0xB7, 0xBB", 24609625cffSIan Rogers "EventName": "OCR.HWPF_L3.L3_MISS", 24709625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 24809625cffSIan Rogers "MSRValue": "0x94002380", 24909625cffSIan Rogers "Offcore": "1", 25009625cffSIan Rogers "SampleAfterValue": "100003", 25109625cffSIan Rogers "UMask": "0x1" 25209625cffSIan Rogers }, 25309625cffSIan Rogers { 25409625cffSIan Rogers "BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 25509625cffSIan Rogers "Counter": "0,1,2,3", 25609625cffSIan Rogers "EventCode": "0xB7, 0xBB", 25709625cffSIan Rogers "EventName": "OCR.HWPF_L3.L3_MISS_LOCAL", 25809625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 25909625cffSIan Rogers "MSRValue": "0x84002380", 26009625cffSIan Rogers "Offcore": "1", 26109625cffSIan Rogers "SampleAfterValue": "100003", 26209625cffSIan Rogers "UMask": "0x1" 26309625cffSIan Rogers }, 26409625cffSIan Rogers { 26509625cffSIan Rogers "BriefDescription": "Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 26609625cffSIan Rogers "Counter": "0,1,2,3", 26709625cffSIan Rogers "EventCode": "0xB7, 0xBB", 26809625cffSIan Rogers "EventName": "OCR.ITOM.L3_MISS_LOCAL", 26909625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 27009625cffSIan Rogers "MSRValue": "0x84000002", 27109625cffSIan Rogers "Offcore": "1", 27209625cffSIan Rogers "SampleAfterValue": "100003", 27309625cffSIan Rogers "UMask": "0x1" 27409625cffSIan Rogers }, 27509625cffSIan Rogers { 27609625cffSIan Rogers "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches.", 27709625cffSIan Rogers "Counter": "0,1,2,3", 27809625cffSIan Rogers "EventCode": "0xB7, 0xBB", 27909625cffSIan Rogers "EventName": "OCR.OTHER.L3_MISS", 28009625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 28109625cffSIan Rogers "MSRValue": "0x3FBFC08000", 28209625cffSIan Rogers "Offcore": "1", 28309625cffSIan Rogers "SampleAfterValue": "100003", 28409625cffSIan Rogers "UMask": "0x1" 28509625cffSIan Rogers }, 28609625cffSIan Rogers { 28709625cffSIan Rogers "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 28809625cffSIan Rogers "Counter": "0,1,2,3", 28909625cffSIan Rogers "EventCode": "0xB7, 0xBB", 29009625cffSIan Rogers "EventName": "OCR.OTHER.L3_MISS_LOCAL", 29109625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 292f25db21bSIan Rogers "MSRValue": "0x3F84408000", 29309625cffSIan Rogers "Offcore": "1", 29409625cffSIan Rogers "SampleAfterValue": "100003", 29509625cffSIan Rogers "UMask": "0x1" 29609625cffSIan Rogers }, 29709625cffSIan Rogers { 29809625cffSIan Rogers "BriefDescription": "Counts hardware and software prefetches to all cache levels that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 29909625cffSIan Rogers "Counter": "0,1,2,3", 30009625cffSIan Rogers "EventCode": "0xB7, 0xBB", 30109625cffSIan Rogers "EventName": "OCR.PREFETCHES.L3_MISS_LOCAL", 30209625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 303f25db21bSIan Rogers "MSRValue": "0x3F844027F0", 30409625cffSIan Rogers "Offcore": "1", 30509625cffSIan Rogers "SampleAfterValue": "100003", 30609625cffSIan Rogers "UMask": "0x1" 30709625cffSIan Rogers }, 30809625cffSIan Rogers { 309*d214d0c2SIan Rogers "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.", 31009625cffSIan Rogers "Counter": "0,1,2,3", 31109625cffSIan Rogers "EventCode": "0xB7, 0xBB", 31209625cffSIan Rogers "EventName": "OCR.READS_TO_CORE.L3_MISS", 31309625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 31409625cffSIan Rogers "MSRValue": "0x3F3FC00477", 31509625cffSIan Rogers "Offcore": "1", 31609625cffSIan Rogers "SampleAfterValue": "100003", 31709625cffSIan Rogers "UMask": "0x1" 31809625cffSIan Rogers }, 31909625cffSIan Rogers { 320*d214d0c2SIan Rogers "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.", 32109625cffSIan Rogers "Counter": "0,1,2,3", 32209625cffSIan Rogers "EventCode": "0xB7, 0xBB", 32309625cffSIan Rogers "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", 32409625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 325f25db21bSIan Rogers "MSRValue": "0x3F04400477", 326f25db21bSIan Rogers "Offcore": "1", 327f25db21bSIan Rogers "SampleAfterValue": "100003", 328f25db21bSIan Rogers "UMask": "0x1" 329f25db21bSIan Rogers }, 330f25db21bSIan Rogers { 331*d214d0c2SIan Rogers "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.", 332f25db21bSIan Rogers "Counter": "0,1,2,3", 333f25db21bSIan Rogers "EventCode": "0xB7, 0xBB", 334f25db21bSIan Rogers "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET", 335f25db21bSIan Rogers "MSRIndex": "0x1a6,0x1a7", 336f25db21bSIan Rogers "MSRValue": "0x70CC00477", 33709625cffSIan Rogers "Offcore": "1", 33809625cffSIan Rogers "SampleAfterValue": "100003", 33909625cffSIan Rogers "UMask": "0x1" 34009625cffSIan Rogers }, 34109625cffSIan Rogers { 34209625cffSIan Rogers "BriefDescription": "Counts streaming stores that missed the local socket's L1, L2, and L3 caches.", 34309625cffSIan Rogers "Counter": "0,1,2,3", 34409625cffSIan Rogers "EventCode": "0xB7, 0xBB", 34509625cffSIan Rogers "EventName": "OCR.STREAMING_WR.L3_MISS", 34609625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 34709625cffSIan Rogers "MSRValue": "0x94000800", 34809625cffSIan Rogers "Offcore": "1", 34909625cffSIan Rogers "SampleAfterValue": "100003", 35009625cffSIan Rogers "UMask": "0x1" 35109625cffSIan Rogers }, 35209625cffSIan Rogers { 35309625cffSIan Rogers "BriefDescription": "Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 35409625cffSIan Rogers "Counter": "0,1,2,3", 35509625cffSIan Rogers "EventCode": "0xB7, 0xBB", 35609625cffSIan Rogers "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL", 35709625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 35809625cffSIan Rogers "MSRValue": "0x84000800", 35909625cffSIan Rogers "Offcore": "1", 36009625cffSIan Rogers "SampleAfterValue": "100003", 36109625cffSIan Rogers "UMask": "0x1" 36209625cffSIan Rogers }, 36309625cffSIan Rogers { 36409625cffSIan Rogers "BriefDescription": "Counts demand data read requests that miss the L3 cache.", 365cdb29a8fSJin Yao "CollectPEBSRecord": "2", 366cdb29a8fSJin Yao "Counter": "0,1,2,3", 36709625cffSIan Rogers "EventCode": "0xb0", 36809625cffSIan Rogers "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 369cdb29a8fSJin Yao "PEBScounters": "0,1,2,3", 370cdb29a8fSJin Yao "SampleAfterValue": "100003", 371cdb29a8fSJin Yao "Speculative": "1", 37209625cffSIan Rogers "UMask": "0x10" 37309625cffSIan Rogers }, 37409625cffSIan Rogers { 37509625cffSIan Rogers "BriefDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending.", 37609625cffSIan Rogers "CollectPEBSRecord": "2", 37709625cffSIan Rogers "Counter": "0,1,2,3", 37809625cffSIan Rogers "CounterMask": "1", 37909625cffSIan Rogers "EventCode": "0x60", 38009625cffSIan Rogers "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", 38109625cffSIan Rogers "PEBScounters": "0,1,2,3", 38209625cffSIan Rogers "PublicDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.", 38309625cffSIan Rogers "SampleAfterValue": "1000003", 38409625cffSIan Rogers "Speculative": "1", 38509625cffSIan Rogers "UMask": "0x10" 38609625cffSIan Rogers }, 38709625cffSIan Rogers { 38809625cffSIan Rogers "BriefDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.", 38909625cffSIan Rogers "CollectPEBSRecord": "2", 39009625cffSIan Rogers "Counter": "0,1,2,3", 39109625cffSIan Rogers "EventCode": "0x60", 39209625cffSIan Rogers "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", 39309625cffSIan Rogers "PEBScounters": "0,1,2,3", 39409625cffSIan Rogers "PublicDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.", 39509625cffSIan Rogers "SampleAfterValue": "2000003", 39609625cffSIan Rogers "Speculative": "1", 39709625cffSIan Rogers "UMask": "0x10" 39809625cffSIan Rogers }, 39909625cffSIan Rogers { 40009625cffSIan Rogers "BriefDescription": "Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache.", 40109625cffSIan Rogers "CollectPEBSRecord": "2", 40209625cffSIan Rogers "Counter": "0,1,2,3", 40309625cffSIan Rogers "CounterMask": "6", 40409625cffSIan Rogers "EventCode": "0x60", 40509625cffSIan Rogers "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", 40609625cffSIan Rogers "PEBScounters": "0,1,2,3", 40709625cffSIan Rogers "PublicDescription": "Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache. Note that this event does not capture all elapsed cycles while the requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.", 40809625cffSIan Rogers "SampleAfterValue": "2000003", 40909625cffSIan Rogers "Speculative": "1", 41009625cffSIan Rogers "UMask": "0x10" 41109625cffSIan Rogers }, 41209625cffSIan Rogers { 41309625cffSIan Rogers "BriefDescription": "Number of times an RTM execution aborted.", 41409625cffSIan Rogers "CollectPEBSRecord": "2", 41509625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 41609625cffSIan Rogers "EventCode": "0xc9", 41709625cffSIan Rogers "EventName": "RTM_RETIRED.ABORTED", 41809625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 41909625cffSIan Rogers "PublicDescription": "Counts the number of times RTM abort was triggered.", 42009625cffSIan Rogers "SampleAfterValue": "100003", 42109625cffSIan Rogers "UMask": "0x4" 42209625cffSIan Rogers }, 42309625cffSIan Rogers { 42409625cffSIan Rogers "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 42509625cffSIan Rogers "CollectPEBSRecord": "2", 42609625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 42709625cffSIan Rogers "EventCode": "0xc9", 42809625cffSIan Rogers "EventName": "RTM_RETIRED.ABORTED_EVENTS", 42909625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 43009625cffSIan Rogers "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 43109625cffSIan Rogers "SampleAfterValue": "100003", 432cdb29a8fSJin Yao "UMask": "0x80" 433cdb29a8fSJin Yao }, 434cdb29a8fSJin Yao { 43509625cffSIan Rogers "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 43609625cffSIan Rogers "CollectPEBSRecord": "2", 43709625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 43809625cffSIan Rogers "EventCode": "0xc9", 43909625cffSIan Rogers "EventName": "RTM_RETIRED.ABORTED_MEM", 44009625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 44109625cffSIan Rogers "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 44209625cffSIan Rogers "SampleAfterValue": "100003", 44309625cffSIan Rogers "UMask": "0x8" 44409625cffSIan Rogers }, 44509625cffSIan Rogers { 44609625cffSIan Rogers "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 44709625cffSIan Rogers "CollectPEBSRecord": "2", 44809625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 44909625cffSIan Rogers "EventCode": "0xc9", 45009625cffSIan Rogers "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 45109625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 45209625cffSIan Rogers "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.", 45309625cffSIan Rogers "SampleAfterValue": "100003", 45409625cffSIan Rogers "UMask": "0x40" 45509625cffSIan Rogers }, 45609625cffSIan Rogers { 45709625cffSIan Rogers "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 45809625cffSIan Rogers "CollectPEBSRecord": "2", 45909625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 46009625cffSIan Rogers "EventCode": "0xc9", 46109625cffSIan Rogers "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 46209625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 46309625cffSIan Rogers "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.", 46409625cffSIan Rogers "SampleAfterValue": "100003", 46509625cffSIan Rogers "UMask": "0x20" 46609625cffSIan Rogers }, 46709625cffSIan Rogers { 46809625cffSIan Rogers "BriefDescription": "Number of times an RTM execution successfully committed", 46909625cffSIan Rogers "CollectPEBSRecord": "2", 47009625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 47109625cffSIan Rogers "EventCode": "0xc9", 47209625cffSIan Rogers "EventName": "RTM_RETIRED.COMMIT", 47309625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 47409625cffSIan Rogers "PublicDescription": "Counts the number of times RTM commit succeeded.", 47509625cffSIan Rogers "SampleAfterValue": "100003", 47609625cffSIan Rogers "UMask": "0x2" 47709625cffSIan Rogers }, 47809625cffSIan Rogers { 47909625cffSIan Rogers "BriefDescription": "Number of times an RTM execution started.", 48009625cffSIan Rogers "CollectPEBSRecord": "2", 48109625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 48209625cffSIan Rogers "EventCode": "0xc9", 48309625cffSIan Rogers "EventName": "RTM_RETIRED.START", 48409625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 48509625cffSIan Rogers "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.", 48609625cffSIan Rogers "SampleAfterValue": "100003", 48709625cffSIan Rogers "UMask": "0x1" 48809625cffSIan Rogers }, 48909625cffSIan Rogers { 490cdb29a8fSJin Yao "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region", 491cdb29a8fSJin Yao "CollectPEBSRecord": "2", 492cdb29a8fSJin Yao "Counter": "0,1,2,3,4,5,6,7", 493cdb29a8fSJin Yao "EventCode": "0x5d", 494cdb29a8fSJin Yao "EventName": "TX_EXEC.MISC2", 495cdb29a8fSJin Yao "PEBScounters": "0,1,2,3,4,5,6,7", 496cdb29a8fSJin Yao "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.", 497cdb29a8fSJin Yao "SampleAfterValue": "100003", 498cdb29a8fSJin Yao "Speculative": "1", 499cdb29a8fSJin Yao "UMask": "0x2" 500cdb29a8fSJin Yao }, 501cdb29a8fSJin Yao { 502cdb29a8fSJin Yao "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded", 503cdb29a8fSJin Yao "CollectPEBSRecord": "2", 504cdb29a8fSJin Yao "Counter": "0,1,2,3,4,5,6,7", 505cdb29a8fSJin Yao "EventCode": "0x5d", 506cdb29a8fSJin Yao "EventName": "TX_EXEC.MISC3", 507cdb29a8fSJin Yao "PEBScounters": "0,1,2,3,4,5,6,7", 508cdb29a8fSJin Yao "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.", 509cdb29a8fSJin Yao "SampleAfterValue": "100003", 510cdb29a8fSJin Yao "Speculative": "1", 511cdb29a8fSJin Yao "UMask": "0x4" 512cdb29a8fSJin Yao }, 513cdb29a8fSJin Yao { 51409625cffSIan Rogers "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads", 515cdb29a8fSJin Yao "CollectPEBSRecord": "2", 516cdb29a8fSJin Yao "Counter": "0,1,2,3", 51709625cffSIan Rogers "EventCode": "0x54", 51809625cffSIan Rogers "EventName": "TX_MEM.ABORT_CAPACITY_READ", 519cdb29a8fSJin Yao "PEBScounters": "0,1,2,3", 52009625cffSIan Rogers "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads", 521cdb29a8fSJin Yao "SampleAfterValue": "100003", 522cdb29a8fSJin Yao "Speculative": "1", 523cdb29a8fSJin Yao "UMask": "0x80" 524cdb29a8fSJin Yao }, 525cdb29a8fSJin Yao { 52609625cffSIan Rogers "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.", 527cdb29a8fSJin Yao "CollectPEBSRecord": "2", 52809625cffSIan Rogers "Counter": "0,1,2,3", 52909625cffSIan Rogers "EventCode": "0x54", 53009625cffSIan Rogers "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", 53109625cffSIan Rogers "PEBScounters": "0,1,2,3", 53209625cffSIan Rogers "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.", 533cdb29a8fSJin Yao "SampleAfterValue": "100003", 53409625cffSIan Rogers "Speculative": "1", 53509625cffSIan Rogers "UMask": "0x2" 536cdb29a8fSJin Yao }, 537cdb29a8fSJin Yao { 53809625cffSIan Rogers "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", 539cdb29a8fSJin Yao "CollectPEBSRecord": "2", 54009625cffSIan Rogers "Counter": "0,1,2,3", 54109625cffSIan Rogers "EventCode": "0x54", 54209625cffSIan Rogers "EventName": "TX_MEM.ABORT_CONFLICT", 54309625cffSIan Rogers "PEBScounters": "0,1,2,3", 54409625cffSIan Rogers "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", 54509625cffSIan Rogers "SampleAfterValue": "100003", 54609625cffSIan Rogers "Speculative": "1", 547cdb29a8fSJin Yao "UMask": "0x1" 548cdb29a8fSJin Yao } 549cdb29a8fSJin Yao] 550