1cdb29a8fSJin Yao[ 2cdb29a8fSJin Yao { 3*09625cffSIan Rogers "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 4cdb29a8fSJin Yao "CollectPEBSRecord": "2", 5cdb29a8fSJin Yao "Counter": "0,1,2,3", 6*09625cffSIan Rogers "CounterMask": "6", 7*09625cffSIan Rogers "EventCode": "0xa3", 8*09625cffSIan Rogers "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 9cdb29a8fSJin Yao "PEBScounters": "0,1,2,3", 10*09625cffSIan Rogers "SampleAfterValue": "1000003", 11cdb29a8fSJin Yao "Speculative": "1", 12*09625cffSIan Rogers "UMask": "0x6" 13cdb29a8fSJin Yao }, 14cdb29a8fSJin Yao { 15*09625cffSIan Rogers "BriefDescription": "Number of machine clears due to memory ordering conflicts.", 16cdb29a8fSJin Yao "CollectPEBSRecord": "2", 17*09625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 18*09625cffSIan Rogers "EventCode": "0xc3", 19*09625cffSIan Rogers "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 20*09625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 21*09625cffSIan Rogers "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture", 22cdb29a8fSJin Yao "SampleAfterValue": "100003", 23cdb29a8fSJin Yao "Speculative": "1", 24cdb29a8fSJin Yao "UMask": "0x2" 25cdb29a8fSJin Yao }, 26cdb29a8fSJin Yao { 27*09625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 28*09625cffSIan Rogers "CollectPEBSRecord": "2", 29*09625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 30*09625cffSIan Rogers "Data_LA": "1", 31*09625cffSIan Rogers "EventCode": "0xcd", 32*09625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 33*09625cffSIan Rogers "MSRIndex": "0x3F6", 34*09625cffSIan Rogers "MSRValue": "0x80", 35*09625cffSIan Rogers "PEBS": "2", 36*09625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 37*09625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 38*09625cffSIan Rogers "SampleAfterValue": "1009", 39*09625cffSIan Rogers "TakenAlone": "1", 40*09625cffSIan Rogers "UMask": "0x1" 41*09625cffSIan Rogers }, 42*09625cffSIan Rogers { 43*09625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 44*09625cffSIan Rogers "CollectPEBSRecord": "2", 45*09625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 46*09625cffSIan Rogers "Data_LA": "1", 47*09625cffSIan Rogers "EventCode": "0xcd", 48*09625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 49*09625cffSIan Rogers "MSRIndex": "0x3F6", 50*09625cffSIan Rogers "MSRValue": "0x10", 51*09625cffSIan Rogers "PEBS": "2", 52*09625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 53*09625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 54*09625cffSIan Rogers "SampleAfterValue": "20011", 55*09625cffSIan Rogers "TakenAlone": "1", 56*09625cffSIan Rogers "UMask": "0x1" 57*09625cffSIan Rogers }, 58*09625cffSIan Rogers { 59*09625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 60*09625cffSIan Rogers "CollectPEBSRecord": "2", 61*09625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 62*09625cffSIan Rogers "Data_LA": "1", 63*09625cffSIan Rogers "EventCode": "0xcd", 64*09625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 65*09625cffSIan Rogers "MSRIndex": "0x3F6", 66*09625cffSIan Rogers "MSRValue": "0x100", 67*09625cffSIan Rogers "PEBS": "2", 68*09625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 69*09625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 70*09625cffSIan Rogers "SampleAfterValue": "503", 71*09625cffSIan Rogers "TakenAlone": "1", 72*09625cffSIan Rogers "UMask": "0x1" 73*09625cffSIan Rogers }, 74*09625cffSIan Rogers { 75*09625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 76*09625cffSIan Rogers "CollectPEBSRecord": "2", 77*09625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 78*09625cffSIan Rogers "Data_LA": "1", 79*09625cffSIan Rogers "EventCode": "0xcd", 80*09625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 81*09625cffSIan Rogers "MSRIndex": "0x3F6", 82*09625cffSIan Rogers "MSRValue": "0x20", 83*09625cffSIan Rogers "PEBS": "2", 84*09625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 85*09625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 86*09625cffSIan Rogers "SampleAfterValue": "100007", 87*09625cffSIan Rogers "TakenAlone": "1", 88*09625cffSIan Rogers "UMask": "0x1" 89*09625cffSIan Rogers }, 90*09625cffSIan Rogers { 91*09625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 92*09625cffSIan Rogers "CollectPEBSRecord": "2", 93*09625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 94*09625cffSIan Rogers "Data_LA": "1", 95*09625cffSIan Rogers "EventCode": "0xcd", 96*09625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 97*09625cffSIan Rogers "MSRIndex": "0x3F6", 98*09625cffSIan Rogers "MSRValue": "0x4", 99*09625cffSIan Rogers "PEBS": "2", 100*09625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 101*09625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 102*09625cffSIan Rogers "SampleAfterValue": "100003", 103*09625cffSIan Rogers "TakenAlone": "1", 104*09625cffSIan Rogers "UMask": "0x1" 105*09625cffSIan Rogers }, 106*09625cffSIan Rogers { 107*09625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 108*09625cffSIan Rogers "CollectPEBSRecord": "2", 109*09625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 110*09625cffSIan Rogers "Data_LA": "1", 111*09625cffSIan Rogers "EventCode": "0xcd", 112*09625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 113*09625cffSIan Rogers "MSRIndex": "0x3F6", 114*09625cffSIan Rogers "MSRValue": "0x200", 115*09625cffSIan Rogers "PEBS": "2", 116*09625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 117*09625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 118*09625cffSIan Rogers "SampleAfterValue": "101", 119*09625cffSIan Rogers "TakenAlone": "1", 120*09625cffSIan Rogers "UMask": "0x1" 121*09625cffSIan Rogers }, 122*09625cffSIan Rogers { 123*09625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 124*09625cffSIan Rogers "CollectPEBSRecord": "2", 125*09625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 126*09625cffSIan Rogers "Data_LA": "1", 127*09625cffSIan Rogers "EventCode": "0xcd", 128*09625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 129*09625cffSIan Rogers "MSRIndex": "0x3F6", 130*09625cffSIan Rogers "MSRValue": "0x40", 131*09625cffSIan Rogers "PEBS": "2", 132*09625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 133*09625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 134*09625cffSIan Rogers "SampleAfterValue": "2003", 135*09625cffSIan Rogers "TakenAlone": "1", 136*09625cffSIan Rogers "UMask": "0x1" 137*09625cffSIan Rogers }, 138*09625cffSIan Rogers { 139*09625cffSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 140*09625cffSIan Rogers "CollectPEBSRecord": "2", 141*09625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 142*09625cffSIan Rogers "Data_LA": "1", 143*09625cffSIan Rogers "EventCode": "0xcd", 144*09625cffSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 145*09625cffSIan Rogers "MSRIndex": "0x3F6", 146*09625cffSIan Rogers "MSRValue": "0x8", 147*09625cffSIan Rogers "PEBS": "2", 148*09625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 149*09625cffSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 150*09625cffSIan Rogers "SampleAfterValue": "50021", 151*09625cffSIan Rogers "TakenAlone": "1", 152*09625cffSIan Rogers "UMask": "0x1" 153*09625cffSIan Rogers }, 154*09625cffSIan Rogers { 155*09625cffSIan Rogers "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", 156*09625cffSIan Rogers "Counter": "0,1,2,3", 157*09625cffSIan Rogers "EventCode": "0xB7, 0xBB", 158*09625cffSIan Rogers "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", 159*09625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 160*09625cffSIan Rogers "MSRValue": "0x3FBFC00004", 161*09625cffSIan Rogers "Offcore": "1", 162*09625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 163*09625cffSIan Rogers "SampleAfterValue": "100003", 164*09625cffSIan Rogers "UMask": "0x1" 165*09625cffSIan Rogers }, 166*09625cffSIan Rogers { 167*09625cffSIan Rogers "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 168*09625cffSIan Rogers "Counter": "0,1,2,3", 169*09625cffSIan Rogers "EventCode": "0xB7, 0xBB", 170*09625cffSIan Rogers "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL", 171*09625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 172*09625cffSIan Rogers "MSRValue": "0x3F8CC00004", 173*09625cffSIan Rogers "Offcore": "1", 174*09625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 175*09625cffSIan Rogers "SampleAfterValue": "100003", 176*09625cffSIan Rogers "UMask": "0x1" 177*09625cffSIan Rogers }, 178*09625cffSIan Rogers { 179*09625cffSIan Rogers "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", 180*09625cffSIan Rogers "Counter": "0,1,2,3", 181*09625cffSIan Rogers "EventCode": "0xB7, 0xBB", 182*09625cffSIan Rogers "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", 183*09625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 184*09625cffSIan Rogers "MSRValue": "0x3FBFC00001", 185*09625cffSIan Rogers "Offcore": "1", 186*09625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 187*09625cffSIan Rogers "SampleAfterValue": "100003", 188*09625cffSIan Rogers "UMask": "0x1" 189*09625cffSIan Rogers }, 190*09625cffSIan Rogers { 191*09625cffSIan Rogers "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 192*09625cffSIan Rogers "Counter": "0,1,2,3", 193*09625cffSIan Rogers "EventCode": "0xB7, 0xBB", 194*09625cffSIan Rogers "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", 195*09625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 196*09625cffSIan Rogers "MSRValue": "0x3F8CC00001", 197*09625cffSIan Rogers "Offcore": "1", 198*09625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 199*09625cffSIan Rogers "SampleAfterValue": "100003", 200*09625cffSIan Rogers "UMask": "0x1" 201*09625cffSIan Rogers }, 202*09625cffSIan Rogers { 203*09625cffSIan Rogers "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 204*09625cffSIan Rogers "Counter": "0,1,2,3", 205*09625cffSIan Rogers "EventCode": "0xB7, 0xBB", 206*09625cffSIan Rogers "EventName": "OCR.DEMAND_RFO.L3_MISS", 207*09625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 208*09625cffSIan Rogers "MSRValue": "0x3F3FC00002", 209*09625cffSIan Rogers "Offcore": "1", 210*09625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 211*09625cffSIan Rogers "SampleAfterValue": "100003", 212*09625cffSIan Rogers "UMask": "0x1" 213*09625cffSIan Rogers }, 214*09625cffSIan Rogers { 215*09625cffSIan Rogers "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.", 216*09625cffSIan Rogers "Counter": "0,1,2,3", 217*09625cffSIan Rogers "EventCode": "0xB7, 0xBB", 218*09625cffSIan Rogers "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", 219*09625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 220*09625cffSIan Rogers "MSRValue": "0x3F0CC00002", 221*09625cffSIan Rogers "Offcore": "1", 222*09625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 223*09625cffSIan Rogers "SampleAfterValue": "100003", 224*09625cffSIan Rogers "UMask": "0x1" 225*09625cffSIan Rogers }, 226*09625cffSIan Rogers { 227*09625cffSIan Rogers "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 228*09625cffSIan Rogers "Counter": "0,1,2,3", 229*09625cffSIan Rogers "EventCode": "0xB7, 0xBB", 230*09625cffSIan Rogers "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS", 231*09625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 232*09625cffSIan Rogers "MSRValue": "0x3FBFC00400", 233*09625cffSIan Rogers "Offcore": "1", 234*09625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 235*09625cffSIan Rogers "SampleAfterValue": "100003", 236*09625cffSIan Rogers "UMask": "0x1" 237*09625cffSIan Rogers }, 238*09625cffSIan Rogers { 239*09625cffSIan Rogers "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 240*09625cffSIan Rogers "Counter": "0,1,2,3", 241*09625cffSIan Rogers "EventCode": "0xB7, 0xBB", 242*09625cffSIan Rogers "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS_LOCAL", 243*09625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 244*09625cffSIan Rogers "MSRValue": "0x3F8CC00400", 245*09625cffSIan Rogers "Offcore": "1", 246*09625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 247*09625cffSIan Rogers "SampleAfterValue": "100003", 248*09625cffSIan Rogers "UMask": "0x1" 249*09625cffSIan Rogers }, 250*09625cffSIan Rogers { 251*09625cffSIan Rogers "BriefDescription": "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.", 252*09625cffSIan Rogers "Counter": "0,1,2,3", 253*09625cffSIan Rogers "EventCode": "0xB7, 0xBB", 254*09625cffSIan Rogers "EventName": "OCR.HWPF_L3.L3_MISS", 255*09625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 256*09625cffSIan Rogers "MSRValue": "0x94002380", 257*09625cffSIan Rogers "Offcore": "1", 258*09625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 259*09625cffSIan Rogers "SampleAfterValue": "100003", 260*09625cffSIan Rogers "UMask": "0x1" 261*09625cffSIan Rogers }, 262*09625cffSIan Rogers { 263*09625cffSIan Rogers "BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 264*09625cffSIan Rogers "Counter": "0,1,2,3", 265*09625cffSIan Rogers "EventCode": "0xB7, 0xBB", 266*09625cffSIan Rogers "EventName": "OCR.HWPF_L3.L3_MISS_LOCAL", 267*09625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 268*09625cffSIan Rogers "MSRValue": "0x84002380", 269*09625cffSIan Rogers "Offcore": "1", 270*09625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 271*09625cffSIan Rogers "SampleAfterValue": "100003", 272*09625cffSIan Rogers "UMask": "0x1" 273*09625cffSIan Rogers }, 274*09625cffSIan Rogers { 275*09625cffSIan Rogers "BriefDescription": "Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 276*09625cffSIan Rogers "Counter": "0,1,2,3", 277*09625cffSIan Rogers "EventCode": "0xB7, 0xBB", 278*09625cffSIan Rogers "EventName": "OCR.ITOM.L3_MISS_LOCAL", 279*09625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 280*09625cffSIan Rogers "MSRValue": "0x84000002", 281*09625cffSIan Rogers "Offcore": "1", 282*09625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 283*09625cffSIan Rogers "SampleAfterValue": "100003", 284*09625cffSIan Rogers "UMask": "0x1" 285*09625cffSIan Rogers }, 286*09625cffSIan Rogers { 287*09625cffSIan Rogers "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches.", 288*09625cffSIan Rogers "Counter": "0,1,2,3", 289*09625cffSIan Rogers "EventCode": "0xB7, 0xBB", 290*09625cffSIan Rogers "EventName": "OCR.OTHER.L3_MISS", 291*09625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 292*09625cffSIan Rogers "MSRValue": "0x3FBFC08000", 293*09625cffSIan Rogers "Offcore": "1", 294*09625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 295*09625cffSIan Rogers "SampleAfterValue": "100003", 296*09625cffSIan Rogers "UMask": "0x1" 297*09625cffSIan Rogers }, 298*09625cffSIan Rogers { 299*09625cffSIan Rogers "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 300*09625cffSIan Rogers "Counter": "0,1,2,3", 301*09625cffSIan Rogers "EventCode": "0xB7, 0xBB", 302*09625cffSIan Rogers "EventName": "OCR.OTHER.L3_MISS_LOCAL", 303*09625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 304*09625cffSIan Rogers "MSRValue": "0x3F8CC08000", 305*09625cffSIan Rogers "Offcore": "1", 306*09625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 307*09625cffSIan Rogers "SampleAfterValue": "100003", 308*09625cffSIan Rogers "UMask": "0x1" 309*09625cffSIan Rogers }, 310*09625cffSIan Rogers { 311*09625cffSIan Rogers "BriefDescription": "Counts hardware and software prefetches to all cache levels that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 312*09625cffSIan Rogers "Counter": "0,1,2,3", 313*09625cffSIan Rogers "EventCode": "0xB7, 0xBB", 314*09625cffSIan Rogers "EventName": "OCR.PREFETCHES.L3_MISS_LOCAL", 315*09625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 316*09625cffSIan Rogers "MSRValue": "0x3F8CC027F0", 317*09625cffSIan Rogers "Offcore": "1", 318*09625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 319*09625cffSIan Rogers "SampleAfterValue": "100003", 320*09625cffSIan Rogers "UMask": "0x1" 321*09625cffSIan Rogers }, 322*09625cffSIan Rogers { 323*09625cffSIan Rogers "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.", 324*09625cffSIan Rogers "Counter": "0,1,2,3", 325*09625cffSIan Rogers "EventCode": "0xB7, 0xBB", 326*09625cffSIan Rogers "EventName": "OCR.READS_TO_CORE.L3_MISS", 327*09625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 328*09625cffSIan Rogers "MSRValue": "0x3F3FC00477", 329*09625cffSIan Rogers "Offcore": "1", 330*09625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 331*09625cffSIan Rogers "SampleAfterValue": "100003", 332*09625cffSIan Rogers "UMask": "0x1" 333*09625cffSIan Rogers }, 334*09625cffSIan Rogers { 335*09625cffSIan Rogers "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.", 336*09625cffSIan Rogers "Counter": "0,1,2,3", 337*09625cffSIan Rogers "EventCode": "0xB7, 0xBB", 338*09625cffSIan Rogers "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", 339*09625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 340*09625cffSIan Rogers "MSRValue": "0x3F0CC00477", 341*09625cffSIan Rogers "Offcore": "1", 342*09625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 343*09625cffSIan Rogers "SampleAfterValue": "100003", 344*09625cffSIan Rogers "UMask": "0x1" 345*09625cffSIan Rogers }, 346*09625cffSIan Rogers { 347*09625cffSIan Rogers "BriefDescription": "Counts streaming stores that missed the local socket's L1, L2, and L3 caches.", 348*09625cffSIan Rogers "Counter": "0,1,2,3", 349*09625cffSIan Rogers "EventCode": "0xB7, 0xBB", 350*09625cffSIan Rogers "EventName": "OCR.STREAMING_WR.L3_MISS", 351*09625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 352*09625cffSIan Rogers "MSRValue": "0x94000800", 353*09625cffSIan Rogers "Offcore": "1", 354*09625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 355*09625cffSIan Rogers "SampleAfterValue": "100003", 356*09625cffSIan Rogers "UMask": "0x1" 357*09625cffSIan Rogers }, 358*09625cffSIan Rogers { 359*09625cffSIan Rogers "BriefDescription": "Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 360*09625cffSIan Rogers "Counter": "0,1,2,3", 361*09625cffSIan Rogers "EventCode": "0xB7, 0xBB", 362*09625cffSIan Rogers "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL", 363*09625cffSIan Rogers "MSRIndex": "0x1a6,0x1a7", 364*09625cffSIan Rogers "MSRValue": "0x84000800", 365*09625cffSIan Rogers "Offcore": "1", 366*09625cffSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 367*09625cffSIan Rogers "SampleAfterValue": "100003", 368*09625cffSIan Rogers "UMask": "0x1" 369*09625cffSIan Rogers }, 370*09625cffSIan Rogers { 371*09625cffSIan Rogers "BriefDescription": "Counts demand data read requests that miss the L3 cache.", 372cdb29a8fSJin Yao "CollectPEBSRecord": "2", 373cdb29a8fSJin Yao "Counter": "0,1,2,3", 374*09625cffSIan Rogers "EventCode": "0xb0", 375*09625cffSIan Rogers "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 376cdb29a8fSJin Yao "PEBScounters": "0,1,2,3", 377cdb29a8fSJin Yao "SampleAfterValue": "100003", 378cdb29a8fSJin Yao "Speculative": "1", 379*09625cffSIan Rogers "UMask": "0x10" 380*09625cffSIan Rogers }, 381*09625cffSIan Rogers { 382*09625cffSIan Rogers "BriefDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending.", 383*09625cffSIan Rogers "CollectPEBSRecord": "2", 384*09625cffSIan Rogers "Counter": "0,1,2,3", 385*09625cffSIan Rogers "CounterMask": "1", 386*09625cffSIan Rogers "EventCode": "0x60", 387*09625cffSIan Rogers "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", 388*09625cffSIan Rogers "PEBScounters": "0,1,2,3", 389*09625cffSIan Rogers "PublicDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.", 390*09625cffSIan Rogers "SampleAfterValue": "1000003", 391*09625cffSIan Rogers "Speculative": "1", 392*09625cffSIan Rogers "UMask": "0x10" 393*09625cffSIan Rogers }, 394*09625cffSIan Rogers { 395*09625cffSIan Rogers "BriefDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.", 396*09625cffSIan Rogers "CollectPEBSRecord": "2", 397*09625cffSIan Rogers "Counter": "0,1,2,3", 398*09625cffSIan Rogers "EventCode": "0x60", 399*09625cffSIan Rogers "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", 400*09625cffSIan Rogers "PEBScounters": "0,1,2,3", 401*09625cffSIan Rogers "PublicDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.", 402*09625cffSIan Rogers "SampleAfterValue": "2000003", 403*09625cffSIan Rogers "Speculative": "1", 404*09625cffSIan Rogers "UMask": "0x10" 405*09625cffSIan Rogers }, 406*09625cffSIan Rogers { 407*09625cffSIan Rogers "BriefDescription": "Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache.", 408*09625cffSIan Rogers "CollectPEBSRecord": "2", 409*09625cffSIan Rogers "Counter": "0,1,2,3", 410*09625cffSIan Rogers "CounterMask": "6", 411*09625cffSIan Rogers "EventCode": "0x60", 412*09625cffSIan Rogers "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", 413*09625cffSIan Rogers "PEBScounters": "0,1,2,3", 414*09625cffSIan Rogers "PublicDescription": "Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache. Note that this event does not capture all elapsed cycles while the requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.", 415*09625cffSIan Rogers "SampleAfterValue": "2000003", 416*09625cffSIan Rogers "Speculative": "1", 417*09625cffSIan Rogers "UMask": "0x10" 418*09625cffSIan Rogers }, 419*09625cffSIan Rogers { 420*09625cffSIan Rogers "BriefDescription": "Number of times an RTM execution aborted.", 421*09625cffSIan Rogers "CollectPEBSRecord": "2", 422*09625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 423*09625cffSIan Rogers "EventCode": "0xc9", 424*09625cffSIan Rogers "EventName": "RTM_RETIRED.ABORTED", 425*09625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 426*09625cffSIan Rogers "PublicDescription": "Counts the number of times RTM abort was triggered.", 427*09625cffSIan Rogers "SampleAfterValue": "100003", 428*09625cffSIan Rogers "UMask": "0x4" 429*09625cffSIan Rogers }, 430*09625cffSIan Rogers { 431*09625cffSIan Rogers "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 432*09625cffSIan Rogers "CollectPEBSRecord": "2", 433*09625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 434*09625cffSIan Rogers "EventCode": "0xc9", 435*09625cffSIan Rogers "EventName": "RTM_RETIRED.ABORTED_EVENTS", 436*09625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 437*09625cffSIan Rogers "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 438*09625cffSIan Rogers "SampleAfterValue": "100003", 439cdb29a8fSJin Yao "UMask": "0x80" 440cdb29a8fSJin Yao }, 441cdb29a8fSJin Yao { 442*09625cffSIan Rogers "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 443*09625cffSIan Rogers "CollectPEBSRecord": "2", 444*09625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 445*09625cffSIan Rogers "EventCode": "0xc9", 446*09625cffSIan Rogers "EventName": "RTM_RETIRED.ABORTED_MEM", 447*09625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 448*09625cffSIan Rogers "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 449*09625cffSIan Rogers "SampleAfterValue": "100003", 450*09625cffSIan Rogers "UMask": "0x8" 451*09625cffSIan Rogers }, 452*09625cffSIan Rogers { 453*09625cffSIan Rogers "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 454*09625cffSIan Rogers "CollectPEBSRecord": "2", 455*09625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 456*09625cffSIan Rogers "EventCode": "0xc9", 457*09625cffSIan Rogers "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 458*09625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 459*09625cffSIan Rogers "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.", 460*09625cffSIan Rogers "SampleAfterValue": "100003", 461*09625cffSIan Rogers "UMask": "0x40" 462*09625cffSIan Rogers }, 463*09625cffSIan Rogers { 464*09625cffSIan Rogers "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 465*09625cffSIan Rogers "CollectPEBSRecord": "2", 466*09625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 467*09625cffSIan Rogers "EventCode": "0xc9", 468*09625cffSIan Rogers "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 469*09625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 470*09625cffSIan Rogers "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.", 471*09625cffSIan Rogers "SampleAfterValue": "100003", 472*09625cffSIan Rogers "UMask": "0x20" 473*09625cffSIan Rogers }, 474*09625cffSIan Rogers { 475*09625cffSIan Rogers "BriefDescription": "Number of times an RTM execution successfully committed", 476*09625cffSIan Rogers "CollectPEBSRecord": "2", 477*09625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 478*09625cffSIan Rogers "EventCode": "0xc9", 479*09625cffSIan Rogers "EventName": "RTM_RETIRED.COMMIT", 480*09625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 481*09625cffSIan Rogers "PublicDescription": "Counts the number of times RTM commit succeeded.", 482*09625cffSIan Rogers "SampleAfterValue": "100003", 483*09625cffSIan Rogers "UMask": "0x2" 484*09625cffSIan Rogers }, 485*09625cffSIan Rogers { 486*09625cffSIan Rogers "BriefDescription": "Number of times an RTM execution started.", 487*09625cffSIan Rogers "CollectPEBSRecord": "2", 488*09625cffSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 489*09625cffSIan Rogers "EventCode": "0xc9", 490*09625cffSIan Rogers "EventName": "RTM_RETIRED.START", 491*09625cffSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 492*09625cffSIan Rogers "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.", 493*09625cffSIan Rogers "SampleAfterValue": "100003", 494*09625cffSIan Rogers "UMask": "0x1" 495*09625cffSIan Rogers }, 496*09625cffSIan Rogers { 497cdb29a8fSJin Yao "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region", 498cdb29a8fSJin Yao "CollectPEBSRecord": "2", 499cdb29a8fSJin Yao "Counter": "0,1,2,3,4,5,6,7", 500cdb29a8fSJin Yao "EventCode": "0x5d", 501cdb29a8fSJin Yao "EventName": "TX_EXEC.MISC2", 502cdb29a8fSJin Yao "PEBScounters": "0,1,2,3,4,5,6,7", 503cdb29a8fSJin Yao "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.", 504cdb29a8fSJin Yao "SampleAfterValue": "100003", 505cdb29a8fSJin Yao "Speculative": "1", 506cdb29a8fSJin Yao "UMask": "0x2" 507cdb29a8fSJin Yao }, 508cdb29a8fSJin Yao { 509cdb29a8fSJin Yao "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded", 510cdb29a8fSJin Yao "CollectPEBSRecord": "2", 511cdb29a8fSJin Yao "Counter": "0,1,2,3,4,5,6,7", 512cdb29a8fSJin Yao "EventCode": "0x5d", 513cdb29a8fSJin Yao "EventName": "TX_EXEC.MISC3", 514cdb29a8fSJin Yao "PEBScounters": "0,1,2,3,4,5,6,7", 515cdb29a8fSJin Yao "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.", 516cdb29a8fSJin Yao "SampleAfterValue": "100003", 517cdb29a8fSJin Yao "Speculative": "1", 518cdb29a8fSJin Yao "UMask": "0x4" 519cdb29a8fSJin Yao }, 520cdb29a8fSJin Yao { 521*09625cffSIan Rogers "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads", 522cdb29a8fSJin Yao "CollectPEBSRecord": "2", 523cdb29a8fSJin Yao "Counter": "0,1,2,3", 524*09625cffSIan Rogers "EventCode": "0x54", 525*09625cffSIan Rogers "EventName": "TX_MEM.ABORT_CAPACITY_READ", 526cdb29a8fSJin Yao "PEBScounters": "0,1,2,3", 527*09625cffSIan Rogers "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads", 528cdb29a8fSJin Yao "SampleAfterValue": "100003", 529cdb29a8fSJin Yao "Speculative": "1", 530cdb29a8fSJin Yao "UMask": "0x80" 531cdb29a8fSJin Yao }, 532cdb29a8fSJin Yao { 533*09625cffSIan Rogers "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.", 534cdb29a8fSJin Yao "CollectPEBSRecord": "2", 535*09625cffSIan Rogers "Counter": "0,1,2,3", 536*09625cffSIan Rogers "EventCode": "0x54", 537*09625cffSIan Rogers "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", 538*09625cffSIan Rogers "PEBScounters": "0,1,2,3", 539*09625cffSIan Rogers "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.", 540cdb29a8fSJin Yao "SampleAfterValue": "100003", 541*09625cffSIan Rogers "Speculative": "1", 542*09625cffSIan Rogers "UMask": "0x2" 543cdb29a8fSJin Yao }, 544cdb29a8fSJin Yao { 545*09625cffSIan Rogers "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", 546cdb29a8fSJin Yao "CollectPEBSRecord": "2", 547*09625cffSIan Rogers "Counter": "0,1,2,3", 548*09625cffSIan Rogers "EventCode": "0x54", 549*09625cffSIan Rogers "EventName": "TX_MEM.ABORT_CONFLICT", 550*09625cffSIan Rogers "PEBScounters": "0,1,2,3", 551*09625cffSIan Rogers "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", 552*09625cffSIan Rogers "SampleAfterValue": "100003", 553*09625cffSIan Rogers "Speculative": "1", 554cdb29a8fSJin Yao "UMask": "0x1" 555cdb29a8fSJin Yao } 556cdb29a8fSJin Yao]