1[ 2 { 3 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", 4 "CollectPEBSRecord": "2", 5 "Counter": "0,1,2,3", 6 "EventCode": "0x28", 7 "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", 8 "PEBScounters": "0,1,2,3", 9 "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", 10 "SampleAfterValue": "200003", 11 "Speculative": "1", 12 "UMask": "0x7" 13 }, 14 { 15 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", 16 "CollectPEBSRecord": "2", 17 "Counter": "0,1,2,3", 18 "EventCode": "0x28", 19 "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", 20 "PEBScounters": "0,1,2,3", 21 "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", 22 "SampleAfterValue": "200003", 23 "Speculative": "1", 24 "UMask": "0x18" 25 }, 26 { 27 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", 28 "CollectPEBSRecord": "2", 29 "Counter": "0,1,2,3", 30 "EventCode": "0x28", 31 "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", 32 "PEBScounters": "0,1,2,3", 33 "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.", 34 "SampleAfterValue": "200003", 35 "Speculative": "1", 36 "UMask": "0x20" 37 }, 38 { 39 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", 40 "CollectPEBSRecord": "2", 41 "Counter": "0,1,2,3", 42 "EventCode": "0xB7, 0xBB", 43 "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", 44 "MSRIndex": "0x1a6,0x1a7", 45 "MSRValue": "0x10004", 46 "Offcore": "1", 47 "PEBScounters": "0,1,2,3", 48 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 49 "SampleAfterValue": "100003", 50 "Speculative": "1", 51 "UMask": "0x1" 52 }, 53 { 54 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", 55 "CollectPEBSRecord": "2", 56 "Counter": "0,1,2,3", 57 "EventCode": "0xB7, 0xBB", 58 "EventName": "OCR.DEMAND_CODE_RD.DRAM", 59 "MSRIndex": "0x1a6,0x1a7", 60 "MSRValue": "0x184000004", 61 "Offcore": "1", 62 "PEBScounters": "0,1,2,3", 63 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 64 "SampleAfterValue": "100003", 65 "Speculative": "1", 66 "UMask": "0x1" 67 }, 68 { 69 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", 70 "CollectPEBSRecord": "2", 71 "Counter": "0,1,2,3", 72 "EventCode": "0xB7, 0xBB", 73 "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", 74 "MSRIndex": "0x1a6,0x1a7", 75 "MSRValue": "0x184000004", 76 "Offcore": "1", 77 "PEBScounters": "0,1,2,3", 78 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 79 "SampleAfterValue": "100003", 80 "Speculative": "1", 81 "UMask": "0x1" 82 }, 83 { 84 "BriefDescription": "Counts demand data reads that have any type of response.", 85 "CollectPEBSRecord": "2", 86 "Counter": "0,1,2,3", 87 "EventCode": "0xB7, 0xBB", 88 "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", 89 "MSRIndex": "0x1a6,0x1a7", 90 "MSRValue": "0x10001", 91 "Offcore": "1", 92 "PEBScounters": "0,1,2,3", 93 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 94 "SampleAfterValue": "100003", 95 "Speculative": "1", 96 "UMask": "0x1" 97 }, 98 { 99 "BriefDescription": "Counts demand data reads that DRAM supplied the request.", 100 "CollectPEBSRecord": "2", 101 "Counter": "0,1,2,3", 102 "EventCode": "0xB7, 0xBB", 103 "EventName": "OCR.DEMAND_DATA_RD.DRAM", 104 "MSRIndex": "0x1a6,0x1a7", 105 "MSRValue": "0x184000001", 106 "Offcore": "1", 107 "PEBScounters": "0,1,2,3", 108 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 109 "SampleAfterValue": "100003", 110 "Speculative": "1", 111 "UMask": "0x1" 112 }, 113 { 114 "BriefDescription": "Counts demand data reads that DRAM supplied the request.", 115 "CollectPEBSRecord": "2", 116 "Counter": "0,1,2,3", 117 "EventCode": "0xB7, 0xBB", 118 "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", 119 "MSRIndex": "0x1a6,0x1a7", 120 "MSRValue": "0x184000001", 121 "Offcore": "1", 122 "PEBScounters": "0,1,2,3", 123 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 124 "SampleAfterValue": "100003", 125 "Speculative": "1", 126 "UMask": "0x1" 127 }, 128 { 129 "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", 130 "CollectPEBSRecord": "2", 131 "Counter": "0,1,2,3", 132 "EventCode": "0xB7, 0xBB", 133 "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", 134 "MSRIndex": "0x1a6,0x1a7", 135 "MSRValue": "0x10002", 136 "Offcore": "1", 137 "PEBScounters": "0,1,2,3", 138 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 139 "SampleAfterValue": "100003", 140 "Speculative": "1", 141 "UMask": "0x1" 142 }, 143 { 144 "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", 145 "CollectPEBSRecord": "2", 146 "Counter": "0,1,2,3", 147 "EventCode": "0xB7, 0xBB", 148 "EventName": "OCR.DEMAND_RFO.DRAM", 149 "MSRIndex": "0x1a6,0x1a7", 150 "MSRValue": "0x184000002", 151 "Offcore": "1", 152 "PEBScounters": "0,1,2,3", 153 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 154 "SampleAfterValue": "100003", 155 "Speculative": "1", 156 "UMask": "0x1" 157 }, 158 { 159 "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", 160 "CollectPEBSRecord": "2", 161 "Counter": "0,1,2,3", 162 "EventCode": "0xB7, 0xBB", 163 "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", 164 "MSRIndex": "0x1a6,0x1a7", 165 "MSRValue": "0x184000002", 166 "Offcore": "1", 167 "PEBScounters": "0,1,2,3", 168 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 169 "SampleAfterValue": "100003", 170 "Speculative": "1", 171 "UMask": "0x1" 172 }, 173 { 174 "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.", 175 "CollectPEBSRecord": "2", 176 "Counter": "0,1,2,3", 177 "EventCode": "0xB7, 0xBB", 178 "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", 179 "MSRIndex": "0x1a6,0x1a7", 180 "MSRValue": "0x10400", 181 "Offcore": "1", 182 "PEBScounters": "0,1,2,3", 183 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 184 "SampleAfterValue": "100003", 185 "Speculative": "1", 186 "UMask": "0x1" 187 }, 188 { 189 "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", 190 "CollectPEBSRecord": "2", 191 "Counter": "0,1,2,3", 192 "EventCode": "0xB7, 0xBB", 193 "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", 194 "MSRIndex": "0x1a6,0x1a7", 195 "MSRValue": "0x184000400", 196 "Offcore": "1", 197 "PEBScounters": "0,1,2,3", 198 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 199 "SampleAfterValue": "100003", 200 "Speculative": "1", 201 "UMask": "0x1" 202 }, 203 { 204 "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", 205 "CollectPEBSRecord": "2", 206 "Counter": "0,1,2,3", 207 "EventCode": "0xB7, 0xBB", 208 "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", 209 "MSRIndex": "0x1a6,0x1a7", 210 "MSRValue": "0x184000400", 211 "Offcore": "1", 212 "PEBScounters": "0,1,2,3", 213 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 214 "SampleAfterValue": "100003", 215 "Speculative": "1", 216 "UMask": "0x1" 217 }, 218 { 219 "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.", 220 "CollectPEBSRecord": "2", 221 "Counter": "0,1,2,3", 222 "EventCode": "0xB7, 0xBB", 223 "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", 224 "MSRIndex": "0x1a6,0x1a7", 225 "MSRValue": "0x10010", 226 "Offcore": "1", 227 "PEBScounters": "0,1,2,3", 228 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 229 "SampleAfterValue": "100003", 230 "Speculative": "1", 231 "UMask": "0x1" 232 }, 233 { 234 "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", 235 "CollectPEBSRecord": "2", 236 "Counter": "0,1,2,3", 237 "EventCode": "0xB7, 0xBB", 238 "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", 239 "MSRIndex": "0x1a6,0x1a7", 240 "MSRValue": "0x184000010", 241 "Offcore": "1", 242 "PEBScounters": "0,1,2,3", 243 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 244 "SampleAfterValue": "100003", 245 "Speculative": "1", 246 "UMask": "0x1" 247 }, 248 { 249 "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", 250 "CollectPEBSRecord": "2", 251 "Counter": "0,1,2,3", 252 "EventCode": "0xB7, 0xBB", 253 "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", 254 "MSRIndex": "0x1a6,0x1a7", 255 "MSRValue": "0x184000010", 256 "Offcore": "1", 257 "PEBScounters": "0,1,2,3", 258 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 259 "SampleAfterValue": "100003", 260 "Speculative": "1", 261 "UMask": "0x1" 262 }, 263 { 264 "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that have any type of response.", 265 "CollectPEBSRecord": "2", 266 "Counter": "0,1,2,3", 267 "EventCode": "0xB7, 0xBB", 268 "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", 269 "MSRIndex": "0x1a6,0x1a7", 270 "MSRValue": "0x10020", 271 "Offcore": "1", 272 "PEBScounters": "0,1,2,3", 273 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 274 "SampleAfterValue": "100003", 275 "Speculative": "1", 276 "UMask": "0x1" 277 }, 278 { 279 "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", 280 "CollectPEBSRecord": "2", 281 "Counter": "0,1,2,3", 282 "EventCode": "0xB7, 0xBB", 283 "EventName": "OCR.HWPF_L2_RFO.DRAM", 284 "MSRIndex": "0x1a6,0x1a7", 285 "MSRValue": "0x184000020", 286 "Offcore": "1", 287 "PEBScounters": "0,1,2,3", 288 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 289 "SampleAfterValue": "100003", 290 "Speculative": "1", 291 "UMask": "0x1" 292 }, 293 { 294 "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", 295 "CollectPEBSRecord": "2", 296 "Counter": "0,1,2,3", 297 "EventCode": "0xB7, 0xBB", 298 "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", 299 "MSRIndex": "0x1a6,0x1a7", 300 "MSRValue": "0x184000020", 301 "Offcore": "1", 302 "PEBScounters": "0,1,2,3", 303 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 304 "SampleAfterValue": "100003", 305 "Speculative": "1", 306 "UMask": "0x1" 307 }, 308 { 309 "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.", 310 "CollectPEBSRecord": "2", 311 "Counter": "0,1,2,3", 312 "EventCode": "0xB7, 0xBB", 313 "EventName": "OCR.OTHER.ANY_RESPONSE", 314 "MSRIndex": "0x1a6,0x1a7", 315 "MSRValue": "0x18000", 316 "Offcore": "1", 317 "PEBScounters": "0,1,2,3", 318 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 319 "SampleAfterValue": "100003", 320 "Speculative": "1", 321 "UMask": "0x1" 322 }, 323 { 324 "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", 325 "CollectPEBSRecord": "2", 326 "Counter": "0,1,2,3", 327 "EventCode": "0xB7, 0xBB", 328 "EventName": "OCR.OTHER.DRAM", 329 "MSRIndex": "0x1a6,0x1a7", 330 "MSRValue": "0x184008000", 331 "Offcore": "1", 332 "PEBScounters": "0,1,2,3", 333 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 334 "SampleAfterValue": "100003", 335 "Speculative": "1", 336 "UMask": "0x1" 337 }, 338 { 339 "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", 340 "CollectPEBSRecord": "2", 341 "Counter": "0,1,2,3", 342 "EventCode": "0xB7, 0xBB", 343 "EventName": "OCR.OTHER.LOCAL_DRAM", 344 "MSRIndex": "0x1a6,0x1a7", 345 "MSRValue": "0x184008000", 346 "Offcore": "1", 347 "PEBScounters": "0,1,2,3", 348 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 349 "SampleAfterValue": "100003", 350 "Speculative": "1", 351 "UMask": "0x1" 352 }, 353 { 354 "BriefDescription": "Counts streaming stores that have any type of response.", 355 "CollectPEBSRecord": "2", 356 "Counter": "0,1,2,3", 357 "EventCode": "0xB7, 0xBB", 358 "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", 359 "MSRIndex": "0x1a6,0x1a7", 360 "MSRValue": "0x10800", 361 "Offcore": "1", 362 "PEBScounters": "0,1,2,3", 363 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 364 "SampleAfterValue": "100003", 365 "Speculative": "1", 366 "UMask": "0x1" 367 }, 368 { 369 "BriefDescription": "Counts streaming stores that DRAM supplied the request.", 370 "CollectPEBSRecord": "2", 371 "Counter": "0,1,2,3", 372 "EventCode": "0xB7, 0xBB", 373 "EventName": "OCR.STREAMING_WR.DRAM", 374 "MSRIndex": "0x1a6,0x1a7", 375 "MSRValue": "0x184000800", 376 "Offcore": "1", 377 "PEBScounters": "0,1,2,3", 378 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 379 "SampleAfterValue": "100003", 380 "Speculative": "1", 381 "UMask": "0x1" 382 }, 383 { 384 "BriefDescription": "Counts streaming stores that DRAM supplied the request.", 385 "CollectPEBSRecord": "2", 386 "Counter": "0,1,2,3", 387 "EventCode": "0xB7, 0xBB", 388 "EventName": "OCR.STREAMING_WR.LOCAL_DRAM", 389 "MSRIndex": "0x1a6,0x1a7", 390 "MSRValue": "0x184000800", 391 "Offcore": "1", 392 "PEBScounters": "0,1,2,3", 393 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 394 "SampleAfterValue": "100003", 395 "Speculative": "1", 396 "UMask": "0x1" 397 } 398] 399